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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2010 |
0ad775db HC |
4 | * |
5 | * Author(s): Hartmut Penner <hp@de.ibm.com> | |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com> | |
7 | * Rob van der Heij <rvdhei@iae.nl> | |
8 | * Heiko Carstens <heiko.carstens@de.ibm.com> | |
1da177e4 | 9 | * |
1da177e4 LT |
10 | */ |
11 | ||
1844c9bc | 12 | #include <linux/init.h> |
144d634a | 13 | #include <linux/linkage.h> |
1844c9bc MS |
14 | #include <asm/asm-offsets.h> |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/page.h> | |
4e62d458 | 17 | #include <asm/ptrace.h> |
b1b70306 | 18 | |
1844c9bc | 19 | __HEAD |
144d634a | 20 | ENTRY(startup_continue) |
7a76aa95 | 21 | tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ? |
e22cf8ca CB |
22 | jz 0f |
23 | xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid | |
24 | mvi __LC_LPP,0x80 # and set LPP_MAGIC | |
25 | .insn s,0xb2800000,__LC_LPP # load program parameter | |
6e2ef5e4 MS |
26 | 0: larl %r1,tod_clock_base |
27 | mvc 0(16,%r1),__LC_BOOT_CLOCK | |
1844c9bc | 28 | larl %r13,.LPG1 # get base |
25d83cbf | 29 | lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers |
0aaba41b | 30 | larl %r0,boot_vdso_data |
c742b31c | 31 | stg %r0,__LC_VDSO_PER_CPU |
e87bfe51 HC |
32 | # |
33 | # Setup stack | |
34 | # | |
d5c352cd | 35 | larl %r14,init_task |
25d83cbf | 36 | stg %r14,__LC_CURRENT |
ce3dc447 | 37 | larl %r15,init_thread_union+THREAD_SIZE-STACK_FRAME_OVERHEAD |
1da177e4 | 38 | # |
971a9ca6 HC |
39 | # Early setup functions that may not rely on an initialized bss section, |
40 | # like moving the initrd. Returns with an initialized bss section. | |
41 | # | |
42 | brasl %r14,startup_init_nobss | |
43 | # | |
44 | # Early machine initialization and detection functions. | |
1da177e4 | 45 | # |
fe355b7f | 46 | brasl %r14,startup_init |
c9497864 VG |
47 | |
48 | # check control registers | |
49 | stctg %c0,%c15,0(%r15) | |
50 | oi 6(%r15),0x60 # enable sigp emergency & external call | |
51 | oi 4(%r15),0x10 # switch on low address proctection | |
52 | lctlg %c0,%c15,0(%r15) | |
53 | ||
54 | lam 0,15,.Laregs-.LPG1(%r13) # load acrs needed by uaccess | |
55 | brasl %r14,start_kernel # go to C code | |
56 | # | |
57 | # We returned from start_kernel ?!? PANIK | |
58 | # | |
59 | basr %r13,0 | |
60 | lpswe .Ldw-.(%r13) # load disabled wait psw | |
61 | ||
25d83cbf | 62 | .align 16 |
1844c9bc | 63 | .LPG1: |
c76e70d3 | 64 | .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space |
25d83cbf HC |
65 | .quad 0 # cr1: primary space segment table |
66 | .quad .Lduct # cr2: dispatchable unit control table | |
67 | .quad 0 # cr3: instruction authorization | |
df26c2e8 | 68 | .quad 0xffff # cr4: instruction authorization |
482b05dd | 69 | .quad .Lduct # cr5: primary-aste origin |
25d83cbf HC |
70 | .quad 0 # cr6: I/O interrupts |
71 | .quad 0 # cr7: secondary space segment table | |
72 | .quad 0 # cr8: access registers translation | |
73 | .quad 0 # cr9: tracing off | |
74 | .quad 0 # cr10: tracing off | |
75 | .quad 0 # cr11: tracing off | |
76 | .quad 0 # cr12: tracing off | |
77 | .quad 0 # cr13: home space segment table | |
78 | .quad 0xc0000000 # cr14: machine check handling off | |
8d7f6690 | 79 | .quad .Llinkage_stack # cr15: linkage stack operations |
25d83cbf | 80 | .Lpcmsk:.quad 0x0000000180000000 |
1da177e4 | 81 | .L4malign:.quad 0xffffffffffc00000 |
25d83cbf HC |
82 | .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 |
83 | .Lnop: .long 0x07000700 | |
b1b70306 HC |
84 | .Lparmaddr: |
85 | .quad PARMAREA | |
482b05dd | 86 | .align 64 |
8d7f6690 | 87 | .Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0 |
482b05dd | 88 | .long 0,0,0,0,0,0,0,0 |
8d7f6690 | 89 | .Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0 |
482b05dd GS |
90 | .align 128 |
91 | .Lduald:.rept 8 | |
92 | .long 0x80000000,0,0,0 # invalid access-list entries | |
93 | .endr | |
8d7f6690 MS |
94 | .Llinkage_stack: |
95 | .long 0,0,0x89000000,0,0,0,0x8a000000,0 | |
25d83cbf HC |
96 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 |
97 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |