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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ad775db | 2 | * arch/s390/kernel/head64.S |
1da177e4 | 3 | * |
b1b70306 | 4 | * Copyright (C) IBM Corp. 1999,2006 |
0ad775db HC |
5 | * |
6 | * Author(s): Hartmut Penner <hp@de.ibm.com> | |
7 | * Martin Schwidefsky <schwidefsky@de.ibm.com> | |
8 | * Rob van der Heij <rvdhei@iae.nl> | |
9 | * Heiko Carstens <heiko.carstens@de.ibm.com> | |
1da177e4 | 10 | * |
1da177e4 LT |
11 | */ |
12 | ||
25d83cbf | 13 | .org 0x11000 |
b1b70306 HC |
14 | |
15 | startup_continue: | |
25d83cbf HC |
16 | basr %r13,0 # get base |
17 | .LPG1: sll %r13,1 # remove high order bit | |
18 | srl %r13,1 | |
411ed322 MH |
19 | |
20 | #ifdef CONFIG_ZFCPDUMP | |
21 | ||
22 | # check if we have been ipled using zfcp dump: | |
23 | ||
24 | tm 0xb9,0x01 # test if subchannel is enabled | |
25 | jno .nodump # subchannel disabled | |
26 | l %r1,0xb8 | |
27 | la %r5,.Lipl_schib-.LPG1(%r13) | |
28 | stsch 0(%r5) # get schib of subchannel | |
29 | jne .nodump # schib not available | |
30 | tm 5(%r5),0x01 # devno valid? | |
31 | jno .nodump | |
32 | tm 4(%r5),0x80 # qdio capable device? | |
33 | jno .nodump | |
34 | l %r2,20(%r0) # address of ipl parameter block | |
35 | lhi %r3,0 | |
36 | ic %r3,0x148(%r2) # get opt field | |
37 | chi %r3,0x20 # load with dump? | |
38 | jne .nodump | |
39 | ||
40 | # store all prefix registers in case of load with dump: | |
41 | ||
42 | la %r7,0 # base register for 0 page | |
43 | la %r8,0 # first cpu | |
44 | l %r11,.Lpref_arr_ptr-.LPG1(%r13) # address of prefix array | |
45 | ahi %r11,4 # skip boot cpu | |
46 | lr %r12,%r11 | |
47 | ahi %r12,(CONFIG_NR_CPUS*4) # end of prefix array | |
48 | stap .Lcurrent_cpu+2-.LPG1(%r13) # store current cpu addr | |
49 | 1: | |
50 | cl %r8,.Lcurrent_cpu-.LPG1(%r13) # is ipl cpu ? | |
51 | je 4f # if yes get next cpu | |
52 | 2: | |
53 | lr %r9,%r7 | |
54 | sigp %r9,%r8,0x9 # stop & store status of cpu | |
55 | brc 8,3f # accepted | |
56 | brc 4,4f # status stored: next cpu | |
57 | brc 2,2b # busy: try again | |
58 | brc 1,4f # not op: next cpu | |
59 | 3: | |
60 | mvc 0(4,%r11),264(%r7) # copy prefix register to prefix array | |
61 | ahi %r11,4 # next element in prefix array | |
62 | clr %r11,%r12 | |
63 | je 5f # no more space in prefix array | |
64 | 4: | |
65 | ahi %r8,1 # next cpu (r8 += 1) | |
66 | cl %r8,.Llast_cpu-.LPG1(%r13) # is last possible cpu ? | |
67 | jl 1b # jump if not last cpu | |
68 | 5: | |
69 | lhi %r1,2 # mode 2 = esame (dump) | |
70 | j 6f | |
71 | .align 4 | |
72 | .Lipl_schib: | |
73 | .rept 13 | |
74 | .long 0 | |
75 | .endr | |
76 | .nodump: | |
77 | lhi %r1,1 # mode 1 = esame (normal ipl) | |
78 | 6: | |
79 | #else | |
80 | lhi %r1,1 # mode 1 = esame (normal ipl) | |
81 | #endif /* CONFIG_ZFCPDUMP */ | |
25d83cbf HC |
82 | mvi __LC_AR_MODE_ID,1 # set esame flag |
83 | slr %r0,%r0 # set cpuid to zero | |
84 | sigp %r1,%r0,0x12 # switch to esame mode | |
85 | sam64 # switch to 64 bit mode | |
86 | lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers | |
87 | lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area | |
88 | # move IPL device to lowcore | |
c742b31c MS |
89 | lghi %r0,__LC_PASTE |
90 | stg %r0,__LC_VDSO_PER_CPU | |
e87bfe51 HC |
91 | # |
92 | # Setup stack | |
93 | # | |
25d83cbf HC |
94 | larl %r15,init_thread_union |
95 | lg %r14,__TI_task(%r15) # cache current in lowcore | |
96 | stg %r14,__LC_CURRENT | |
97 | aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE | |
98 | stg %r15,__LC_KERNEL_STACK # set end of kernel stack | |
99 | aghi %r15,-160 | |
1da177e4 | 100 | # |
fe355b7f HY |
101 | # Save ipl parameters, clear bss memory, initialize storage key for kernel pages, |
102 | # and create a kernel NSS if the SAVESYS= parm is defined | |
1da177e4 | 103 | # |
fe355b7f | 104 | brasl %r14,startup_init |
25d83cbf HC |
105 | lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space, |
106 | # virtual and never return ... | |
107 | .align 16 | |
108 | .Lentry:.quad 0x0000000180000000,_stext | |
53492b1d | 109 | .Lctl: .quad 0x04350002 # cr0: various things |
25d83cbf HC |
110 | .quad 0 # cr1: primary space segment table |
111 | .quad .Lduct # cr2: dispatchable unit control table | |
112 | .quad 0 # cr3: instruction authorization | |
113 | .quad 0 # cr4: instruction authorization | |
482b05dd | 114 | .quad .Lduct # cr5: primary-aste origin |
25d83cbf HC |
115 | .quad 0 # cr6: I/O interrupts |
116 | .quad 0 # cr7: secondary space segment table | |
117 | .quad 0 # cr8: access registers translation | |
118 | .quad 0 # cr9: tracing off | |
119 | .quad 0 # cr10: tracing off | |
120 | .quad 0 # cr11: tracing off | |
121 | .quad 0 # cr12: tracing off | |
122 | .quad 0 # cr13: home space segment table | |
123 | .quad 0xc0000000 # cr14: machine check handling off | |
124 | .quad 0 # cr15: linkage stack operations | |
25d83cbf | 125 | .Lpcmsk:.quad 0x0000000180000000 |
1da177e4 | 126 | .L4malign:.quad 0xffffffffffc00000 |
25d83cbf HC |
127 | .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 |
128 | .Lnop: .long 0x07000700 | |
411ed322 MH |
129 | #ifdef CONFIG_ZFCPDUMP |
130 | .Lcurrent_cpu: | |
131 | .long 0x0 | |
132 | .Llast_cpu: | |
133 | .long 0x0000ffff | |
134 | .Lpref_arr_ptr: | |
135 | .long zfcpdump_prefix_array | |
136 | #endif /* CONFIG_ZFCPDUMP */ | |
b1b70306 HC |
137 | .Lparmaddr: |
138 | .quad PARMAREA | |
482b05dd GS |
139 | .align 64 |
140 | .Lduct: .long 0,0,0,0,.Lduald,0,0,0 | |
141 | .long 0,0,0,0,0,0,0,0 | |
142 | .align 128 | |
143 | .Lduald:.rept 8 | |
144 | .long 0x80000000,0,0,0 # invalid access-list entries | |
145 | .endr | |
1da177e4 | 146 | |
dc8f5d21 | 147 | .org 0x12000 |
615b04b3 HC |
148 | .globl _ehead |
149 | _ehead: | |
1da177e4 | 150 | #ifdef CONFIG_SHARED_KERNEL |
25d83cbf | 151 | .org 0x100000 |
1da177e4 | 152 | #endif |
25d83cbf | 153 | |
1da177e4 | 154 | # |
b1b70306 | 155 | # startup-code, running in absolute addressing mode |
1da177e4 | 156 | # |
25d83cbf HC |
157 | .globl _stext |
158 | _stext: basr %r13,0 # get base | |
1e8e3383 | 159 | .LPG3: |
1da177e4 | 160 | # check control registers |
25d83cbf HC |
161 | stctg %c0,%c15,0(%r15) |
162 | oi 6(%r15),0x40 # enable sigp emergency signal | |
163 | oi 4(%r15),0x10 # switch on low address proctection | |
164 | lctlg %c0,%c15,0(%r15) | |
1da177e4 | 165 | |
25d83cbf HC |
166 | lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess |
167 | brasl %r14,start_kernel # go to C code | |
1da177e4 LT |
168 | # |
169 | # We returned from start_kernel ?!? PANIK | |
170 | # | |
25d83cbf HC |
171 | basr %r13,0 |
172 | lpswe .Ldw-.(%r13) # load disabled wait psw | |
e87bfe51 | 173 | |
25d83cbf HC |
174 | .align 8 |
175 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 | |
176 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |