projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| a53c8fab | 2 | * Copyright IBM Corp. 1999, 2010 |
| 0ad775db HC |
3 | * |
| 4 | * Author(s): Hartmut Penner <hp@de.ibm.com> | |
| 5 | * Martin Schwidefsky <schwidefsky@de.ibm.com> | |
| 6 | * Rob van der Heij <rvdhei@iae.nl> | |
| 7 | * Heiko Carstens <heiko.carstens@de.ibm.com> | |
| 1da177e4 | 8 | * |
| 1da177e4 LT |
9 | */ |
| 10 | ||
| 1844c9bc | 11 | #include <linux/init.h> |
| 144d634a | 12 | #include <linux/linkage.h> |
| 1844c9bc MS |
13 | #include <asm/asm-offsets.h> |
| 14 | #include <asm/thread_info.h> | |
| 15 | #include <asm/page.h> | |
| b1b70306 | 16 | |
| 1844c9bc | 17 | __HEAD |
| 144d634a | 18 | ENTRY(startup_continue) |
| 7a76aa95 | 19 | tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ? |
| e22cf8ca CB |
20 | jz 0f |
| 21 | xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid | |
| 22 | mvi __LC_LPP,0x80 # and set LPP_MAGIC | |
| 23 | .insn s,0xb2800000,__LC_LPP # load program parameter | |
| 24 | 0: larl %r1,sched_clock_base_cc | |
| 1844c9bc MS |
25 | mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK |
| 26 | larl %r13,.LPG1 # get base | |
| 25d83cbf HC |
27 | lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers |
| 28 | lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area | |
| 29 | # move IPL device to lowcore | |
| c742b31c MS |
30 | lghi %r0,__LC_PASTE |
| 31 | stg %r0,__LC_VDSO_PER_CPU | |
| e87bfe51 HC |
32 | # |
| 33 | # Setup stack | |
| 34 | # | |
| d5c352cd | 35 | larl %r14,init_task |
| 25d83cbf | 36 | stg %r14,__LC_CURRENT |
| d5c352cd | 37 | larl %r15,init_thread_union |
| 3a890380 | 38 | aghi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER) # init_task_union + THREAD_SIZE |
| 25d83cbf HC |
39 | stg %r15,__LC_KERNEL_STACK # set end of kernel stack |
| 40 | aghi %r15,-160 | |
| 1da177e4 | 41 | # |
| fe355b7f HY |
42 | # Save ipl parameters, clear bss memory, initialize storage key for kernel pages, |
| 43 | # and create a kernel NSS if the SAVESYS= parm is defined | |
| 1da177e4 | 44 | # |
| fe355b7f | 45 | brasl %r14,startup_init |
| 25d83cbf HC |
46 | lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space, |
| 47 | # virtual and never return ... | |
| 48 | .align 16 | |
| 1844c9bc | 49 | .LPG1: |
| 25d83cbf | 50 | .Lentry:.quad 0x0000000180000000,_stext |
| c76e70d3 | 51 | .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space |
| 25d83cbf HC |
52 | .quad 0 # cr1: primary space segment table |
| 53 | .quad .Lduct # cr2: dispatchable unit control table | |
| 54 | .quad 0 # cr3: instruction authorization | |
| df26c2e8 | 55 | .quad 0xffff # cr4: instruction authorization |
| 482b05dd | 56 | .quad .Lduct # cr5: primary-aste origin |
| 25d83cbf HC |
57 | .quad 0 # cr6: I/O interrupts |
| 58 | .quad 0 # cr7: secondary space segment table | |
| 59 | .quad 0 # cr8: access registers translation | |
| 60 | .quad 0 # cr9: tracing off | |
| 61 | .quad 0 # cr10: tracing off | |
| 62 | .quad 0 # cr11: tracing off | |
| 63 | .quad 0 # cr12: tracing off | |
| 64 | .quad 0 # cr13: home space segment table | |
| 65 | .quad 0xc0000000 # cr14: machine check handling off | |
| 8d7f6690 | 66 | .quad .Llinkage_stack # cr15: linkage stack operations |
| 25d83cbf | 67 | .Lpcmsk:.quad 0x0000000180000000 |
| 1da177e4 | 68 | .L4malign:.quad 0xffffffffffc00000 |
| 25d83cbf HC |
69 | .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 |
| 70 | .Lnop: .long 0x07000700 | |
| b1b70306 HC |
71 | .Lparmaddr: |
| 72 | .quad PARMAREA | |
| 482b05dd | 73 | .align 64 |
| 8d7f6690 | 74 | .Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0 |
| 482b05dd | 75 | .long 0,0,0,0,0,0,0,0 |
| 8d7f6690 | 76 | .Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0 |
| 482b05dd GS |
77 | .align 128 |
| 78 | .Lduald:.rept 8 | |
| 79 | .long 0x80000000,0,0,0 # invalid access-list entries | |
| 80 | .endr | |
| 8d7f6690 MS |
81 | .Llinkage_stack: |
| 82 | .long 0,0,0x89000000,0,0,0,0x8a000000,0 | |
| 1da177e4 | 83 | |
| 144d634a | 84 | ENTRY(_ehead) |
| 1844c9bc | 85 | |
| 57d84906 | 86 | .org 0x100000 - 0x11000 # head.o ends at 0x11000 |
| 1da177e4 | 87 | # |
| b1b70306 | 88 | # startup-code, running in absolute addressing mode |
| 1da177e4 | 89 | # |
| 144d634a JG |
90 | ENTRY(_stext) |
| 91 | basr %r13,0 # get base | |
| 1e8e3383 | 92 | .LPG3: |
| 1da177e4 | 93 | # check control registers |
| 25d83cbf | 94 | stctg %c0,%c15,0(%r15) |
| d98e19cc | 95 | oi 6(%r15),0x60 # enable sigp emergency & external call |
| 25d83cbf HC |
96 | oi 4(%r15),0x10 # switch on low address proctection |
| 97 | lctlg %c0,%c15,0(%r15) | |
| 1da177e4 | 98 | |
| 25d83cbf HC |
99 | lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess |
| 100 | brasl %r14,start_kernel # go to C code | |
| 1da177e4 LT |
101 | # |
| 102 | # We returned from start_kernel ?!? PANIK | |
| 103 | # | |
| 25d83cbf HC |
104 | basr %r13,0 |
| 105 | lpswe .Ldw-.(%r13) # load disabled wait psw | |
| e87bfe51 | 106 | |
| 25d83cbf HC |
107 | .align 8 |
| 108 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 | |
| 109 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |