[mirror_ubuntu-bionic-kernel.git] / arch / s390 / kernel / perf_cpum_cf.c

/*
 * Performance event support for s390x - CPU-measurement Counter Facility
 *
 *  Copyright IBM Corp. 2012
 *  Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
 * as published by the Free Software Foundation.
 */
#define KMSG_COMPONENT	"cpum_cf"
#define pr_fmt(fmt)	KMSG_COMPONENT ": " fmt

#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/perf_event.h>
#include <linux/percpu.h>
#include <linux/notifier.h>
#include <linux/init.h>
#include <linux/export.h>
#include <asm/ctl_reg.h>
#include <asm/irq.h>
#include <asm/cpu_mf.h>

/* CPU-measurement counter facility supports these CPU counter sets:
 * For CPU counter sets:
 *    Basic counter set:	     0-31
 *    Problem-state counter set:    32-63
 *    Crypto-activity counter set:  64-127
 *    Extented counter set:	   128-159
 */
enum cpumf_ctr_set {
	/* CPU counter sets */
	CPUMF_CTR_SET_BASIC   = 0,
	CPUMF_CTR_SET_USER    = 1,
	CPUMF_CTR_SET_CRYPTO  = 2,
	CPUMF_CTR_SET_EXT     = 3,

	/* Maximum number of counter sets */
	CPUMF_CTR_SET_MAX,
};

#define CPUMF_LCCTL_ENABLE_SHIFT    16
#define CPUMF_LCCTL_ACTCTL_SHIFT     0
static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = {
	[CPUMF_CTR_SET_BASIC]	= 0x02,
	[CPUMF_CTR_SET_USER]	= 0x04,
	[CPUMF_CTR_SET_CRYPTO]	= 0x08,
	[CPUMF_CTR_SET_EXT]	= 0x01,
};

static void ctr_set_enable(u64 *state, int ctr_set)
{
	*state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT;
}
static void ctr_set_disable(u64 *state, int ctr_set)
{
	*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT);
}
static void ctr_set_start(u64 *state, int ctr_set)
{
	*state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT;
}
static void ctr_set_stop(u64 *state, int ctr_set)
{
	*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT);
}

/* Local CPUMF event structure */
struct cpu_hw_events {
	struct cpumf_ctr_info	info;
	atomic_t		ctr_set[CPUMF_CTR_SET_MAX];
	u64			state, tx_state;
	unsigned int		flags;
	unsigned int		txn_flags;
};
static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
	.ctr_set = {
		[CPUMF_CTR_SET_BASIC]  = ATOMIC_INIT(0),
		[CPUMF_CTR_SET_USER]   = ATOMIC_INIT(0),
		[CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0),
		[CPUMF_CTR_SET_EXT]    = ATOMIC_INIT(0),
	},
	.state = 0,
	.flags = 0,
	.txn_flags = 0,
};

static int get_counter_set(u64 event)
{
	int set = -1;

	if (event < 32)
		set = CPUMF_CTR_SET_BASIC;
	else if (event < 64)
		set = CPUMF_CTR_SET_USER;
	else if (event < 128)
		set = CPUMF_CTR_SET_CRYPTO;
	else if (event < 256)
		set = CPUMF_CTR_SET_EXT;

	return set;
}

static int validate_event(const struct hw_perf_event *hwc)
{
	switch (hwc->config_base) {
	case CPUMF_CTR_SET_BASIC:
	case CPUMF_CTR_SET_USER:
	case CPUMF_CTR_SET_CRYPTO:
	case CPUMF_CTR_SET_EXT:
		/* check for reserved counters */
		if ((hwc->config >=  6 && hwc->config <=  31) ||
		    (hwc->config >= 38 && hwc->config <=  63) ||
		    (hwc->config >= 80 && hwc->config <= 127))
			return -EOPNOTSUPP;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int validate_ctr_version(const struct hw_perf_event *hwc)
{
	struct cpu_hw_events *cpuhw;
	int err = 0;

	cpuhw = &get_cpu_var(cpu_hw_events);

	/* check required version for counter sets */
	switch (hwc->config_base) {
	case CPUMF_CTR_SET_BASIC:
	case CPUMF_CTR_SET_USER:
		if (cpuhw->info.cfvn < 1)
			err = -EOPNOTSUPP;
		break;
	case CPUMF_CTR_SET_CRYPTO:
	case CPUMF_CTR_SET_EXT:
		if (cpuhw->info.csvn < 1)
			err = -EOPNOTSUPP;
		if ((cpuhw->info.csvn == 1 && hwc->config > 159) ||
		    (cpuhw->info.csvn == 2 && hwc->config > 175) ||
		    (cpuhw->info.csvn  > 2 && hwc->config > 255))
			err = -EOPNOTSUPP;
		break;
	}

	put_cpu_var(cpu_hw_events);
	return err;
}

static int validate_ctr_auth(const struct hw_perf_event *hwc)
{
	struct cpu_hw_events *cpuhw;
	u64 ctrs_state;
	int err = 0;

	cpuhw = &get_cpu_var(cpu_hw_events);

	/* check authorization for cpu counter sets */
	ctrs_state = cpumf_state_ctl[hwc->config_base];
	if (!(ctrs_state & cpuhw->info.auth_ctl))
		err = -EPERM;

	put_cpu_var(cpu_hw_events);
	return err;
}

/*
 * Change the CPUMF state to active.
 * Enable and activate the CPU-counter sets according
 * to the per-cpu control state.
 */
static void cpumf_pmu_enable(struct pmu *pmu)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
	int err;

	if (cpuhw->flags & PMU_F_ENABLED)
		return;

	err = lcctl(cpuhw->state);
	if (err) {
		pr_err("Enabling the performance measuring unit "
		       "failed with rc=%x\n", err);
		return;
	}

	cpuhw->flags |= PMU_F_ENABLED;
}

/*
 * Change the CPUMF state to inactive.
 * Disable and enable (inactive) the CPU-counter sets according
 * to the per-cpu control state.
 */
static void cpumf_pmu_disable(struct pmu *pmu)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
	int err;
	u64 inactive;

	if (!(cpuhw->flags & PMU_F_ENABLED))
		return;

	inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
	err = lcctl(inactive);
	if (err) {
		pr_err("Disabling the performance measuring unit "
		       "failed with rc=%x\n", err);
		return;
	}

	cpuhw->flags &= ~PMU_F_ENABLED;
}


/* Number of perf events counting hardware events */
static atomic_t num_events = ATOMIC_INIT(0);
/* Used to avoid races in calling reserve/release_cpumf_hardware */
static DEFINE_MUTEX(pmc_reserve_mutex);

/* CPU-measurement alerts for the counter facility */
static void cpumf_measurement_alert(struct ext_code ext_code,
				    unsigned int alert, unsigned long unused)
{
	struct cpu_hw_events *cpuhw;

	if (!(alert & CPU_MF_INT_CF_MASK))
		return;

	inc_irq_stat(IRQEXT_CMC);
	cpuhw = this_cpu_ptr(&cpu_hw_events);

	/* Measurement alerts are shared and might happen when the PMU
	 * is not reserved.  Ignore these alerts in this case. */
	if (!(cpuhw->flags & PMU_F_RESERVED))
		return;

	/* counter authorization change alert */
	if (alert & CPU_MF_INT_CF_CACA)
		qctri(&cpuhw->info);

	/* loss of counter data alert */
	if (alert & CPU_MF_INT_CF_LCDA)
		pr_err("CPU[%i] Counter data was lost\n", smp_processor_id());
}

#define PMC_INIT      0
#define PMC_RELEASE   1
static void setup_pmc_cpu(void *flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);

	switch (*((int *) flags)) {
	case PMC_INIT:
		memset(&cpuhw->info, 0, sizeof(cpuhw->info));
		qctri(&cpuhw->info);
		cpuhw->flags |= PMU_F_RESERVED;
		break;

	case PMC_RELEASE:
		cpuhw->flags &= ~PMU_F_RESERVED;
		break;
	}

	/* Disable CPU counter sets */
	lcctl(0);
}

/* Initialize the CPU-measurement facility */
static int reserve_pmc_hardware(void)
{
	int flags = PMC_INIT;

	on_each_cpu(setup_pmc_cpu, &flags, 1);
	irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT);

	return 0;
}

/* Release the CPU-measurement facility */
static void release_pmc_hardware(void)
{
	int flags = PMC_RELEASE;

	on_each_cpu(setup_pmc_cpu, &flags, 1);
	irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT);
}

/* Release the PMU if event is the last perf event */
static void hw_perf_event_destroy(struct perf_event *event)
{
	if (!atomic_add_unless(&num_events, -1, 1)) {
		mutex_lock(&pmc_reserve_mutex);
		if (atomic_dec_return(&num_events) == 0)
			release_pmc_hardware();
		mutex_unlock(&pmc_reserve_mutex);
	}
}

/* CPUMF <-> perf event mappings for kernel+userspace (basic set) */
static const int cpumf_generic_events_basic[] = {
	[PERF_COUNT_HW_CPU_CYCLES]	    = 0,
	[PERF_COUNT_HW_INSTRUCTIONS]	    = 1,
	[PERF_COUNT_HW_CACHE_REFERENCES]    = -1,
	[PERF_COUNT_HW_CACHE_MISSES]	    = -1,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
	[PERF_COUNT_HW_BRANCH_MISSES]	    = -1,
	[PERF_COUNT_HW_BUS_CYCLES]	    = -1,
};
/* CPUMF <-> perf event mappings for userspace (problem-state set) */
static const int cpumf_generic_events_user[] = {
	[PERF_COUNT_HW_CPU_CYCLES]	    = 32,
	[PERF_COUNT_HW_INSTRUCTIONS]	    = 33,
	[PERF_COUNT_HW_CACHE_REFERENCES]    = -1,
	[PERF_COUNT_HW_CACHE_MISSES]	    = -1,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
	[PERF_COUNT_HW_BRANCH_MISSES]	    = -1,
	[PERF_COUNT_HW_BUS_CYCLES]	    = -1,
};

static int __hw_perf_event_init(struct perf_event *event)
{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	int err;
	u64 ev;

	switch (attr->type) {
	case PERF_TYPE_RAW:
		/* Raw events are used to access counters directly,
		 * hence do not permit excludes */
		if (attr->exclude_kernel || attr->exclude_user ||
		    attr->exclude_hv)
			return -EOPNOTSUPP;
		ev = attr->config;
		break;

	case PERF_TYPE_HARDWARE:
		ev = attr->config;
		/* Count user space (problem-state) only */
		if (!attr->exclude_user && attr->exclude_kernel) {
			if (ev >= ARRAY_SIZE(cpumf_generic_events_user))
				return -EOPNOTSUPP;
			ev = cpumf_generic_events_user[ev];

		/* No support for kernel space counters only */
		} else if (!attr->exclude_kernel && attr->exclude_user) {
			return -EOPNOTSUPP;

		/* Count user and kernel space */
		} else {
			if (ev >= ARRAY_SIZE(cpumf_generic_events_basic))
				return -EOPNOTSUPP;
			ev = cpumf_generic_events_basic[ev];
		}
		break;

	default:
		return -ENOENT;
	}

	if (ev == -1)
		return -ENOENT;

	if (ev >= PERF_CPUM_CF_MAX_CTR)
		return -EINVAL;

	/* Use the hardware perf event structure to store the counter number
	 * in 'config' member and the counter set to which the counter belongs
	 * in the 'config_base'.  The counter set (config_base) is then used
	 * to enable/disable the counters.
	 */
	hwc->config = ev;
	hwc->config_base = get_counter_set(ev);

	/* Validate the counter that is assigned to this event.
	 * Because the counter facility can use numerous counters at the
	 * same time without constraints, it is not necessary to explicity
	 * validate event groups (event->group_leader != event).
	 */
	err = validate_event(hwc);
	if (err)
		return err;

	/* Initialize for using the CPU-measurement counter facility */
	if (!atomic_inc_not_zero(&num_events)) {
		mutex_lock(&pmc_reserve_mutex);
		if (atomic_read(&num_events) == 0 && reserve_pmc_hardware())
			err = -EBUSY;
		else
			atomic_inc(&num_events);
		mutex_unlock(&pmc_reserve_mutex);
	}
	event->destroy = hw_perf_event_destroy;

	/* Finally, validate version and authorization of the counter set */
	err = validate_ctr_auth(hwc);
	if (!err)
		err = validate_ctr_version(hwc);

	return err;
}

static int cpumf_pmu_event_init(struct perf_event *event)
{
	int err;

	switch (event->attr.type) {
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
	case PERF_TYPE_RAW:
		err = __hw_perf_event_init(event);
		break;
	default:
		return -ENOENT;
	}

	if (unlikely(err) && event->destroy)
		event->destroy(event);

	return err;
}

static int hw_perf_event_reset(struct perf_event *event)
{
	u64 prev, new;
	int err;

	do {
		prev = local64_read(&event->hw.prev_count);
		err = ecctr(event->hw.config, &new);
		if (err) {
			if (err != 3)
				break;
			/* The counter is not (yet) available. This
			 * might happen if the counter set to which
			 * this counter belongs is in the disabled
			 * state.
			 */
			new = 0;
		}
	} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);

	return err;
}

static int hw_perf_event_update(struct perf_event *event)
{
	u64 prev, new, delta;
	int err;

	do {
		prev = local64_read(&event->hw.prev_count);
		err = ecctr(event->hw.config, &new);
		if (err)
			goto out;
	} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);

	delta = (prev <= new) ? new - prev
			      : (-1ULL - prev) + new + 1;	 /* overflow */
	local64_add(delta, &event->count);
out:
	return err;
}

static void cpumf_pmu_read(struct perf_event *event)
{
	if (event->hw.state & PERF_HES_STOPPED)
		return;

	hw_perf_event_update(event);
}

static void cpumf_pmu_start(struct perf_event *event, int flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;

	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(hwc->config == -1))
		return;

	if (flags & PERF_EF_RELOAD)
		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));

	hwc->state = 0;

	/* (Re-)enable and activate the counter set */
	ctr_set_enable(&cpuhw->state, hwc->config_base);
	ctr_set_start(&cpuhw->state, hwc->config_base);

	/* The counter set to which this counter belongs can be already active.
	 * Because all counters in a set are active, the event->hw.prev_count
	 * needs to be synchronized.  At this point, the counter set can be in
	 * the inactive or disabled state.
	 */
	hw_perf_event_reset(event);

	/* increment refcount for this counter set */
	atomic_inc(&cpuhw->ctr_set[hwc->config_base]);
}

static void cpumf_pmu_stop(struct perf_event *event, int flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
	struct hw_perf_event *hwc = &event->hw;

	if (!(hwc->state & PERF_HES_STOPPED)) {
		/* Decrement reference count for this counter set and if this
		 * is the last used counter in the set, clear activation
		 * control and set the counter set state to inactive.
		 */
		if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base]))
			ctr_set_stop(&cpuhw->state, hwc->config_base);
		event->hw.state |= PERF_HES_STOPPED;
	}

	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		hw_perf_event_update(event);
		event->hw.state |= PERF_HES_UPTODATE;
	}
}

static int cpumf_pmu_add(struct perf_event *event, int flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);

	/* Check authorization for the counter set to which this
	 * counter belongs.
	 * For group events transaction, the authorization check is
	 * done in cpumf_pmu_commit_txn().
	 */
	if (!(cpuhw->flags & PERF_EVENT_TXN))
		if (validate_ctr_auth(&event->hw))
			return -EPERM;

	ctr_set_enable(&cpuhw->state, event->hw.config_base);
	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;

	if (flags & PERF_EF_START)
		cpumf_pmu_start(event, PERF_EF_RELOAD);

	perf_event_update_userpage(event);

	return 0;
}

static void cpumf_pmu_del(struct perf_event *event, int flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);

	cpumf_pmu_stop(event, PERF_EF_UPDATE);

	/* Check if any counter in the counter set is still used.  If not used,
	 * change the counter set to the disabled state.  This also clears the
	 * content of all counters in the set.
	 *
	 * When a new perf event has been added but not yet started, this can
	 * clear enable control and resets all counters in a set.  Therefore,
	 * cpumf_pmu_start() always has to reenable a counter set.
	 */
	if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base]))
		ctr_set_disable(&cpuhw->state, event->hw.config_base);

	perf_event_update_userpage(event);
}

/*
 * Start group events scheduling transaction.
 * Set flags to perform a single test at commit time.
 *
 * We only support PERF_PMU_TXN_ADD transactions. Save the
 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
 * transactions.
 */
static void cpumf_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(cpuhw->txn_flags);		/* txn already in flight */

	cpuhw->txn_flags = txn_flags;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

	perf_pmu_disable(pmu);
	cpuhw->flags |= PERF_EVENT_TXN;
	cpuhw->tx_state = cpuhw->state;
}

/*
 * Stop and cancel a group events scheduling tranctions.
 * Assumes cpumf_pmu_del() is called for each successful added
 * cpumf_pmu_add() during the transaction.
 */
static void cpumf_pmu_cancel_txn(struct pmu *pmu)
{
	unsigned int txn_flags;
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(!cpuhw->txn_flags);	/* no txn in flight */

	txn_flags = cpuhw->txn_flags;
	cpuhw->txn_flags = 0;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

	WARN_ON(cpuhw->tx_state != cpuhw->state);

	cpuhw->flags &= ~PERF_EVENT_TXN;
	perf_pmu_enable(pmu);
}

/*
 * Commit the group events scheduling transaction.  On success, the
 * transaction is closed.   On error, the transaction is kept open
 * until cpumf_pmu_cancel_txn() is called.
 */
static int cpumf_pmu_commit_txn(struct pmu *pmu)
{
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
	u64 state;

	WARN_ON_ONCE(!cpuhw->txn_flags);	/* no txn in flight */

	if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
		cpuhw->txn_flags = 0;
		return 0;
	}

	/* check if the updated state can be scheduled */
	state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
	state >>= CPUMF_LCCTL_ENABLE_SHIFT;
	if ((state & cpuhw->info.auth_ctl) != state)
		return -EPERM;

	cpuhw->flags &= ~PERF_EVENT_TXN;
	cpuhw->txn_flags = 0;
	perf_pmu_enable(pmu);
	return 0;
}

/* Performance monitoring unit for s390x */
static struct pmu cpumf_pmu = {
	.pmu_enable   = cpumf_pmu_enable,
	.pmu_disable  = cpumf_pmu_disable,
	.event_init   = cpumf_pmu_event_init,
	.add	      = cpumf_pmu_add,
	.del	      = cpumf_pmu_del,
	.start	      = cpumf_pmu_start,
	.stop	      = cpumf_pmu_stop,
	.read	      = cpumf_pmu_read,
	.start_txn    = cpumf_pmu_start_txn,
	.commit_txn   = cpumf_pmu_commit_txn,
	.cancel_txn   = cpumf_pmu_cancel_txn,
};

static int cpumf_pmu_notifier(struct notifier_block *self, unsigned long action,
			      void *hcpu)
{
	unsigned int cpu = (long) hcpu;
	int flags;

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_ONLINE:
		flags = PMC_INIT;
		smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
		break;
	case CPU_DOWN_PREPARE:
		flags = PMC_RELEASE;
		smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
		break;
	default:
		break;
	}

	return NOTIFY_OK;
}

static int __init cpumf_pmu_init(void)
{
	int rc;

	if (!cpum_cf_avail())
		return -ENODEV;

	/* clear bit 15 of cr0 to unauthorize problem-state to
	 * extract measurement counters */
	ctl_clear_bit(0, 48);

	/* register handler for measurement-alert interruptions */
	rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
				   cpumf_measurement_alert);
	if (rc) {
		pr_err("Registering for CPU-measurement alerts "
		       "failed with rc=%i\n", rc);
		goto out;
	}

	/* The CPU measurement counter facility does not have overflow
	 * interrupts to do sampling.  Sampling must be provided by
	 * external means, for example, by timers.
	 */
	cpumf_pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

	cpumf_pmu.attr_groups = cpumf_cf_event_group();
	rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
	if (rc) {
		pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);
		unregister_external_irq(EXT_IRQ_MEASURE_ALERT,
					cpumf_measurement_alert);
		goto out;
	}
	perf_cpu_notifier(cpumf_pmu_notifier);
out:
	return rc;
}
early_initcall(cpumf_pmu_init);
Commit	Line	Data
212188a5 HB	1	/*
	2	* Performance event support for s390x - CPU-measurement Counter Facility
	3	*
	4	* Copyright IBM Corp. 2012
	5	* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License (version 2 only)
	9	* as published by the Free Software Foundation.
	10	*/
	11	#define KMSG_COMPONENT "cpum_cf"
	12	#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
	13
	14	#include <linux/kernel.h>
	15	#include <linux/kernel_stat.h>
	16	#include <linux/perf_event.h>
	17	#include <linux/percpu.h>
	18	#include <linux/notifier.h>
	19	#include <linux/init.h>
	20	#include <linux/export.h>
1e3cab2f	21	#include <asm/ctl_reg.h>
212188a5 HB	22	#include <asm/irq.h>
	23	#include <asm/cpu_mf.h>
	24
	25	/* CPU-measurement counter facility supports these CPU counter sets:
	26	* For CPU counter sets:
	27	* Basic counter set: 0-31
	28	* Problem-state counter set: 32-63
	29	* Crypto-activity counter set: 64-127
	30	* Extented counter set: 128-159
	31	*/
	32	enum cpumf_ctr_set {
	33	/* CPU counter sets */
	34	CPUMF_CTR_SET_BASIC = 0,
	35	CPUMF_CTR_SET_USER = 1,
	36	CPUMF_CTR_SET_CRYPTO = 2,
	37	CPUMF_CTR_SET_EXT = 3,
	38
	39	/* Maximum number of counter sets */
	40	CPUMF_CTR_SET_MAX,
	41	};
	42
	43	#define CPUMF_LCCTL_ENABLE_SHIFT 16
	44	#define CPUMF_LCCTL_ACTCTL_SHIFT 0
	45	static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = {
	46	[CPUMF_CTR_SET_BASIC] = 0x02,
	47	[CPUMF_CTR_SET_USER] = 0x04,
	48	[CPUMF_CTR_SET_CRYPTO] = 0x08,
	49	[CPUMF_CTR_SET_EXT] = 0x01,
	50	};
	51
	52	static void ctr_set_enable(u64 *state, int ctr_set)
	53	{
	54	*state \|= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT;
	55	}
	56	static void ctr_set_disable(u64 *state, int ctr_set)
	57	{
	58	*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT);
	59	}
	60	static void ctr_set_start(u64 *state, int ctr_set)
	61	{
	62	*state \|= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT;
	63	}
	64	static void ctr_set_stop(u64 *state, int ctr_set)
	65	{
	66	*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT);
	67	}
	68
	69	/* Local CPUMF event structure */
	70	struct cpu_hw_events {
	71	struct cpumf_ctr_info info;
	72	atomic_t ctr_set[CPUMF_CTR_SET_MAX];
	73	u64 state, tx_state;
	74	unsigned int flags;
fbbe0701	75	unsigned int txn_flags;
212188a5 HB	76	};
	77	static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
	78	.ctr_set = {
	79	[CPUMF_CTR_SET_BASIC] = ATOMIC_INIT(0),
	80	[CPUMF_CTR_SET_USER] = ATOMIC_INIT(0),
	81	[CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0),
	82	[CPUMF_CTR_SET_EXT] = ATOMIC_INIT(0),
	83	},
	84	.state = 0,
	85	.flags = 0,
fbbe0701	86	.txn_flags = 0,
212188a5 HB	87	};
	88
	89	static int get_counter_set(u64 event)
	90	{
	91	int set = -1;
	92
	93	if (event < 32)
	94	set = CPUMF_CTR_SET_BASIC;
	95	else if (event < 64)
	96	set = CPUMF_CTR_SET_USER;
	97	else if (event < 128)
	98	set = CPUMF_CTR_SET_CRYPTO;
f47586b2	99	else if (event < 256)
212188a5 HB	100	set = CPUMF_CTR_SET_EXT;
	101
	102	return set;
	103	}
	104
	105	static int validate_event(const struct hw_perf_event *hwc)
	106	{
	107	switch (hwc->config_base) {
	108	case CPUMF_CTR_SET_BASIC:
	109	case CPUMF_CTR_SET_USER:
	110	case CPUMF_CTR_SET_CRYPTO:
	111	case CPUMF_CTR_SET_EXT:
	112	/* check for reserved counters */
	113	if ((hwc->config >= 6 && hwc->config <= 31) \|\|
	114	(hwc->config >= 38 && hwc->config <= 63) \|\|
	115	(hwc->config >= 80 && hwc->config <= 127))
	116	return -EOPNOTSUPP;
	117	break;
	118	default:
	119	return -EINVAL;
	120	}
	121
	122	return 0;
	123	}
	124
	125	static int validate_ctr_version(const struct hw_perf_event *hwc)
	126	{
	127	struct cpu_hw_events *cpuhw;
	128	int err = 0;
	129
	130	cpuhw = &get_cpu_var(cpu_hw_events);
	131
	132	/* check required version for counter sets */
	133	switch (hwc->config_base) {
	134	case CPUMF_CTR_SET_BASIC:
	135	case CPUMF_CTR_SET_USER:
	136	if (cpuhw->info.cfvn < 1)
	137	err = -EOPNOTSUPP;
	138	break;
	139	case CPUMF_CTR_SET_CRYPTO:
	140	case CPUMF_CTR_SET_EXT:
	141	if (cpuhw->info.csvn < 1)
	142	err = -EOPNOTSUPP;
f47586b2 HB	143	if ((cpuhw->info.csvn == 1 && hwc->config > 159) \|\|
	144	(cpuhw->info.csvn == 2 && hwc->config > 175) \|\|
	145	(cpuhw->info.csvn > 2 && hwc->config > 255))
	146	err = -EOPNOTSUPP;
212188a5 HB	147	break;
	148	}
	149
	150	put_cpu_var(cpu_hw_events);
	151	return err;
	152	}
	153
	154	static int validate_ctr_auth(const struct hw_perf_event *hwc)
	155	{
	156	struct cpu_hw_events *cpuhw;
	157	u64 ctrs_state;
	158	int err = 0;
	159
	160	cpuhw = &get_cpu_var(cpu_hw_events);
	161
	162	/* check authorization for cpu counter sets */
	163	ctrs_state = cpumf_state_ctl[hwc->config_base];
	164	if (!(ctrs_state & cpuhw->info.auth_ctl))
	165	err = -EPERM;
	166
	167	put_cpu_var(cpu_hw_events);
	168	return err;
	169	}
	170
	171	/*
	172	* Change the CPUMF state to active.
	173	* Enable and activate the CPU-counter sets according
	174	* to the per-cpu control state.
	175	*/
	176	static void cpumf_pmu_enable(struct pmu *pmu)
	177	{
eb7e7d76	178	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	179	int err;
	180
	181	if (cpuhw->flags & PMU_F_ENABLED)
	182	return;
	183
	184	err = lcctl(cpuhw->state);
	185	if (err) {
	186	pr_err("Enabling the performance measuring unit "
af0ee94e	187	"failed with rc=%x\n", err);
212188a5 HB	188	return;
	189	}
	190
	191	cpuhw->flags \|= PMU_F_ENABLED;
	192	}
	193
	194	/*
	195	* Change the CPUMF state to inactive.
	196	* Disable and enable (inactive) the CPU-counter sets according
	197	* to the per-cpu control state.
	198	*/
	199	static void cpumf_pmu_disable(struct pmu *pmu)
	200	{
eb7e7d76	201	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	202	int err;
	203	u64 inactive;
	204
	205	if (!(cpuhw->flags & PMU_F_ENABLED))
	206	return;
	207
	208	inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
	209	err = lcctl(inactive);
	210	if (err) {
	211	pr_err("Disabling the performance measuring unit "
af0ee94e	212	"failed with rc=%x\n", err);
212188a5 HB	213	return;
	214	}
	215
	216	cpuhw->flags &= ~PMU_F_ENABLED;
	217	}
	218
	219
	220	/* Number of perf events counting hardware events */
	221	static atomic_t num_events = ATOMIC_INIT(0);
	222	/* Used to avoid races in calling reserve/release_cpumf_hardware */
	223	static DEFINE_MUTEX(pmc_reserve_mutex);
	224
	225	/* CPU-measurement alerts for the counter facility */
	226	static void cpumf_measurement_alert(struct ext_code ext_code,
	227	unsigned int alert, unsigned long unused)
	228	{
	229	struct cpu_hw_events *cpuhw;
	230
	231	if (!(alert & CPU_MF_INT_CF_MASK))
	232	return;
	233
420f42ec	234	inc_irq_stat(IRQEXT_CMC);
eb7e7d76	235	cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	236
	237	/* Measurement alerts are shared and might happen when the PMU
	238	* is not reserved. Ignore these alerts in this case. */
	239	if (!(cpuhw->flags & PMU_F_RESERVED))
	240	return;
	241
	242	/* counter authorization change alert */
	243	if (alert & CPU_MF_INT_CF_CACA)
	244	qctri(&cpuhw->info);
	245
	246	/* loss of counter data alert */
	247	if (alert & CPU_MF_INT_CF_LCDA)
	248	pr_err("CPU[%i] Counter data was lost\n", smp_processor_id());
	249	}
	250
	251	#define PMC_INIT 0
	252	#define PMC_RELEASE 1
	253	static void setup_pmc_cpu(void *flags)
	254	{
eb7e7d76	255	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	256
	257	switch (((int ) flags)) {
	258	case PMC_INIT:
	259	memset(&cpuhw->info, 0, sizeof(cpuhw->info));
	260	qctri(&cpuhw->info);
	261	cpuhw->flags \|= PMU_F_RESERVED;
	262	break;
	263
	264	case PMC_RELEASE:
	265	cpuhw->flags &= ~PMU_F_RESERVED;
	266	break;
	267	}
	268
	269	/* Disable CPU counter sets */
	270	lcctl(0);
	271	}
	272
	273	/* Initialize the CPU-measurement facility */
	274	static int reserve_pmc_hardware(void)
	275	{
	276	int flags = PMC_INIT;
	277
	278	on_each_cpu(setup_pmc_cpu, &flags, 1);
82003c3e	279	irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT);
212188a5 HB	280
	281	return 0;
	282	}
	283
	284	/* Release the CPU-measurement facility */
	285	static void release_pmc_hardware(void)
	286	{
	287	int flags = PMC_RELEASE;
	288
	289	on_each_cpu(setup_pmc_cpu, &flags, 1);
82003c3e	290	irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT);
212188a5 HB	291	}
	292
	293	/* Release the PMU if event is the last perf event */
	294	static void hw_perf_event_destroy(struct perf_event *event)
	295	{
	296	if (!atomic_add_unless(&num_events, -1, 1)) {
	297	mutex_lock(&pmc_reserve_mutex);
	298	if (atomic_dec_return(&num_events) == 0)
	299	release_pmc_hardware();
	300	mutex_unlock(&pmc_reserve_mutex);
	301	}
	302	}
	303
	304	/* CPUMF <-> perf event mappings for kernel+userspace (basic set) */
	305	static const int cpumf_generic_events_basic[] = {
	306	[PERF_COUNT_HW_CPU_CYCLES] = 0,
	307	[PERF_COUNT_HW_INSTRUCTIONS] = 1,
	308	[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
	309	[PERF_COUNT_HW_CACHE_MISSES] = -1,
	310	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
	311	[PERF_COUNT_HW_BRANCH_MISSES] = -1,
	312	[PERF_COUNT_HW_BUS_CYCLES] = -1,
	313	};
	314	/* CPUMF <-> perf event mappings for userspace (problem-state set) */
	315	static const int cpumf_generic_events_user[] = {
	316	[PERF_COUNT_HW_CPU_CYCLES] = 32,
	317	[PERF_COUNT_HW_INSTRUCTIONS] = 33,
	318	[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
	319	[PERF_COUNT_HW_CACHE_MISSES] = -1,
	320	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
	321	[PERF_COUNT_HW_BRANCH_MISSES] = -1,
	322	[PERF_COUNT_HW_BUS_CYCLES] = -1,
	323	};
	324
	325	static int __hw_perf_event_init(struct perf_event *event)
	326	{
	327	struct perf_event_attr *attr = &event->attr;
	328	struct hw_perf_event *hwc = &event->hw;
	329	int err;
	330	u64 ev;
	331
	332	switch (attr->type) {
	333	case PERF_TYPE_RAW:
	334	/* Raw events are used to access counters directly,
	335	* hence do not permit excludes */
	336	if (attr->exclude_kernel \|\| attr->exclude_user \|\|
	337	attr->exclude_hv)
	338	return -EOPNOTSUPP;
	339	ev = attr->config;
	340	break;
	341
	342	case PERF_TYPE_HARDWARE:
	343	ev = attr->config;
	344	/* Count user space (problem-state) only */
	345	if (!attr->exclude_user && attr->exclude_kernel) {
	346	if (ev >= ARRAY_SIZE(cpumf_generic_events_user))
	347	return -EOPNOTSUPP;
	348	ev = cpumf_generic_events_user[ev];
	349
	350	/* No support for kernel space counters only */
	351	} else if (!attr->exclude_kernel && attr->exclude_user) {
	352	return -EOPNOTSUPP;
	353
	354	/* Count user and kernel space */
355	} else {
356	if (ev >= ARRAY_SIZE(cpumf_generic_events_basic))
357	return -EOPNOTSUPP;
358	ev = cpumf_generic_events_basic[ev];
359	}
360	break;
361
362	default:
363	return -ENOENT;
364	}
365
366	if (ev == -1)
367	return -ENOENT;
368
369	if (ev >= PERF_CPUM_CF_MAX_CTR)
370	return -EINVAL;
371
212188a5 HB	372	/* Use the hardware perf event structure to store the counter number
	373	* in 'config' member and the counter set to which the counter belongs
	374	* in the 'config_base'. The counter set (config_base) is then used
	375	* to enable/disable the counters.
	376	*/
	377	hwc->config = ev;
	378	hwc->config_base = get_counter_set(ev);
	379
	380	/* Validate the counter that is assigned to this event.
	381	* Because the counter facility can use numerous counters at the
	382	* same time without constraints, it is not necessary to explicity
	383	* validate event groups (event->group_leader != event).
	384	*/
	385	err = validate_event(hwc);
	386	if (err)
	387	return err;
	388
	389	/* Initialize for using the CPU-measurement counter facility */
	390	if (!atomic_inc_not_zero(&num_events)) {
	391	mutex_lock(&pmc_reserve_mutex);
	392	if (atomic_read(&num_events) == 0 && reserve_pmc_hardware())
	393	err = -EBUSY;
	394	else
	395	atomic_inc(&num_events);
	396	mutex_unlock(&pmc_reserve_mutex);
	397	}
	398	event->destroy = hw_perf_event_destroy;
	399
	400	/* Finally, validate version and authorization of the counter set */
	401	err = validate_ctr_auth(hwc);
	402	if (!err)
	403	err = validate_ctr_version(hwc);
	404
	405	return err;
	406	}
	407
	408	static int cpumf_pmu_event_init(struct perf_event *event)
	409	{
	410	int err;
	411
	412	switch (event->attr.type) {
	413	case PERF_TYPE_HARDWARE:
	414	case PERF_TYPE_HW_CACHE:
	415	case PERF_TYPE_RAW:
	416	err = __hw_perf_event_init(event);
	417	break;
	418	default:
	419	return -ENOENT;
	420	}
	421
	422	if (unlikely(err) && event->destroy)
	423	event->destroy(event);
	424
	425	return err;
	426	}
	427
	428	static int hw_perf_event_reset(struct perf_event *event)
	429	{
	430	u64 prev, new;
	431	int err;
	432
	433	do {
	434	prev = local64_read(&event->hw.prev_count);
	435	err = ecctr(event->hw.config, &new);
436	if (err) {
437	if (err != 3)
438	break;
439	/* The counter is not (yet) available. This
440	* might happen if the counter set to which
441	* this counter belongs is in the disabled
442	* state.
443	*/
444	new = 0;
445	}
446	} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
447
448	return err;
449	}
450
451	static int hw_perf_event_update(struct perf_event *event)
452	{
453	u64 prev, new, delta;
454	int err;
455
456	do {
457	prev = local64_read(&event->hw.prev_count);
458	err = ecctr(event->hw.config, &new);
459	if (err)
460	goto out;
461	} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
462
463	delta = (prev <= new) ? new - prev
464	: (-1ULL - prev) + new + 1; /* overflow */
465	local64_add(delta, &event->count);
466	out:
467	return err;
468	}
469
470	static void cpumf_pmu_read(struct perf_event *event)
471	{
472	if (event->hw.state & PERF_HES_STOPPED)
473	return;
474
475	hw_perf_event_update(event);
476	}
477
478	static void cpumf_pmu_start(struct perf_event *event, int flags)
479	{
eb7e7d76	480	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	481	struct hw_perf_event *hwc = &event->hw;
	482
	483	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
	484	return;
	485
	486	if (WARN_ON_ONCE(hwc->config == -1))
	487	return;
	488
	489	if (flags & PERF_EF_RELOAD)
	490	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
	491
	492	hwc->state = 0;
	493
	494	/* (Re-)enable and activate the counter set */
	495	ctr_set_enable(&cpuhw->state, hwc->config_base);
	496	ctr_set_start(&cpuhw->state, hwc->config_base);
	497
	498	/* The counter set to which this counter belongs can be already active.
	499	* Because all counters in a set are active, the event->hw.prev_count
	500	* needs to be synchronized. At this point, the counter set can be in
	501	* the inactive or disabled state.
	502	*/
	503	hw_perf_event_reset(event);
	504
	505	/* increment refcount for this counter set */
	506	atomic_inc(&cpuhw->ctr_set[hwc->config_base]);
	507	}
	508
	509	static void cpumf_pmu_stop(struct perf_event *event, int flags)
	510	{
eb7e7d76	511	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	512	struct hw_perf_event *hwc = &event->hw;
	513
	514	if (!(hwc->state & PERF_HES_STOPPED)) {
	515	/* Decrement reference count for this counter set and if this
	516	* is the last used counter in the set, clear activation
	517	* control and set the counter set state to inactive.
	518	*/
	519	if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base]))
	520	ctr_set_stop(&cpuhw->state, hwc->config_base);
	521	event->hw.state \|= PERF_HES_STOPPED;
	522	}
	523
	524	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
	525	hw_perf_event_update(event);
	526	event->hw.state \|= PERF_HES_UPTODATE;
	527	}
	528	}
	529
	530	static int cpumf_pmu_add(struct perf_event *event, int flags)
	531	{
eb7e7d76	532	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	533
	534	/* Check authorization for the counter set to which this
	535	* counter belongs.
	536	* For group events transaction, the authorization check is
	537	* done in cpumf_pmu_commit_txn().
	538	*/
	539	if (!(cpuhw->flags & PERF_EVENT_TXN))
	540	if (validate_ctr_auth(&event->hw))
	541	return -EPERM;
	542
	543	ctr_set_enable(&cpuhw->state, event->hw.config_base);
	544	event->hw.state = PERF_HES_UPTODATE \| PERF_HES_STOPPED;
	545
	546	if (flags & PERF_EF_START)
	547	cpumf_pmu_start(event, PERF_EF_RELOAD);
	548
	549	perf_event_update_userpage(event);
	550
	551	return 0;
	552	}
	553
	554	static void cpumf_pmu_del(struct perf_event *event, int flags)
	555	{
eb7e7d76	556	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	557
	558	cpumf_pmu_stop(event, PERF_EF_UPDATE);
	559
	560	/* Check if any counter in the counter set is still used. If not used,
	561	* change the counter set to the disabled state. This also clears the
	562	* content of all counters in the set.
	563	*
	564	* When a new perf event has been added but not yet started, this can
	565	* clear enable control and resets all counters in a set. Therefore,
	566	* cpumf_pmu_start() always has to reenable a counter set.
	567	*/
	568	if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base]))
	569	ctr_set_disable(&cpuhw->state, event->hw.config_base);
	570
	571	perf_event_update_userpage(event);
	572	}
	573
	574	/*
	575	* Start group events scheduling transaction.
	576	* Set flags to perform a single test at commit time.
fbbe0701 SB	577	*
	578	* We only support PERF_PMU_TXN_ADD transactions. Save the
	579	* transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
	580	* transactions.
212188a5	581	*/
fbbe0701	582	static void cpumf_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
212188a5	583	{
eb7e7d76	584	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5	585
fbbe0701 SB	586	WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
	587
	588	cpuhw->txn_flags = txn_flags;
	589	if (txn_flags & ~PERF_PMU_TXN_ADD)
	590	return;
	591
212188a5 HB	592	perf_pmu_disable(pmu);
	593	cpuhw->flags \|= PERF_EVENT_TXN;
	594	cpuhw->tx_state = cpuhw->state;
	595	}
	596
	597	/*
	598	* Stop and cancel a group events scheduling tranctions.
	599	* Assumes cpumf_pmu_del() is called for each successful added
	600	* cpumf_pmu_add() during the transaction.
	601	*/
	602	static void cpumf_pmu_cancel_txn(struct pmu *pmu)
	603	{
fbbe0701	604	unsigned int txn_flags;
eb7e7d76	605	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5	606
fbbe0701 SB	607	WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
	608
	609	txn_flags = cpuhw->txn_flags;
	610	cpuhw->txn_flags = 0;
	611	if (txn_flags & ~PERF_PMU_TXN_ADD)
	612	return;
	613
212188a5 HB	614	WARN_ON(cpuhw->tx_state != cpuhw->state);
	615
	616	cpuhw->flags &= ~PERF_EVENT_TXN;
	617	perf_pmu_enable(pmu);
	618	}
	619
	620	/*
	621	* Commit the group events scheduling transaction. On success, the
	622	* transaction is closed. On error, the transaction is kept open
	623	* until cpumf_pmu_cancel_txn() is called.
	624	*/
	625	static int cpumf_pmu_commit_txn(struct pmu *pmu)
	626	{
eb7e7d76	627	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
212188a5 HB	628	u64 state;
212188a5 HB	629
fbbe0701 SB	630	WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
	631
	632	if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
	633	cpuhw->txn_flags = 0;
	634	return 0;
	635	}
	636
212188a5 HB	637	/* check if the updated state can be scheduled */
	638	state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
	639	state >>= CPUMF_LCCTL_ENABLE_SHIFT;
	640	if ((state & cpuhw->info.auth_ctl) != state)
	641	return -EPERM;
	642
	643	cpuhw->flags &= ~PERF_EVENT_TXN;
fbbe0701	644	cpuhw->txn_flags = 0;
212188a5 HB	645	perf_pmu_enable(pmu);
	646	return 0;
	647	}
	648
	649	/* Performance monitoring unit for s390x */
	650	static struct pmu cpumf_pmu = {
	651	.pmu_enable = cpumf_pmu_enable,
	652	.pmu_disable = cpumf_pmu_disable,
	653	.event_init = cpumf_pmu_event_init,
	654	.add = cpumf_pmu_add,
	655	.del = cpumf_pmu_del,
	656	.start = cpumf_pmu_start,
	657	.stop = cpumf_pmu_stop,
	658	.read = cpumf_pmu_read,
	659	.start_txn = cpumf_pmu_start_txn,
	660	.commit_txn = cpumf_pmu_commit_txn,
	661	.cancel_txn = cpumf_pmu_cancel_txn,
	662	};
	663
e2741f17 PG	664	static int cpumf_pmu_notifier(struct notifier_block *self, unsigned long action,
e2741f17 PG	665	void *hcpu)
212188a5 HB	666	{
	667	unsigned int cpu = (long) hcpu;
	668	int flags;
	669
	670	switch (action & ~CPU_TASKS_FROZEN) {
	671	case CPU_ONLINE:
	672	flags = PMC_INIT;
	673	smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
	674	break;
	675	case CPU_DOWN_PREPARE:
	676	flags = PMC_RELEASE;
	677	smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
	678	break;
	679	default:
	680	break;
	681	}
	682
	683	return NOTIFY_OK;
	684	}
	685
	686	static int __init cpumf_pmu_init(void)
	687	{
	688	int rc;
	689
	690	if (!cpum_cf_avail())
	691	return -ENODEV;
	692
	693	/* clear bit 15 of cr0 to unauthorize problem-state to
	694	* extract measurement counters */
	695	ctl_clear_bit(0, 48);
	696
	697	/* register handler for measurement-alert interruptions */
1dad093b TH	698	rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
1dad093b TH	699	cpumf_measurement_alert);
212188a5 HB	700	if (rc) {
	701	pr_err("Registering for CPU-measurement alerts "
	702	"failed with rc=%i\n", rc);
	703	goto out;
	704	}
	705
97b1198f VW	706	/* The CPU measurement counter facility does not have overflow
	707	* interrupts to do sampling. Sampling must be provided by
	708	* external means, for example, by timers.
	709	*/
	710	cpumf_pmu.capabilities \|= PERF_PMU_CAP_NO_INTERRUPT;
	711
c7168325	712	cpumf_pmu.attr_groups = cpumf_cf_event_group();
212188a5 HB	713	rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
	714	if (rc) {
	715	pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);
1dad093b TH	716	unregister_external_irq(EXT_IRQ_MEASURE_ALERT,
1dad093b TH	717	cpumf_measurement_alert);
212188a5 HB	718	goto out;
	719	}
	720	perf_cpu_notifier(cpumf_pmu_notifier);
	721	out:
	722	return rc;
	723	}
	724	early_initcall(cpumf_pmu_init);