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212188a5 HB |
1 | /* |
2 | * Performance event support for s390x - CPU-measurement Counter Facility | |
3 | * | |
db17160d | 4 | * Copyright IBM Corp. 2012, 2017 |
212188a5 HB |
5 | * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License (version 2 only) | |
9 | * as published by the Free Software Foundation. | |
10 | */ | |
11 | #define KMSG_COMPONENT "cpum_cf" | |
12 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/perf_event.h> | |
17 | #include <linux/percpu.h> | |
18 | #include <linux/notifier.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/export.h> | |
1e3cab2f | 21 | #include <asm/ctl_reg.h> |
212188a5 HB |
22 | #include <asm/irq.h> |
23 | #include <asm/cpu_mf.h> | |
24 | ||
25 | /* CPU-measurement counter facility supports these CPU counter sets: | |
26 | * For CPU counter sets: | |
27 | * Basic counter set: 0-31 | |
28 | * Problem-state counter set: 32-63 | |
29 | * Crypto-activity counter set: 64-127 | |
30 | * Extented counter set: 128-159 | |
31 | */ | |
32 | enum cpumf_ctr_set { | |
33 | /* CPU counter sets */ | |
34 | CPUMF_CTR_SET_BASIC = 0, | |
35 | CPUMF_CTR_SET_USER = 1, | |
36 | CPUMF_CTR_SET_CRYPTO = 2, | |
37 | CPUMF_CTR_SET_EXT = 3, | |
38 | ||
39 | /* Maximum number of counter sets */ | |
40 | CPUMF_CTR_SET_MAX, | |
41 | }; | |
42 | ||
43 | #define CPUMF_LCCTL_ENABLE_SHIFT 16 | |
44 | #define CPUMF_LCCTL_ACTCTL_SHIFT 0 | |
45 | static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = { | |
46 | [CPUMF_CTR_SET_BASIC] = 0x02, | |
47 | [CPUMF_CTR_SET_USER] = 0x04, | |
48 | [CPUMF_CTR_SET_CRYPTO] = 0x08, | |
49 | [CPUMF_CTR_SET_EXT] = 0x01, | |
50 | }; | |
51 | ||
52 | static void ctr_set_enable(u64 *state, int ctr_set) | |
53 | { | |
54 | *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT; | |
55 | } | |
56 | static void ctr_set_disable(u64 *state, int ctr_set) | |
57 | { | |
58 | *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT); | |
59 | } | |
60 | static void ctr_set_start(u64 *state, int ctr_set) | |
61 | { | |
62 | *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT; | |
63 | } | |
64 | static void ctr_set_stop(u64 *state, int ctr_set) | |
65 | { | |
66 | *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT); | |
67 | } | |
68 | ||
69 | /* Local CPUMF event structure */ | |
70 | struct cpu_hw_events { | |
71 | struct cpumf_ctr_info info; | |
72 | atomic_t ctr_set[CPUMF_CTR_SET_MAX]; | |
73 | u64 state, tx_state; | |
74 | unsigned int flags; | |
fbbe0701 | 75 | unsigned int txn_flags; |
212188a5 HB |
76 | }; |
77 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { | |
78 | .ctr_set = { | |
79 | [CPUMF_CTR_SET_BASIC] = ATOMIC_INIT(0), | |
80 | [CPUMF_CTR_SET_USER] = ATOMIC_INIT(0), | |
81 | [CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0), | |
82 | [CPUMF_CTR_SET_EXT] = ATOMIC_INIT(0), | |
83 | }, | |
84 | .state = 0, | |
85 | .flags = 0, | |
fbbe0701 | 86 | .txn_flags = 0, |
212188a5 HB |
87 | }; |
88 | ||
89 | static int get_counter_set(u64 event) | |
90 | { | |
91 | int set = -1; | |
92 | ||
93 | if (event < 32) | |
94 | set = CPUMF_CTR_SET_BASIC; | |
95 | else if (event < 64) | |
96 | set = CPUMF_CTR_SET_USER; | |
97 | else if (event < 128) | |
98 | set = CPUMF_CTR_SET_CRYPTO; | |
f47586b2 | 99 | else if (event < 256) |
212188a5 HB |
100 | set = CPUMF_CTR_SET_EXT; |
101 | ||
102 | return set; | |
103 | } | |
104 | ||
212188a5 HB |
105 | static int validate_ctr_version(const struct hw_perf_event *hwc) |
106 | { | |
107 | struct cpu_hw_events *cpuhw; | |
108 | int err = 0; | |
109 | ||
110 | cpuhw = &get_cpu_var(cpu_hw_events); | |
111 | ||
112 | /* check required version for counter sets */ | |
113 | switch (hwc->config_base) { | |
114 | case CPUMF_CTR_SET_BASIC: | |
115 | case CPUMF_CTR_SET_USER: | |
116 | if (cpuhw->info.cfvn < 1) | |
117 | err = -EOPNOTSUPP; | |
118 | break; | |
119 | case CPUMF_CTR_SET_CRYPTO: | |
120 | case CPUMF_CTR_SET_EXT: | |
121 | if (cpuhw->info.csvn < 1) | |
122 | err = -EOPNOTSUPP; | |
f47586b2 HB |
123 | if ((cpuhw->info.csvn == 1 && hwc->config > 159) || |
124 | (cpuhw->info.csvn == 2 && hwc->config > 175) || | |
125 | (cpuhw->info.csvn > 2 && hwc->config > 255)) | |
126 | err = -EOPNOTSUPP; | |
212188a5 HB |
127 | break; |
128 | } | |
129 | ||
130 | put_cpu_var(cpu_hw_events); | |
131 | return err; | |
132 | } | |
133 | ||
134 | static int validate_ctr_auth(const struct hw_perf_event *hwc) | |
135 | { | |
136 | struct cpu_hw_events *cpuhw; | |
137 | u64 ctrs_state; | |
138 | int err = 0; | |
139 | ||
140 | cpuhw = &get_cpu_var(cpu_hw_events); | |
141 | ||
58f8e9da HB |
142 | /* Check authorization for cpu counter sets. |
143 | * If the particular CPU counter set is not authorized, | |
144 | * return with -ENOENT in order to fall back to other | |
145 | * PMUs that might suffice the event request. | |
146 | */ | |
212188a5 HB |
147 | ctrs_state = cpumf_state_ctl[hwc->config_base]; |
148 | if (!(ctrs_state & cpuhw->info.auth_ctl)) | |
58f8e9da | 149 | err = -ENOENT; |
212188a5 HB |
150 | |
151 | put_cpu_var(cpu_hw_events); | |
152 | return err; | |
153 | } | |
154 | ||
155 | /* | |
156 | * Change the CPUMF state to active. | |
157 | * Enable and activate the CPU-counter sets according | |
158 | * to the per-cpu control state. | |
159 | */ | |
160 | static void cpumf_pmu_enable(struct pmu *pmu) | |
161 | { | |
eb7e7d76 | 162 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
163 | int err; |
164 | ||
165 | if (cpuhw->flags & PMU_F_ENABLED) | |
166 | return; | |
167 | ||
168 | err = lcctl(cpuhw->state); | |
169 | if (err) { | |
170 | pr_err("Enabling the performance measuring unit " | |
af0ee94e | 171 | "failed with rc=%x\n", err); |
212188a5 HB |
172 | return; |
173 | } | |
174 | ||
175 | cpuhw->flags |= PMU_F_ENABLED; | |
176 | } | |
177 | ||
178 | /* | |
179 | * Change the CPUMF state to inactive. | |
180 | * Disable and enable (inactive) the CPU-counter sets according | |
181 | * to the per-cpu control state. | |
182 | */ | |
183 | static void cpumf_pmu_disable(struct pmu *pmu) | |
184 | { | |
eb7e7d76 | 185 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
186 | int err; |
187 | u64 inactive; | |
188 | ||
189 | if (!(cpuhw->flags & PMU_F_ENABLED)) | |
190 | return; | |
191 | ||
192 | inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); | |
193 | err = lcctl(inactive); | |
194 | if (err) { | |
195 | pr_err("Disabling the performance measuring unit " | |
af0ee94e | 196 | "failed with rc=%x\n", err); |
212188a5 HB |
197 | return; |
198 | } | |
199 | ||
200 | cpuhw->flags &= ~PMU_F_ENABLED; | |
201 | } | |
202 | ||
203 | ||
204 | /* Number of perf events counting hardware events */ | |
205 | static atomic_t num_events = ATOMIC_INIT(0); | |
206 | /* Used to avoid races in calling reserve/release_cpumf_hardware */ | |
207 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
208 | ||
209 | /* CPU-measurement alerts for the counter facility */ | |
210 | static void cpumf_measurement_alert(struct ext_code ext_code, | |
211 | unsigned int alert, unsigned long unused) | |
212 | { | |
213 | struct cpu_hw_events *cpuhw; | |
214 | ||
215 | if (!(alert & CPU_MF_INT_CF_MASK)) | |
216 | return; | |
217 | ||
420f42ec | 218 | inc_irq_stat(IRQEXT_CMC); |
eb7e7d76 | 219 | cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
220 | |
221 | /* Measurement alerts are shared and might happen when the PMU | |
222 | * is not reserved. Ignore these alerts in this case. */ | |
223 | if (!(cpuhw->flags & PMU_F_RESERVED)) | |
224 | return; | |
225 | ||
226 | /* counter authorization change alert */ | |
227 | if (alert & CPU_MF_INT_CF_CACA) | |
228 | qctri(&cpuhw->info); | |
229 | ||
230 | /* loss of counter data alert */ | |
231 | if (alert & CPU_MF_INT_CF_LCDA) | |
232 | pr_err("CPU[%i] Counter data was lost\n", smp_processor_id()); | |
233 | } | |
234 | ||
235 | #define PMC_INIT 0 | |
236 | #define PMC_RELEASE 1 | |
237 | static void setup_pmc_cpu(void *flags) | |
238 | { | |
eb7e7d76 | 239 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
240 | |
241 | switch (*((int *) flags)) { | |
242 | case PMC_INIT: | |
243 | memset(&cpuhw->info, 0, sizeof(cpuhw->info)); | |
244 | qctri(&cpuhw->info); | |
245 | cpuhw->flags |= PMU_F_RESERVED; | |
246 | break; | |
247 | ||
248 | case PMC_RELEASE: | |
249 | cpuhw->flags &= ~PMU_F_RESERVED; | |
250 | break; | |
251 | } | |
252 | ||
253 | /* Disable CPU counter sets */ | |
254 | lcctl(0); | |
255 | } | |
256 | ||
257 | /* Initialize the CPU-measurement facility */ | |
258 | static int reserve_pmc_hardware(void) | |
259 | { | |
260 | int flags = PMC_INIT; | |
261 | ||
262 | on_each_cpu(setup_pmc_cpu, &flags, 1); | |
82003c3e | 263 | irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT); |
212188a5 HB |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
268 | /* Release the CPU-measurement facility */ | |
269 | static void release_pmc_hardware(void) | |
270 | { | |
271 | int flags = PMC_RELEASE; | |
272 | ||
273 | on_each_cpu(setup_pmc_cpu, &flags, 1); | |
82003c3e | 274 | irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT); |
212188a5 HB |
275 | } |
276 | ||
277 | /* Release the PMU if event is the last perf event */ | |
278 | static void hw_perf_event_destroy(struct perf_event *event) | |
279 | { | |
280 | if (!atomic_add_unless(&num_events, -1, 1)) { | |
281 | mutex_lock(&pmc_reserve_mutex); | |
282 | if (atomic_dec_return(&num_events) == 0) | |
283 | release_pmc_hardware(); | |
284 | mutex_unlock(&pmc_reserve_mutex); | |
285 | } | |
286 | } | |
287 | ||
288 | /* CPUMF <-> perf event mappings for kernel+userspace (basic set) */ | |
289 | static const int cpumf_generic_events_basic[] = { | |
290 | [PERF_COUNT_HW_CPU_CYCLES] = 0, | |
291 | [PERF_COUNT_HW_INSTRUCTIONS] = 1, | |
292 | [PERF_COUNT_HW_CACHE_REFERENCES] = -1, | |
293 | [PERF_COUNT_HW_CACHE_MISSES] = -1, | |
294 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, | |
295 | [PERF_COUNT_HW_BRANCH_MISSES] = -1, | |
296 | [PERF_COUNT_HW_BUS_CYCLES] = -1, | |
297 | }; | |
298 | /* CPUMF <-> perf event mappings for userspace (problem-state set) */ | |
299 | static const int cpumf_generic_events_user[] = { | |
300 | [PERF_COUNT_HW_CPU_CYCLES] = 32, | |
301 | [PERF_COUNT_HW_INSTRUCTIONS] = 33, | |
302 | [PERF_COUNT_HW_CACHE_REFERENCES] = -1, | |
303 | [PERF_COUNT_HW_CACHE_MISSES] = -1, | |
304 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, | |
305 | [PERF_COUNT_HW_BRANCH_MISSES] = -1, | |
306 | [PERF_COUNT_HW_BUS_CYCLES] = -1, | |
307 | }; | |
308 | ||
309 | static int __hw_perf_event_init(struct perf_event *event) | |
310 | { | |
311 | struct perf_event_attr *attr = &event->attr; | |
312 | struct hw_perf_event *hwc = &event->hw; | |
313 | int err; | |
314 | u64 ev; | |
315 | ||
316 | switch (attr->type) { | |
317 | case PERF_TYPE_RAW: | |
318 | /* Raw events are used to access counters directly, | |
319 | * hence do not permit excludes */ | |
320 | if (attr->exclude_kernel || attr->exclude_user || | |
321 | attr->exclude_hv) | |
322 | return -EOPNOTSUPP; | |
323 | ev = attr->config; | |
324 | break; | |
325 | ||
326 | case PERF_TYPE_HARDWARE: | |
327 | ev = attr->config; | |
328 | /* Count user space (problem-state) only */ | |
329 | if (!attr->exclude_user && attr->exclude_kernel) { | |
330 | if (ev >= ARRAY_SIZE(cpumf_generic_events_user)) | |
331 | return -EOPNOTSUPP; | |
332 | ev = cpumf_generic_events_user[ev]; | |
333 | ||
334 | /* No support for kernel space counters only */ | |
335 | } else if (!attr->exclude_kernel && attr->exclude_user) { | |
336 | return -EOPNOTSUPP; | |
337 | ||
338 | /* Count user and kernel space */ | |
339 | } else { | |
340 | if (ev >= ARRAY_SIZE(cpumf_generic_events_basic)) | |
341 | return -EOPNOTSUPP; | |
342 | ev = cpumf_generic_events_basic[ev]; | |
343 | } | |
344 | break; | |
345 | ||
346 | default: | |
347 | return -ENOENT; | |
348 | } | |
349 | ||
350 | if (ev == -1) | |
351 | return -ENOENT; | |
352 | ||
20ba46da | 353 | if (ev > PERF_CPUM_CF_MAX_CTR) |
212188a5 HB |
354 | return -EINVAL; |
355 | ||
212188a5 HB |
356 | /* Use the hardware perf event structure to store the counter number |
357 | * in 'config' member and the counter set to which the counter belongs | |
358 | * in the 'config_base'. The counter set (config_base) is then used | |
359 | * to enable/disable the counters. | |
360 | */ | |
361 | hwc->config = ev; | |
362 | hwc->config_base = get_counter_set(ev); | |
363 | ||
212188a5 HB |
364 | /* Initialize for using the CPU-measurement counter facility */ |
365 | if (!atomic_inc_not_zero(&num_events)) { | |
366 | mutex_lock(&pmc_reserve_mutex); | |
367 | if (atomic_read(&num_events) == 0 && reserve_pmc_hardware()) | |
368 | err = -EBUSY; | |
369 | else | |
370 | atomic_inc(&num_events); | |
371 | mutex_unlock(&pmc_reserve_mutex); | |
372 | } | |
373 | event->destroy = hw_perf_event_destroy; | |
374 | ||
375 | /* Finally, validate version and authorization of the counter set */ | |
376 | err = validate_ctr_auth(hwc); | |
377 | if (!err) | |
378 | err = validate_ctr_version(hwc); | |
379 | ||
380 | return err; | |
381 | } | |
382 | ||
383 | static int cpumf_pmu_event_init(struct perf_event *event) | |
384 | { | |
385 | int err; | |
386 | ||
387 | switch (event->attr.type) { | |
388 | case PERF_TYPE_HARDWARE: | |
389 | case PERF_TYPE_HW_CACHE: | |
390 | case PERF_TYPE_RAW: | |
391 | err = __hw_perf_event_init(event); | |
392 | break; | |
393 | default: | |
394 | return -ENOENT; | |
395 | } | |
396 | ||
397 | if (unlikely(err) && event->destroy) | |
398 | event->destroy(event); | |
399 | ||
400 | return err; | |
401 | } | |
402 | ||
403 | static int hw_perf_event_reset(struct perf_event *event) | |
404 | { | |
405 | u64 prev, new; | |
406 | int err; | |
407 | ||
408 | do { | |
409 | prev = local64_read(&event->hw.prev_count); | |
410 | err = ecctr(event->hw.config, &new); | |
411 | if (err) { | |
412 | if (err != 3) | |
413 | break; | |
414 | /* The counter is not (yet) available. This | |
415 | * might happen if the counter set to which | |
416 | * this counter belongs is in the disabled | |
417 | * state. | |
418 | */ | |
419 | new = 0; | |
420 | } | |
421 | } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); | |
422 | ||
423 | return err; | |
424 | } | |
425 | ||
426 | static int hw_perf_event_update(struct perf_event *event) | |
427 | { | |
428 | u64 prev, new, delta; | |
429 | int err; | |
430 | ||
431 | do { | |
432 | prev = local64_read(&event->hw.prev_count); | |
433 | err = ecctr(event->hw.config, &new); | |
434 | if (err) | |
435 | goto out; | |
436 | } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); | |
437 | ||
438 | delta = (prev <= new) ? new - prev | |
439 | : (-1ULL - prev) + new + 1; /* overflow */ | |
440 | local64_add(delta, &event->count); | |
441 | out: | |
442 | return err; | |
443 | } | |
444 | ||
445 | static void cpumf_pmu_read(struct perf_event *event) | |
446 | { | |
447 | if (event->hw.state & PERF_HES_STOPPED) | |
448 | return; | |
449 | ||
450 | hw_perf_event_update(event); | |
451 | } | |
452 | ||
453 | static void cpumf_pmu_start(struct perf_event *event, int flags) | |
454 | { | |
eb7e7d76 | 455 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
456 | struct hw_perf_event *hwc = &event->hw; |
457 | ||
458 | if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) | |
459 | return; | |
460 | ||
461 | if (WARN_ON_ONCE(hwc->config == -1)) | |
462 | return; | |
463 | ||
464 | if (flags & PERF_EF_RELOAD) | |
465 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
466 | ||
467 | hwc->state = 0; | |
468 | ||
469 | /* (Re-)enable and activate the counter set */ | |
470 | ctr_set_enable(&cpuhw->state, hwc->config_base); | |
471 | ctr_set_start(&cpuhw->state, hwc->config_base); | |
472 | ||
473 | /* The counter set to which this counter belongs can be already active. | |
474 | * Because all counters in a set are active, the event->hw.prev_count | |
475 | * needs to be synchronized. At this point, the counter set can be in | |
476 | * the inactive or disabled state. | |
477 | */ | |
478 | hw_perf_event_reset(event); | |
479 | ||
480 | /* increment refcount for this counter set */ | |
481 | atomic_inc(&cpuhw->ctr_set[hwc->config_base]); | |
482 | } | |
483 | ||
484 | static void cpumf_pmu_stop(struct perf_event *event, int flags) | |
485 | { | |
eb7e7d76 | 486 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
487 | struct hw_perf_event *hwc = &event->hw; |
488 | ||
489 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
490 | /* Decrement reference count for this counter set and if this | |
491 | * is the last used counter in the set, clear activation | |
492 | * control and set the counter set state to inactive. | |
493 | */ | |
494 | if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) | |
495 | ctr_set_stop(&cpuhw->state, hwc->config_base); | |
496 | event->hw.state |= PERF_HES_STOPPED; | |
497 | } | |
498 | ||
499 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
500 | hw_perf_event_update(event); | |
501 | event->hw.state |= PERF_HES_UPTODATE; | |
502 | } | |
503 | } | |
504 | ||
505 | static int cpumf_pmu_add(struct perf_event *event, int flags) | |
506 | { | |
eb7e7d76 | 507 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
508 | |
509 | /* Check authorization for the counter set to which this | |
510 | * counter belongs. | |
511 | * For group events transaction, the authorization check is | |
512 | * done in cpumf_pmu_commit_txn(). | |
513 | */ | |
8f3e5684 | 514 | if (!(cpuhw->txn_flags & PERF_PMU_TXN_ADD)) |
212188a5 | 515 | if (validate_ctr_auth(&event->hw)) |
58f8e9da | 516 | return -ENOENT; |
212188a5 HB |
517 | |
518 | ctr_set_enable(&cpuhw->state, event->hw.config_base); | |
519 | event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
520 | ||
521 | if (flags & PERF_EF_START) | |
522 | cpumf_pmu_start(event, PERF_EF_RELOAD); | |
523 | ||
524 | perf_event_update_userpage(event); | |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | static void cpumf_pmu_del(struct perf_event *event, int flags) | |
530 | { | |
eb7e7d76 | 531 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
532 | |
533 | cpumf_pmu_stop(event, PERF_EF_UPDATE); | |
534 | ||
535 | /* Check if any counter in the counter set is still used. If not used, | |
536 | * change the counter set to the disabled state. This also clears the | |
537 | * content of all counters in the set. | |
538 | * | |
539 | * When a new perf event has been added but not yet started, this can | |
540 | * clear enable control and resets all counters in a set. Therefore, | |
541 | * cpumf_pmu_start() always has to reenable a counter set. | |
542 | */ | |
543 | if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base])) | |
544 | ctr_set_disable(&cpuhw->state, event->hw.config_base); | |
545 | ||
546 | perf_event_update_userpage(event); | |
547 | } | |
548 | ||
549 | /* | |
550 | * Start group events scheduling transaction. | |
551 | * Set flags to perform a single test at commit time. | |
fbbe0701 SB |
552 | * |
553 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
554 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
555 | * transactions. | |
212188a5 | 556 | */ |
fbbe0701 | 557 | static void cpumf_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
212188a5 | 558 | { |
eb7e7d76 | 559 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 | 560 | |
fbbe0701 SB |
561 | WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ |
562 | ||
563 | cpuhw->txn_flags = txn_flags; | |
564 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
565 | return; | |
566 | ||
212188a5 | 567 | perf_pmu_disable(pmu); |
212188a5 HB |
568 | cpuhw->tx_state = cpuhw->state; |
569 | } | |
570 | ||
571 | /* | |
572 | * Stop and cancel a group events scheduling tranctions. | |
573 | * Assumes cpumf_pmu_del() is called for each successful added | |
574 | * cpumf_pmu_add() during the transaction. | |
575 | */ | |
576 | static void cpumf_pmu_cancel_txn(struct pmu *pmu) | |
577 | { | |
fbbe0701 | 578 | unsigned int txn_flags; |
eb7e7d76 | 579 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 | 580 | |
fbbe0701 SB |
581 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
582 | ||
583 | txn_flags = cpuhw->txn_flags; | |
584 | cpuhw->txn_flags = 0; | |
585 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
586 | return; | |
587 | ||
212188a5 HB |
588 | WARN_ON(cpuhw->tx_state != cpuhw->state); |
589 | ||
212188a5 HB |
590 | perf_pmu_enable(pmu); |
591 | } | |
592 | ||
593 | /* | |
594 | * Commit the group events scheduling transaction. On success, the | |
595 | * transaction is closed. On error, the transaction is kept open | |
596 | * until cpumf_pmu_cancel_txn() is called. | |
597 | */ | |
598 | static int cpumf_pmu_commit_txn(struct pmu *pmu) | |
599 | { | |
eb7e7d76 | 600 | struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); |
212188a5 HB |
601 | u64 state; |
602 | ||
fbbe0701 SB |
603 | WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ |
604 | ||
605 | if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { | |
606 | cpuhw->txn_flags = 0; | |
607 | return 0; | |
608 | } | |
609 | ||
212188a5 HB |
610 | /* check if the updated state can be scheduled */ |
611 | state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); | |
612 | state >>= CPUMF_LCCTL_ENABLE_SHIFT; | |
613 | if ((state & cpuhw->info.auth_ctl) != state) | |
58f8e9da | 614 | return -ENOENT; |
212188a5 | 615 | |
fbbe0701 | 616 | cpuhw->txn_flags = 0; |
212188a5 HB |
617 | perf_pmu_enable(pmu); |
618 | return 0; | |
619 | } | |
620 | ||
621 | /* Performance monitoring unit for s390x */ | |
622 | static struct pmu cpumf_pmu = { | |
9254e70c HB |
623 | .task_ctx_nr = perf_sw_context, |
624 | .capabilities = PERF_PMU_CAP_NO_INTERRUPT, | |
212188a5 HB |
625 | .pmu_enable = cpumf_pmu_enable, |
626 | .pmu_disable = cpumf_pmu_disable, | |
627 | .event_init = cpumf_pmu_event_init, | |
628 | .add = cpumf_pmu_add, | |
629 | .del = cpumf_pmu_del, | |
630 | .start = cpumf_pmu_start, | |
631 | .stop = cpumf_pmu_stop, | |
632 | .read = cpumf_pmu_read, | |
633 | .start_txn = cpumf_pmu_start_txn, | |
634 | .commit_txn = cpumf_pmu_commit_txn, | |
635 | .cancel_txn = cpumf_pmu_cancel_txn, | |
636 | }; | |
637 | ||
4f0f8217 | 638 | static int cpumf_pmf_setup(unsigned int cpu, int flags) |
212188a5 | 639 | { |
4f0f8217 TG |
640 | local_irq_disable(); |
641 | setup_pmc_cpu(&flags); | |
642 | local_irq_enable(); | |
643 | return 0; | |
644 | } | |
645 | ||
646 | static int s390_pmu_online_cpu(unsigned int cpu) | |
647 | { | |
648 | return cpumf_pmf_setup(cpu, PMC_INIT); | |
649 | } | |
212188a5 | 650 | |
4f0f8217 TG |
651 | static int s390_pmu_offline_cpu(unsigned int cpu) |
652 | { | |
653 | return cpumf_pmf_setup(cpu, PMC_RELEASE); | |
212188a5 HB |
654 | } |
655 | ||
656 | static int __init cpumf_pmu_init(void) | |
657 | { | |
658 | int rc; | |
659 | ||
660 | if (!cpum_cf_avail()) | |
661 | return -ENODEV; | |
662 | ||
663 | /* clear bit 15 of cr0 to unauthorize problem-state to | |
664 | * extract measurement counters */ | |
665 | ctl_clear_bit(0, 48); | |
666 | ||
667 | /* register handler for measurement-alert interruptions */ | |
1dad093b TH |
668 | rc = register_external_irq(EXT_IRQ_MEASURE_ALERT, |
669 | cpumf_measurement_alert); | |
212188a5 HB |
670 | if (rc) { |
671 | pr_err("Registering for CPU-measurement alerts " | |
672 | "failed with rc=%i\n", rc); | |
4f0f8217 | 673 | return rc; |
212188a5 HB |
674 | } |
675 | ||
c7168325 | 676 | cpumf_pmu.attr_groups = cpumf_cf_event_group(); |
212188a5 HB |
677 | rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW); |
678 | if (rc) { | |
679 | pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc); | |
1dad093b TH |
680 | unregister_external_irq(EXT_IRQ_MEASURE_ALERT, |
681 | cpumf_measurement_alert); | |
4f0f8217 | 682 | return rc; |
212188a5 | 683 | } |
4f0f8217 | 684 | return cpuhp_setup_state(CPUHP_AP_PERF_S390_CF_ONLINE, |
73c1b41e | 685 | "perf/s390/cf:online", |
4f0f8217 | 686 | s390_pmu_online_cpu, s390_pmu_offline_cpu); |
212188a5 HB |
687 | } |
688 | early_initcall(cpumf_pmu_init); |