projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * arch/s390/kernel/reipl.S | |
| 3 | * | |
| 4 | * S390 version | |
| 5 | * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
| 6 | * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com) | |
| 25d83cbf | 7 | Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) |
| 1da177e4 LT |
8 | */ |
| 9 | ||
| 10 | #include <asm/lowcore.h> | |
| c5dd8586 HC |
11 | |
| 12 | # | |
| 13 | # do_reipl_asm | |
| 14 | # Parameter: r2 = schid of reipl device | |
| 15 | # | |
| 16 | ||
| ff6b8ea6 MH |
17 | .globl do_reipl_asm |
| 18 | do_reipl_asm: basr %r13,0 | |
| 15e9b586 HC |
19 | .Lpg0: lpswe .Lnewpsw-.Lpg0(%r13) |
| 20 | .Lpg1: # do store status of all registers | |
| ff6b8ea6 | 21 | |
| 15e9b586 | 22 | stg %r1,.Lregsave-.Lpg0(%r13) |
| ff6b8ea6 MH |
23 | lghi %r1,0x1000 |
| 24 | stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1) | |
| 25 | lg %r0,.Lregsave-.Lpg0(%r13) | |
| 26 | stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1) | |
| 27 | stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1) | |
| 28 | stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1) | |
| c5dd8586 HC |
29 | lg %r10,.Ldump_pfx-.Lpg0(%r13) |
| 30 | mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10) | |
| ff6b8ea6 MH |
31 | stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1) |
| 32 | stckc .Lclkcmp-.Lpg0(%r13) | |
| 33 | mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(8,%r1),.Lclkcmp-.Lpg0(%r13) | |
| 34 | stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1) | |
| 35 | stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1) | |
| 36 | ||
| 15e9b586 | 37 | lctlg %c6,%c6,.Lall-.Lpg0(%r13) |
| 25d83cbf HC |
38 | lgr %r1,%r2 |
| 39 | mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13) | |
| 40 | stsch .Lschib-.Lpg0(%r13) | |
| 41 | oi .Lschib+5-.Lpg0(%r13),0x84 | |
| 42 | .Lecs: xi .Lschib+27-.Lpg0(%r13),0x01 | |
| 43 | msch .Lschib-.Lpg0(%r13) | |
| 44 | lghi %r0,5 | |
| 45 | .Lssch: ssch .Liplorb-.Lpg0(%r13) | |
| 1da177e4 | 46 | jz .L001 |
| 25d83cbf | 47 | brct %r0,.Lssch |
| 1da177e4 | 48 | bas %r14,.Ldisab-.Lpg0(%r13) |
| 25d83cbf HC |
49 | .L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13) |
| 50 | .Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13) | |
| 1da177e4 LT |
51 | .Lcont: c %r1,__LC_SUBCHANNEL_ID |
| 52 | jnz .Ltpi | |
| 53 | clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13) | |
| 54 | jnz .Ltpi | |
| 25d83cbf | 55 | tsch .Liplirb-.Lpg0(%r13) |
| 1da177e4 | 56 | tm .Liplirb+9-.Lpg0(%r13),0xbf |
| 25d83cbf HC |
57 | jz .L002 |
| 58 | bas %r14,.Ldisab-.Lpg0(%r13) | |
| 59 | .L002: tm .Liplirb+8-.Lpg0(%r13),0xf3 | |
| 60 | jz .L003 | |
| 61 | bas %r14,.Ldisab-.Lpg0(%r13) | |
| 15e9b586 | 62 | .L003: st %r1,__LC_SUBCHANNEL_ID |
| 25d83cbf HC |
63 | lhi %r1,0 # mode 0 = esa |
| 64 | slr %r0,%r0 # set cpuid to zero | |
| 65 | sigp %r1,%r0,0x12 # switch to esa mode | |
| 66 | lpsw 0 | |
| 67 | .Ldisab: sll %r14,1 | |
| 68 | srl %r14,1 # need to kill hi bit to avoid specification exceptions. | |
| 69 | st %r14,.Ldispsw+12-.Lpg0(%r13) | |
| 1da177e4 | 70 | lpswe .Ldispsw-.Lpg0(%r13) |
| 25d83cbf | 71 | .align 8 |
| ff6b8ea6 | 72 | .Lclkcmp: .quad 0x0000000000000000 |
| 1da177e4 | 73 | .Lall: .quad 0x00000000ff000000 |
| c5dd8586 | 74 | .Ldump_pfx: .quad dump_prefix_page |
| ff6b8ea6 | 75 | .Lregsave: .quad 0x0000000000000000 |
| 25d83cbf | 76 | .align 16 |
| 1da177e4 LT |
77 | /* |
| 78 | * These addresses have to be 31 bit otherwise | |
| 79 | * the sigp will throw a specifcation exception | |
| 80 | * when switching to ESA mode as bit 31 be set | |
| 81 | * in the ESA psw. | |
| 82 | * Bit 31 of the addresses has to be 0 for the | |
| 83 | * 31bit lpswe instruction a fact they appear to have | |
| 84 | * ommited from the pop. | |
| 85 | */ | |
| 25d83cbf HC |
86 | .Lnewpsw: .quad 0x0000000080000000 |
| 87 | .quad .Lpg1 | |
| 88 | .Lpcnew: .quad 0x0000000080000000 | |
| 89 | .quad .Lecs | |
| 90 | .Lionew: .quad 0x0000000080000000 | |
| 91 | .quad .Lcont | |
| 1da177e4 | 92 | .Lwaitpsw: .quad 0x0202000080000000 |
| 25d83cbf HC |
93 | .quad .Ltpi |
| 94 | .Ldispsw: .quad 0x0002000080000000 | |
| 95 | .quad 0x0000000000000000 | |
| 96 | .Liplccws: .long 0x02000000,0x60000018 | |
| 97 | .long 0x08000008,0x20000001 | |
| 1da177e4 LT |
98 | .Liplorb: .long 0x0049504c,0x0040ff80 |
| 99 | .long 0x00000000+.Liplccws | |
| 25d83cbf HC |
100 | .Lschib: .long 0x00000000,0x00000000 |
| 101 | .long 0x00000000,0x00000000 | |
| 102 | .long 0x00000000,0x00000000 | |
| 103 | .long 0x00000000,0x00000000 | |
| 104 | .long 0x00000000,0x00000000 | |
| 105 | .long 0x00000000,0x00000000 | |
| 1da177e4 LT |
106 | .Liplirb: .long 0x00000000,0x00000000 |
| 107 | .long 0x00000000,0x00000000 | |
| 108 | .long 0x00000000,0x00000000 | |
| 109 | .long 0x00000000,0x00000000 | |
| 110 | .long 0x00000000,0x00000000 | |
| 111 | .long 0x00000000,0x00000000 | |
| 112 | .long 0x00000000,0x00000000 | |
| 113 | .long 0x00000000,0x00000000 |