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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/smp.c | |
3 | * | |
155af2f9 | 4 | * Copyright IBM Corp. 1999, 2009 |
1da177e4 | 5 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), |
39ce010d HC |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) |
7 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
13 | * We work with logical cpu numbering everywhere we can. The only | |
14 | * functions using the real cpu address (got from STAP) are the sigp | |
15 | * functions. For all other functions we use the identity mapping. | |
16 | * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is | |
17 | * used e.g. to find the idle task belonging to a logical cpu. Every array | |
18 | * in the kernel is sorted by the logical cpu number and not by the physical | |
19 | * one which is causing all the confusion with __cpu_logical_map and | |
20 | * cpu_number_map in other architectures. | |
21 | */ | |
22 | ||
395d31d4 MS |
23 | #define KMSG_COMPONENT "cpu" |
24 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
25 | ||
1da177e4 LT |
26 | #include <linux/module.h> |
27 | #include <linux/init.h> | |
1da177e4 | 28 | #include <linux/mm.h> |
4e950f6f | 29 | #include <linux/err.h> |
1da177e4 LT |
30 | #include <linux/spinlock.h> |
31 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
32 | #include <linux/delay.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/interrupt.h> | |
3324e60a | 35 | #include <linux/irqflags.h> |
1da177e4 | 36 | #include <linux/cpu.h> |
2b67fc46 | 37 | #include <linux/timex.h> |
411ed322 | 38 | #include <linux/bootmem.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
cbb870c8 | 40 | #include <asm/asm-offsets.h> |
46b05d26 | 41 | #include <asm/ipl.h> |
2b67fc46 | 42 | #include <asm/setup.h> |
1da177e4 LT |
43 | #include <asm/sigp.h> |
44 | #include <asm/pgalloc.h> | |
45 | #include <asm/irq.h> | |
46 | #include <asm/s390_ext.h> | |
47 | #include <asm/cpcmd.h> | |
48 | #include <asm/tlbflush.h> | |
2b67fc46 | 49 | #include <asm/timer.h> |
411ed322 | 50 | #include <asm/lowcore.h> |
08d07968 | 51 | #include <asm/sclp.h> |
76d4e00a | 52 | #include <asm/cputime.h> |
c742b31c | 53 | #include <asm/vdso.h> |
4bb5e07b | 54 | #include <asm/cpu.h> |
a806170e | 55 | #include "entry.h" |
1da177e4 | 56 | |
fb380aad | 57 | /* logical cpu to cpu address */ |
a93b8ec1 | 58 | unsigned short __cpu_logical_map[NR_CPUS]; |
fb380aad | 59 | |
1da177e4 LT |
60 | static struct task_struct *current_set[NR_CPUS]; |
61 | ||
08d07968 HC |
62 | static u8 smp_cpu_type; |
63 | static int smp_use_sigp_detection; | |
64 | ||
65 | enum s390_cpu_state { | |
66 | CPU_STATE_STANDBY, | |
67 | CPU_STATE_CONFIGURED, | |
68 | }; | |
69 | ||
dbd70fb4 | 70 | DEFINE_MUTEX(smp_cpu_state_mutex); |
c10fde0d | 71 | int smp_cpu_polarization[NR_CPUS]; |
08d07968 | 72 | static int smp_cpu_state[NR_CPUS]; |
c10fde0d | 73 | static int cpu_management; |
08d07968 HC |
74 | |
75 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
08d07968 | 76 | |
a93b8ec1 | 77 | static void smp_ext_bitcall(int, int); |
1da177e4 | 78 | |
a93b8ec1 | 79 | static int raw_cpu_stopped(int cpu) |
5c0b912e | 80 | { |
a93b8ec1 | 81 | u32 status; |
5c0b912e | 82 | |
a93b8ec1 | 83 | switch (raw_sigp_ps(&status, 0, cpu, sigp_sense)) { |
5c0b912e HC |
84 | case sigp_status_stored: |
85 | /* Check for stopped and check stop state */ | |
86 | if (status & 0x50) | |
87 | return 1; | |
88 | break; | |
89 | default: | |
90 | break; | |
91 | } | |
92 | return 0; | |
93 | } | |
94 | ||
a93b8ec1 HC |
95 | static inline int cpu_stopped(int cpu) |
96 | { | |
97 | return raw_cpu_stopped(cpu_logical_map(cpu)); | |
98 | } | |
99 | ||
2c2df118 HC |
100 | void smp_switch_to_ipl_cpu(void (*func)(void *), void *data) |
101 | { | |
102 | struct _lowcore *lc, *current_lc; | |
103 | struct stack_frame *sf; | |
104 | struct pt_regs *regs; | |
105 | unsigned long sp; | |
106 | ||
107 | if (smp_processor_id() == 0) | |
108 | func(data); | |
109 | __load_psw_mask(PSW_BASE_BITS | PSW_DEFAULT_KEY); | |
110 | /* Disable lowcore protection */ | |
111 | __ctl_clear_bit(0, 28); | |
112 | current_lc = lowcore_ptr[smp_processor_id()]; | |
113 | lc = lowcore_ptr[0]; | |
114 | if (!lc) | |
115 | lc = current_lc; | |
116 | lc->restart_psw.mask = PSW_BASE_BITS | PSW_DEFAULT_KEY; | |
117 | lc->restart_psw.addr = PSW_ADDR_AMODE | (unsigned long) smp_restart_cpu; | |
118 | if (!cpu_online(0)) | |
119 | smp_switch_to_cpu(func, data, 0, stap(), __cpu_logical_map[0]); | |
a93b8ec1 | 120 | while (sigp(0, sigp_stop_and_store_status) == sigp_busy) |
2c2df118 HC |
121 | cpu_relax(); |
122 | sp = lc->panic_stack; | |
123 | sp -= sizeof(struct pt_regs); | |
124 | regs = (struct pt_regs *) sp; | |
125 | memcpy(®s->gprs, ¤t_lc->gpregs_save_area, sizeof(regs->gprs)); | |
cbb870c8 | 126 | regs->psw = lc->psw_save_area; |
2c2df118 HC |
127 | sp -= STACK_FRAME_OVERHEAD; |
128 | sf = (struct stack_frame *) sp; | |
129 | sf->back_chain = regs->gprs[15]; | |
130 | smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]); | |
131 | } | |
132 | ||
677d7623 | 133 | void smp_send_stop(void) |
1da177e4 | 134 | { |
39ce010d | 135 | int cpu, rc; |
1da177e4 | 136 | |
677d7623 HC |
137 | /* Disable all interrupts/machine checks */ |
138 | __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK); | |
3324e60a | 139 | trace_hardirqs_off(); |
1da177e4 | 140 | |
677d7623 | 141 | /* stop all processors */ |
1da177e4 LT |
142 | for_each_online_cpu(cpu) { |
143 | if (cpu == smp_processor_id()) | |
144 | continue; | |
145 | do { | |
a93b8ec1 | 146 | rc = sigp(cpu, sigp_stop); |
39ce010d | 147 | } while (rc == sigp_busy); |
1da177e4 | 148 | |
5c0b912e | 149 | while (!cpu_stopped(cpu)) |
c6b5b847 HC |
150 | cpu_relax(); |
151 | } | |
152 | } | |
153 | ||
1da177e4 LT |
154 | /* |
155 | * This is the main routine where commands issued by other | |
156 | * cpus are handled. | |
157 | */ | |
158 | ||
f6649a7e MS |
159 | static void do_ext_call_interrupt(unsigned int ext_int_code, |
160 | unsigned int param32, unsigned long param64) | |
1da177e4 | 161 | { |
39ce010d | 162 | unsigned long bits; |
1da177e4 | 163 | |
052ff461 | 164 | kstat_cpu(smp_processor_id()).irqs[EXTINT_IPI]++; |
39ce010d HC |
165 | /* |
166 | * handle bit signal external calls | |
167 | * | |
168 | * For the ec_schedule signal we have to do nothing. All the work | |
169 | * is done automatically when we return from the interrupt. | |
170 | */ | |
1da177e4 LT |
171 | bits = xchg(&S390_lowcore.ext_call_fast, 0); |
172 | ||
39ce010d | 173 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
174 | generic_smp_call_function_interrupt(); |
175 | ||
176 | if (test_bit(ec_call_function_single, &bits)) | |
177 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
178 | } |
179 | ||
180 | /* | |
181 | * Send an external call sigp to another cpu and return without waiting | |
182 | * for its completion. | |
183 | */ | |
a93b8ec1 | 184 | static void smp_ext_bitcall(int cpu, int sig) |
1da177e4 | 185 | { |
39ce010d HC |
186 | /* |
187 | * Set signaling bit in lowcore of target cpu and kick it | |
188 | */ | |
1da177e4 | 189 | set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); |
a93b8ec1 | 190 | while (sigp(cpu, sigp_emergency_signal) == sigp_busy) |
1da177e4 LT |
191 | udelay(10); |
192 | } | |
193 | ||
630cd046 | 194 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
195 | { |
196 | int cpu; | |
197 | ||
630cd046 | 198 | for_each_cpu(cpu, mask) |
ca9fc75a HC |
199 | smp_ext_bitcall(cpu, ec_call_function); |
200 | } | |
201 | ||
202 | void arch_send_call_function_single_ipi(int cpu) | |
203 | { | |
204 | smp_ext_bitcall(cpu, ec_call_function_single); | |
205 | } | |
206 | ||
347a8dc3 | 207 | #ifndef CONFIG_64BIT |
1da177e4 LT |
208 | /* |
209 | * this function sends a 'purge tlb' signal to another CPU. | |
210 | */ | |
a806170e | 211 | static void smp_ptlb_callback(void *info) |
1da177e4 | 212 | { |
ba8a9229 | 213 | __tlb_flush_local(); |
1da177e4 LT |
214 | } |
215 | ||
216 | void smp_ptlb_all(void) | |
217 | { | |
15c8b6c1 | 218 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
219 | } |
220 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 221 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
222 | |
223 | /* | |
224 | * this function sends a 'reschedule' IPI to another CPU. | |
225 | * it goes straight through and wastes no time serializing | |
226 | * anything. Worst case is that we lose a reschedule ... | |
227 | */ | |
228 | void smp_send_reschedule(int cpu) | |
229 | { | |
39ce010d | 230 | smp_ext_bitcall(cpu, ec_schedule); |
1da177e4 LT |
231 | } |
232 | ||
233 | /* | |
234 | * parameter area for the set/clear control bit callbacks | |
235 | */ | |
94c12cc7 | 236 | struct ec_creg_mask_parms { |
1da177e4 LT |
237 | unsigned long orvals[16]; |
238 | unsigned long andvals[16]; | |
94c12cc7 | 239 | }; |
1da177e4 LT |
240 | |
241 | /* | |
242 | * callback for setting/clearing control bits | |
243 | */ | |
39ce010d HC |
244 | static void smp_ctl_bit_callback(void *info) |
245 | { | |
94c12cc7 | 246 | struct ec_creg_mask_parms *pp = info; |
1da177e4 LT |
247 | unsigned long cregs[16]; |
248 | int i; | |
39ce010d | 249 | |
94c12cc7 MS |
250 | __ctl_store(cregs, 0, 15); |
251 | for (i = 0; i <= 15; i++) | |
1da177e4 | 252 | cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i]; |
94c12cc7 | 253 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
254 | } |
255 | ||
256 | /* | |
257 | * Set a bit in a control register of all cpus | |
258 | */ | |
94c12cc7 MS |
259 | void smp_ctl_set_bit(int cr, int bit) |
260 | { | |
261 | struct ec_creg_mask_parms parms; | |
1da177e4 | 262 | |
94c12cc7 MS |
263 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
264 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 265 | parms.orvals[cr] = 1 << bit; |
15c8b6c1 | 266 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 267 | } |
39ce010d | 268 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
269 | |
270 | /* | |
271 | * Clear a bit in a control register of all cpus | |
272 | */ | |
94c12cc7 MS |
273 | void smp_ctl_clear_bit(int cr, int bit) |
274 | { | |
275 | struct ec_creg_mask_parms parms; | |
1da177e4 | 276 | |
94c12cc7 MS |
277 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
278 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
1da177e4 | 279 | parms.andvals[cr] = ~(1L << bit); |
15c8b6c1 | 280 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 281 | } |
39ce010d | 282 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 283 | |
59f2e69d | 284 | #ifdef CONFIG_ZFCPDUMP |
411ed322 | 285 | |
285f6722 | 286 | static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) |
411ed322 | 287 | { |
411ed322 MH |
288 | if (ipl_info.type != IPL_TYPE_FCP_DUMP) |
289 | return; | |
285f6722 | 290 | if (cpu >= NR_CPUS) { |
395d31d4 MS |
291 | pr_warning("CPU %i exceeds the maximum %i and is excluded from " |
292 | "the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 293 | return; |
411ed322 | 294 | } |
f64ca217 | 295 | zfcpdump_save_areas[cpu] = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
a93b8ec1 | 296 | while (raw_sigp(phy_cpu, sigp_stop_and_store_status) == sigp_busy) |
285f6722 | 297 | cpu_relax(); |
92fe3132 MH |
298 | memcpy_real(zfcpdump_save_areas[cpu], |
299 | (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE, | |
300 | sizeof(struct save_area)); | |
411ed322 MH |
301 | } |
302 | ||
f64ca217 | 303 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
411ed322 MH |
304 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); |
305 | ||
306 | #else | |
285f6722 HC |
307 | |
308 | static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { } | |
309 | ||
59f2e69d | 310 | #endif /* CONFIG_ZFCPDUMP */ |
411ed322 | 311 | |
08d07968 HC |
312 | static int cpu_known(int cpu_id) |
313 | { | |
314 | int cpu; | |
315 | ||
316 | for_each_present_cpu(cpu) { | |
317 | if (__cpu_logical_map[cpu] == cpu_id) | |
318 | return 1; | |
319 | } | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static int smp_rescan_cpus_sigp(cpumask_t avail) | |
324 | { | |
325 | int cpu_id, logical_cpu; | |
326 | ||
93632d1b RR |
327 | logical_cpu = cpumask_first(&avail); |
328 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 329 | return 0; |
4bb5e07b | 330 | for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) { |
08d07968 HC |
331 | if (cpu_known(cpu_id)) |
332 | continue; | |
333 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 334 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
335 | if (!cpu_stopped(logical_cpu)) |
336 | continue; | |
337 | cpu_set(logical_cpu, cpu_present_map); | |
338 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
339 | logical_cpu = cpumask_next(logical_cpu, &avail); |
340 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
341 | break; |
342 | } | |
343 | return 0; | |
344 | } | |
345 | ||
48483b32 | 346 | static int smp_rescan_cpus_sclp(cpumask_t avail) |
08d07968 HC |
347 | { |
348 | struct sclp_cpu_info *info; | |
349 | int cpu_id, logical_cpu, cpu; | |
350 | int rc; | |
351 | ||
93632d1b RR |
352 | logical_cpu = cpumask_first(&avail); |
353 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 354 | return 0; |
48483b32 | 355 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
08d07968 HC |
356 | if (!info) |
357 | return -ENOMEM; | |
358 | rc = sclp_get_cpu_info(info); | |
359 | if (rc) | |
360 | goto out; | |
361 | for (cpu = 0; cpu < info->combined; cpu++) { | |
362 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
363 | continue; | |
364 | cpu_id = info->cpu[cpu].address; | |
365 | if (cpu_known(cpu_id)) | |
366 | continue; | |
367 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 368 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
369 | cpu_set(logical_cpu, cpu_present_map); |
370 | if (cpu >= info->configured) | |
371 | smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY; | |
372 | else | |
373 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
374 | logical_cpu = cpumask_next(logical_cpu, &avail); |
375 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
376 | break; |
377 | } | |
378 | out: | |
48483b32 | 379 | kfree(info); |
08d07968 HC |
380 | return rc; |
381 | } | |
382 | ||
1e489518 | 383 | static int __smp_rescan_cpus(void) |
08d07968 HC |
384 | { |
385 | cpumask_t avail; | |
386 | ||
48483b32 | 387 | cpus_xor(avail, cpu_possible_map, cpu_present_map); |
08d07968 HC |
388 | if (smp_use_sigp_detection) |
389 | return smp_rescan_cpus_sigp(avail); | |
390 | else | |
391 | return smp_rescan_cpus_sclp(avail); | |
1da177e4 LT |
392 | } |
393 | ||
48483b32 HC |
394 | static void __init smp_detect_cpus(void) |
395 | { | |
396 | unsigned int cpu, c_cpus, s_cpus; | |
397 | struct sclp_cpu_info *info; | |
398 | u16 boot_cpu_addr, cpu_addr; | |
399 | ||
400 | c_cpus = 1; | |
401 | s_cpus = 0; | |
7b468488 | 402 | boot_cpu_addr = __cpu_logical_map[0]; |
48483b32 HC |
403 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
404 | if (!info) | |
405 | panic("smp_detect_cpus failed to allocate memory\n"); | |
406 | /* Use sigp detection algorithm if sclp doesn't work. */ | |
407 | if (sclp_get_cpu_info(info)) { | |
408 | smp_use_sigp_detection = 1; | |
4bb5e07b | 409 | for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) { |
48483b32 HC |
410 | if (cpu == boot_cpu_addr) |
411 | continue; | |
a93b8ec1 | 412 | if (!raw_cpu_stopped(cpu)) |
48483b32 HC |
413 | continue; |
414 | smp_get_save_area(c_cpus, cpu); | |
415 | c_cpus++; | |
416 | } | |
417 | goto out; | |
418 | } | |
419 | ||
420 | if (info->has_cpu_type) { | |
421 | for (cpu = 0; cpu < info->combined; cpu++) { | |
422 | if (info->cpu[cpu].address == boot_cpu_addr) { | |
423 | smp_cpu_type = info->cpu[cpu].type; | |
424 | break; | |
425 | } | |
426 | } | |
427 | } | |
428 | ||
429 | for (cpu = 0; cpu < info->combined; cpu++) { | |
430 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
431 | continue; | |
432 | cpu_addr = info->cpu[cpu].address; | |
433 | if (cpu_addr == boot_cpu_addr) | |
434 | continue; | |
a93b8ec1 | 435 | if (!raw_cpu_stopped(cpu_addr)) { |
48483b32 HC |
436 | s_cpus++; |
437 | continue; | |
438 | } | |
439 | smp_get_save_area(c_cpus, cpu_addr); | |
440 | c_cpus++; | |
441 | } | |
442 | out: | |
443 | kfree(info); | |
395d31d4 | 444 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 445 | get_online_cpus(); |
1e489518 | 446 | __smp_rescan_cpus(); |
9d40d2e3 | 447 | put_online_cpus(); |
48483b32 HC |
448 | } |
449 | ||
1da177e4 | 450 | /* |
39ce010d | 451 | * Activate a secondary processor. |
1da177e4 | 452 | */ |
ea1f4eec | 453 | int __cpuinit start_secondary(void *cpuvoid) |
1da177e4 | 454 | { |
39ce010d HC |
455 | /* Setup the cpu */ |
456 | cpu_init(); | |
5bfb5d69 | 457 | preempt_disable(); |
d54853ef | 458 | /* Enable TOD clock interrupts on the secondary cpu. */ |
39ce010d | 459 | init_cpu_timer(); |
d54853ef | 460 | /* Enable cpu timer interrupts on the secondary cpu. */ |
39ce010d | 461 | init_cpu_vtimer(); |
1da177e4 | 462 | /* Enable pfault pseudo page faults on this cpu. */ |
29b08d2b HC |
463 | pfault_init(); |
464 | ||
e545a614 MS |
465 | /* call cpu notifiers */ |
466 | notify_cpu_starting(smp_processor_id()); | |
1da177e4 | 467 | /* Mark this cpu as online */ |
ca9fc75a | 468 | ipi_call_lock(); |
1da177e4 | 469 | cpu_set(smp_processor_id(), cpu_online_map); |
ca9fc75a | 470 | ipi_call_unlock(); |
1da177e4 LT |
471 | /* Switch on interrupts */ |
472 | local_irq_enable(); | |
39ce010d | 473 | /* Print info about this processor */ |
7b468488 | 474 | print_cpu_info(); |
39ce010d HC |
475 | /* cpu_idle will call schedule for us */ |
476 | cpu_idle(); | |
477 | return 0; | |
1da177e4 LT |
478 | } |
479 | ||
480 | static void __init smp_create_idle(unsigned int cpu) | |
481 | { | |
482 | struct task_struct *p; | |
483 | ||
484 | /* | |
485 | * don't care about the psw and regs settings since we'll never | |
486 | * reschedule the forked task. | |
487 | */ | |
488 | p = fork_idle(cpu); | |
489 | if (IS_ERR(p)) | |
490 | panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); | |
491 | current_set[cpu] = p; | |
492 | } | |
493 | ||
1cb6bb4b HC |
494 | static int __cpuinit smp_alloc_lowcore(int cpu) |
495 | { | |
496 | unsigned long async_stack, panic_stack; | |
497 | struct _lowcore *lowcore; | |
1cb6bb4b | 498 | |
3fd26a77 | 499 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
1cb6bb4b HC |
500 | if (!lowcore) |
501 | return -ENOMEM; | |
502 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
1cb6bb4b | 503 | panic_stack = __get_free_page(GFP_KERNEL); |
591bb4f6 HC |
504 | if (!panic_stack || !async_stack) |
505 | goto out; | |
98c7b388 HC |
506 | memcpy(lowcore, &S390_lowcore, 512); |
507 | memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512); | |
1cb6bb4b HC |
508 | lowcore->async_stack = async_stack + ASYNC_SIZE; |
509 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
510 | ||
511 | #ifndef CONFIG_64BIT | |
512 | if (MACHINE_HAS_IEEE) { | |
513 | unsigned long save_area; | |
514 | ||
515 | save_area = get_zeroed_page(GFP_KERNEL); | |
516 | if (!save_area) | |
33b1d09e | 517 | goto out; |
1cb6bb4b HC |
518 | lowcore->extended_save_area_addr = (u32) save_area; |
519 | } | |
c742b31c MS |
520 | #else |
521 | if (vdso_alloc_per_cpu(cpu, lowcore)) | |
522 | goto out; | |
1cb6bb4b HC |
523 | #endif |
524 | lowcore_ptr[cpu] = lowcore; | |
525 | return 0; | |
526 | ||
591bb4f6 | 527 | out: |
33b1d09e | 528 | free_page(panic_stack); |
1cb6bb4b | 529 | free_pages(async_stack, ASYNC_ORDER); |
3fd26a77 | 530 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
531 | return -ENOMEM; |
532 | } | |
533 | ||
1cb6bb4b HC |
534 | static void smp_free_lowcore(int cpu) |
535 | { | |
536 | struct _lowcore *lowcore; | |
1cb6bb4b | 537 | |
1cb6bb4b HC |
538 | lowcore = lowcore_ptr[cpu]; |
539 | #ifndef CONFIG_64BIT | |
540 | if (MACHINE_HAS_IEEE) | |
541 | free_page((unsigned long) lowcore->extended_save_area_addr); | |
c742b31c MS |
542 | #else |
543 | vdso_free_per_cpu(cpu, lowcore); | |
1cb6bb4b HC |
544 | #endif |
545 | free_page(lowcore->panic_stack - PAGE_SIZE); | |
546 | free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER); | |
3fd26a77 | 547 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
548 | lowcore_ptr[cpu] = NULL; |
549 | } | |
1cb6bb4b | 550 | |
1da177e4 | 551 | /* Upping and downing of CPUs */ |
1cb6bb4b | 552 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 | 553 | { |
39ce010d | 554 | struct _lowcore *cpu_lowcore; |
a93b8ec1 | 555 | struct task_struct *idle; |
1da177e4 | 556 | struct stack_frame *sf; |
d0d3cdf4 | 557 | u32 lowcore; |
a93b8ec1 | 558 | int ccode; |
1da177e4 | 559 | |
08d07968 HC |
560 | if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) |
561 | return -EIO; | |
1cb6bb4b HC |
562 | if (smp_alloc_lowcore(cpu)) |
563 | return -ENOMEM; | |
d0d3cdf4 | 564 | do { |
a93b8ec1 | 565 | ccode = sigp(cpu, sigp_initial_cpu_reset); |
d0d3cdf4 HC |
566 | if (ccode == sigp_busy) |
567 | udelay(10); | |
568 | if (ccode == sigp_not_operational) | |
569 | goto err_out; | |
570 | } while (ccode == sigp_busy); | |
571 | ||
572 | lowcore = (u32)(unsigned long)lowcore_ptr[cpu]; | |
a93b8ec1 | 573 | while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy) |
d0d3cdf4 | 574 | udelay(10); |
1da177e4 LT |
575 | |
576 | idle = current_set[cpu]; | |
39ce010d | 577 | cpu_lowcore = lowcore_ptr[cpu]; |
1da177e4 | 578 | cpu_lowcore->kernel_stack = (unsigned long) |
39ce010d | 579 | task_stack_page(idle) + THREAD_SIZE; |
1cb6bb4b | 580 | cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle); |
1da177e4 LT |
581 | sf = (struct stack_frame *) (cpu_lowcore->kernel_stack |
582 | - sizeof(struct pt_regs) | |
583 | - sizeof(struct stack_frame)); | |
584 | memset(sf, 0, sizeof(struct stack_frame)); | |
585 | sf->gprs[9] = (unsigned long) sf; | |
586 | cpu_lowcore->save_area[15] = (unsigned long) sf; | |
24d3e210 | 587 | __ctl_store(cpu_lowcore->cregs_save_area, 0, 15); |
050eef36 | 588 | atomic_inc(&init_mm.context.attach_count); |
94c12cc7 MS |
589 | asm volatile( |
590 | " stam 0,15,0(%0)" | |
591 | : : "a" (&cpu_lowcore->access_regs_save_area) : "memory"); | |
1da177e4 | 592 | cpu_lowcore->percpu_offset = __per_cpu_offset[cpu]; |
39ce010d | 593 | cpu_lowcore->current_task = (unsigned long) idle; |
7b468488 | 594 | cpu_lowcore->cpu_nr = cpu; |
591bb4f6 | 595 | cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce; |
25097bf1 | 596 | cpu_lowcore->machine_flags = S390_lowcore.machine_flags; |
dfd9f7ab | 597 | cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func; |
14375bc4 MS |
598 | memcpy(cpu_lowcore->stfle_fac_list, S390_lowcore.stfle_fac_list, |
599 | MAX_FACILITY_BIT/8); | |
1da177e4 | 600 | eieio(); |
699ff13f | 601 | |
a93b8ec1 | 602 | while (sigp(cpu, sigp_restart) == sigp_busy) |
699ff13f | 603 | udelay(10); |
1da177e4 LT |
604 | |
605 | while (!cpu_online(cpu)) | |
606 | cpu_relax(); | |
607 | return 0; | |
d0d3cdf4 HC |
608 | |
609 | err_out: | |
610 | smp_free_lowcore(cpu); | |
611 | return -EIO; | |
1da177e4 LT |
612 | } |
613 | ||
48483b32 | 614 | static int __init setup_possible_cpus(char *s) |
255acee7 | 615 | { |
48483b32 | 616 | int pcpus, cpu; |
255acee7 | 617 | |
48483b32 | 618 | pcpus = simple_strtoul(s, NULL, 0); |
88e01285 HC |
619 | init_cpu_possible(cpumask_of(0)); |
620 | for (cpu = 1; cpu < pcpus && cpu < nr_cpu_ids; cpu++) | |
def6cfb7 | 621 | set_cpu_possible(cpu, true); |
37a33026 HC |
622 | return 0; |
623 | } | |
624 | early_param("possible_cpus", setup_possible_cpus); | |
625 | ||
48483b32 HC |
626 | #ifdef CONFIG_HOTPLUG_CPU |
627 | ||
39ce010d | 628 | int __cpu_disable(void) |
1da177e4 | 629 | { |
94c12cc7 | 630 | struct ec_creg_mask_parms cr_parms; |
f3705136 | 631 | int cpu = smp_processor_id(); |
1da177e4 | 632 | |
f3705136 | 633 | cpu_clear(cpu, cpu_online_map); |
1da177e4 | 634 | |
1da177e4 | 635 | /* Disable pfault pseudo page faults on this cpu. */ |
29b08d2b | 636 | pfault_fini(); |
1da177e4 | 637 | |
94c12cc7 MS |
638 | memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals)); |
639 | memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals)); | |
1da177e4 | 640 | |
94c12cc7 | 641 | /* disable all external interrupts */ |
1da177e4 | 642 | cr_parms.orvals[0] = 0; |
39ce010d HC |
643 | cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 12 | |
644 | 1 << 11 | 1 << 10 | 1 << 6 | 1 << 4); | |
1da177e4 | 645 | /* disable all I/O interrupts */ |
1da177e4 | 646 | cr_parms.orvals[6] = 0; |
39ce010d HC |
647 | cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | |
648 | 1 << 27 | 1 << 26 | 1 << 25 | 1 << 24); | |
1da177e4 | 649 | /* disable most machine checks */ |
1da177e4 | 650 | cr_parms.orvals[14] = 0; |
39ce010d HC |
651 | cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 | |
652 | 1 << 25 | 1 << 24); | |
94c12cc7 | 653 | |
1da177e4 LT |
654 | smp_ctl_bit_callback(&cr_parms); |
655 | ||
1da177e4 LT |
656 | return 0; |
657 | } | |
658 | ||
39ce010d | 659 | void __cpu_die(unsigned int cpu) |
1da177e4 LT |
660 | { |
661 | /* Wait until target cpu is down */ | |
5c0b912e | 662 | while (!cpu_stopped(cpu)) |
1da177e4 | 663 | cpu_relax(); |
a93b8ec1 | 664 | while (sigp_p(0, cpu, sigp_set_prefix) == sigp_busy) |
4f8048ee | 665 | udelay(10); |
1cb6bb4b | 666 | smp_free_lowcore(cpu); |
050eef36 | 667 | atomic_dec(&init_mm.context.attach_count); |
395d31d4 | 668 | pr_info("Processor %d stopped\n", cpu); |
1da177e4 LT |
669 | } |
670 | ||
39ce010d | 671 | void cpu_die(void) |
1da177e4 LT |
672 | { |
673 | idle_task_exit(); | |
a93b8ec1 | 674 | while (sigp(smp_processor_id(), sigp_stop) == sigp_busy) |
f8501ba7 | 675 | cpu_relax(); |
39ce010d | 676 | for (;;); |
1da177e4 LT |
677 | } |
678 | ||
255acee7 HC |
679 | #endif /* CONFIG_HOTPLUG_CPU */ |
680 | ||
1da177e4 LT |
681 | void __init smp_prepare_cpus(unsigned int max_cpus) |
682 | { | |
591bb4f6 HC |
683 | #ifndef CONFIG_64BIT |
684 | unsigned long save_area = 0; | |
685 | #endif | |
686 | unsigned long async_stack, panic_stack; | |
687 | struct _lowcore *lowcore; | |
1da177e4 | 688 | unsigned int cpu; |
39ce010d | 689 | |
48483b32 HC |
690 | smp_detect_cpus(); |
691 | ||
39ce010d HC |
692 | /* request the 0x1201 emergency signal external interrupt */ |
693 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
694 | panic("Couldn't request external interrupt 0x1201"); | |
7b468488 | 695 | print_cpu_info(); |
1da177e4 | 696 | |
591bb4f6 | 697 | /* Reallocate current lowcore, but keep its contents. */ |
3fd26a77 | 698 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
591bb4f6 HC |
699 | panic_stack = __get_free_page(GFP_KERNEL); |
700 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
c742b31c | 701 | BUG_ON(!lowcore || !panic_stack || !async_stack); |
347a8dc3 | 702 | #ifndef CONFIG_64BIT |
77fa2245 | 703 | if (MACHINE_HAS_IEEE) |
591bb4f6 | 704 | save_area = get_zeroed_page(GFP_KERNEL); |
77fa2245 | 705 | #endif |
591bb4f6 HC |
706 | local_irq_disable(); |
707 | local_mcck_disable(); | |
708 | lowcore_ptr[smp_processor_id()] = lowcore; | |
709 | *lowcore = S390_lowcore; | |
710 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
711 | lowcore->async_stack = async_stack + ASYNC_SIZE; | |
712 | #ifndef CONFIG_64BIT | |
713 | if (MACHINE_HAS_IEEE) | |
714 | lowcore->extended_save_area_addr = (u32) save_area; | |
715 | #endif | |
716 | set_prefix((u32)(unsigned long) lowcore); | |
717 | local_mcck_enable(); | |
718 | local_irq_enable(); | |
3a6ba460 HC |
719 | #ifdef CONFIG_64BIT |
720 | if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore)) | |
721 | BUG(); | |
722 | #endif | |
97db7fbf | 723 | for_each_possible_cpu(cpu) |
1da177e4 LT |
724 | if (cpu != smp_processor_id()) |
725 | smp_create_idle(cpu); | |
726 | } | |
727 | ||
ea1f4eec | 728 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
729 | { |
730 | BUG_ON(smp_processor_id() != 0); | |
731 | ||
48483b32 HC |
732 | current_thread_info()->cpu = 0; |
733 | cpu_set(0, cpu_present_map); | |
1da177e4 | 734 | cpu_set(0, cpu_online_map); |
1da177e4 LT |
735 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
736 | current_set[0] = current; | |
08d07968 | 737 | smp_cpu_state[0] = CPU_STATE_CONFIGURED; |
c10fde0d | 738 | smp_cpu_polarization[0] = POLARIZATION_UNKNWN; |
1da177e4 LT |
739 | } |
740 | ||
ea1f4eec | 741 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 742 | { |
1da177e4 LT |
743 | } |
744 | ||
02beaccc HC |
745 | void __init smp_setup_processor_id(void) |
746 | { | |
747 | S390_lowcore.cpu_nr = 0; | |
748 | __cpu_logical_map[0] = stap(); | |
749 | } | |
750 | ||
1da177e4 LT |
751 | /* |
752 | * the frequency of the profiling timer can be changed | |
753 | * by writing a multiplier value into /proc/profile. | |
754 | * | |
755 | * usually you want to run this on all CPUs ;) | |
756 | */ | |
757 | int setup_profiling_timer(unsigned int multiplier) | |
758 | { | |
39ce010d | 759 | return 0; |
1da177e4 LT |
760 | } |
761 | ||
08d07968 | 762 | #ifdef CONFIG_HOTPLUG_CPU |
4a0b2b4d AK |
763 | static ssize_t cpu_configure_show(struct sys_device *dev, |
764 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
765 | { |
766 | ssize_t count; | |
767 | ||
768 | mutex_lock(&smp_cpu_state_mutex); | |
769 | count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]); | |
770 | mutex_unlock(&smp_cpu_state_mutex); | |
771 | return count; | |
772 | } | |
773 | ||
4a0b2b4d AK |
774 | static ssize_t cpu_configure_store(struct sys_device *dev, |
775 | struct sysdev_attribute *attr, | |
776 | const char *buf, size_t count) | |
08d07968 HC |
777 | { |
778 | int cpu = dev->id; | |
779 | int val, rc; | |
780 | char delim; | |
781 | ||
782 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
783 | return -EINVAL; | |
784 | if (val != 0 && val != 1) | |
785 | return -EINVAL; | |
786 | ||
9d40d2e3 | 787 | get_online_cpus(); |
0b18d318 | 788 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 789 | rc = -EBUSY; |
2c2df118 HC |
790 | /* disallow configuration changes of online cpus and cpu 0 */ |
791 | if (cpu_online(cpu) || cpu == 0) | |
08d07968 HC |
792 | goto out; |
793 | rc = 0; | |
794 | switch (val) { | |
795 | case 0: | |
796 | if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) { | |
797 | rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]); | |
c10fde0d | 798 | if (!rc) { |
08d07968 | 799 | smp_cpu_state[cpu] = CPU_STATE_STANDBY; |
c10fde0d HC |
800 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
801 | } | |
08d07968 HC |
802 | } |
803 | break; | |
804 | case 1: | |
805 | if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) { | |
806 | rc = sclp_cpu_configure(__cpu_logical_map[cpu]); | |
c10fde0d | 807 | if (!rc) { |
08d07968 | 808 | smp_cpu_state[cpu] = CPU_STATE_CONFIGURED; |
c10fde0d HC |
809 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
810 | } | |
08d07968 HC |
811 | } |
812 | break; | |
813 | default: | |
814 | break; | |
815 | } | |
816 | out: | |
08d07968 | 817 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 818 | put_online_cpus(); |
08d07968 HC |
819 | return rc ? rc : count; |
820 | } | |
821 | static SYSDEV_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); | |
822 | #endif /* CONFIG_HOTPLUG_CPU */ | |
823 | ||
4a0b2b4d AK |
824 | static ssize_t cpu_polarization_show(struct sys_device *dev, |
825 | struct sysdev_attribute *attr, char *buf) | |
c10fde0d HC |
826 | { |
827 | int cpu = dev->id; | |
828 | ssize_t count; | |
829 | ||
830 | mutex_lock(&smp_cpu_state_mutex); | |
831 | switch (smp_cpu_polarization[cpu]) { | |
832 | case POLARIZATION_HRZ: | |
833 | count = sprintf(buf, "horizontal\n"); | |
834 | break; | |
835 | case POLARIZATION_VL: | |
836 | count = sprintf(buf, "vertical:low\n"); | |
837 | break; | |
838 | case POLARIZATION_VM: | |
839 | count = sprintf(buf, "vertical:medium\n"); | |
840 | break; | |
841 | case POLARIZATION_VH: | |
842 | count = sprintf(buf, "vertical:high\n"); | |
843 | break; | |
844 | default: | |
845 | count = sprintf(buf, "unknown\n"); | |
846 | break; | |
847 | } | |
848 | mutex_unlock(&smp_cpu_state_mutex); | |
849 | return count; | |
850 | } | |
851 | static SYSDEV_ATTR(polarization, 0444, cpu_polarization_show, NULL); | |
852 | ||
4a0b2b4d AK |
853 | static ssize_t show_cpu_address(struct sys_device *dev, |
854 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
855 | { |
856 | return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]); | |
857 | } | |
858 | static SYSDEV_ATTR(address, 0444, show_cpu_address, NULL); | |
859 | ||
860 | ||
861 | static struct attribute *cpu_common_attrs[] = { | |
862 | #ifdef CONFIG_HOTPLUG_CPU | |
863 | &attr_configure.attr, | |
864 | #endif | |
865 | &attr_address.attr, | |
c10fde0d | 866 | &attr_polarization.attr, |
08d07968 HC |
867 | NULL, |
868 | }; | |
869 | ||
870 | static struct attribute_group cpu_common_attr_group = { | |
871 | .attrs = cpu_common_attrs, | |
872 | }; | |
1da177e4 | 873 | |
4a0b2b4d AK |
874 | static ssize_t show_capability(struct sys_device *dev, |
875 | struct sysdev_attribute *attr, char *buf) | |
2fc2d1e9 HC |
876 | { |
877 | unsigned int capability; | |
878 | int rc; | |
879 | ||
880 | rc = get_cpu_capability(&capability); | |
881 | if (rc) | |
882 | return rc; | |
883 | return sprintf(buf, "%u\n", capability); | |
884 | } | |
885 | static SYSDEV_ATTR(capability, 0444, show_capability, NULL); | |
886 | ||
4a0b2b4d AK |
887 | static ssize_t show_idle_count(struct sys_device *dev, |
888 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
889 | { |
890 | struct s390_idle_data *idle; | |
891 | unsigned long long idle_count; | |
e98bbaaf | 892 | unsigned int sequence; |
fae8b22d HC |
893 | |
894 | idle = &per_cpu(s390_idle, dev->id); | |
e98bbaaf MS |
895 | repeat: |
896 | sequence = idle->sequence; | |
897 | smp_rmb(); | |
898 | if (sequence & 1) | |
899 | goto repeat; | |
fae8b22d | 900 | idle_count = idle->idle_count; |
6f430924 MS |
901 | if (idle->idle_enter) |
902 | idle_count++; | |
e98bbaaf MS |
903 | smp_rmb(); |
904 | if (idle->sequence != sequence) | |
905 | goto repeat; | |
fae8b22d HC |
906 | return sprintf(buf, "%llu\n", idle_count); |
907 | } | |
908 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); | |
909 | ||
4a0b2b4d AK |
910 | static ssize_t show_idle_time(struct sys_device *dev, |
911 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
912 | { |
913 | struct s390_idle_data *idle; | |
6f430924 | 914 | unsigned long long now, idle_time, idle_enter; |
e98bbaaf | 915 | unsigned int sequence; |
fae8b22d HC |
916 | |
917 | idle = &per_cpu(s390_idle, dev->id); | |
6f430924 | 918 | now = get_clock(); |
e98bbaaf MS |
919 | repeat: |
920 | sequence = idle->sequence; | |
921 | smp_rmb(); | |
922 | if (sequence & 1) | |
923 | goto repeat; | |
6f430924 MS |
924 | idle_time = idle->idle_time; |
925 | idle_enter = idle->idle_enter; | |
926 | if (idle_enter != 0ULL && idle_enter < now) | |
927 | idle_time += now - idle_enter; | |
e98bbaaf MS |
928 | smp_rmb(); |
929 | if (idle->sequence != sequence) | |
930 | goto repeat; | |
6f430924 | 931 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 932 | } |
69d39d66 | 933 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 934 | |
08d07968 | 935 | static struct attribute *cpu_online_attrs[] = { |
fae8b22d HC |
936 | &attr_capability.attr, |
937 | &attr_idle_count.attr, | |
69d39d66 | 938 | &attr_idle_time_us.attr, |
fae8b22d HC |
939 | NULL, |
940 | }; | |
941 | ||
08d07968 HC |
942 | static struct attribute_group cpu_online_attr_group = { |
943 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
944 | }; |
945 | ||
2fc2d1e9 HC |
946 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
947 | unsigned long action, void *hcpu) | |
948 | { | |
949 | unsigned int cpu = (unsigned int)(long)hcpu; | |
950 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
951 | struct sys_device *s = &c->sysdev; | |
fae8b22d | 952 | struct s390_idle_data *idle; |
d882ba69 | 953 | int err = 0; |
2fc2d1e9 HC |
954 | |
955 | switch (action) { | |
956 | case CPU_ONLINE: | |
8bb78442 | 957 | case CPU_ONLINE_FROZEN: |
fae8b22d | 958 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 959 | memset(idle, 0, sizeof(struct s390_idle_data)); |
d882ba69 | 960 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
961 | break; |
962 | case CPU_DEAD: | |
8bb78442 | 963 | case CPU_DEAD_FROZEN: |
08d07968 | 964 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
965 | break; |
966 | } | |
d882ba69 | 967 | return notifier_from_errno(err); |
2fc2d1e9 HC |
968 | } |
969 | ||
970 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 971 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
972 | }; |
973 | ||
2bc89b5e | 974 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 HC |
975 | { |
976 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
977 | struct sys_device *s = &c->sysdev; | |
978 | int rc; | |
979 | ||
980 | c->hotpluggable = 1; | |
981 | rc = register_cpu(c, cpu); | |
982 | if (rc) | |
983 | goto out; | |
984 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
985 | if (rc) | |
986 | goto out_cpu; | |
987 | if (!cpu_online(cpu)) | |
988 | goto out; | |
989 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
990 | if (!rc) | |
991 | return 0; | |
992 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); | |
993 | out_cpu: | |
994 | #ifdef CONFIG_HOTPLUG_CPU | |
995 | unregister_cpu(c); | |
996 | #endif | |
997 | out: | |
998 | return rc; | |
999 | } | |
1000 | ||
1001 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1002 | |
67060d9c | 1003 | int __ref smp_rescan_cpus(void) |
08d07968 HC |
1004 | { |
1005 | cpumask_t newcpus; | |
1006 | int cpu; | |
1007 | int rc; | |
1008 | ||
9d40d2e3 | 1009 | get_online_cpus(); |
0b18d318 | 1010 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 1011 | newcpus = cpu_present_map; |
1e489518 | 1012 | rc = __smp_rescan_cpus(); |
08d07968 HC |
1013 | if (rc) |
1014 | goto out; | |
1015 | cpus_andnot(newcpus, cpu_present_map, newcpus); | |
1016 | for_each_cpu_mask(cpu, newcpus) { | |
1017 | rc = smp_add_present_cpu(cpu); | |
1018 | if (rc) | |
1019 | cpu_clear(cpu, cpu_present_map); | |
1020 | } | |
1021 | rc = 0; | |
1022 | out: | |
08d07968 | 1023 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1024 | put_online_cpus(); |
c10fde0d HC |
1025 | if (!cpus_empty(newcpus)) |
1026 | topology_schedule_update(); | |
1e489518 HC |
1027 | return rc; |
1028 | } | |
1029 | ||
c9be0a36 AK |
1030 | static ssize_t __ref rescan_store(struct sysdev_class *class, |
1031 | struct sysdev_class_attribute *attr, | |
1032 | const char *buf, | |
1e489518 HC |
1033 | size_t count) |
1034 | { | |
1035 | int rc; | |
1036 | ||
1037 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1038 | return rc ? rc : count; |
1039 | } | |
da5aae70 | 1040 | static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1041 | #endif /* CONFIG_HOTPLUG_CPU */ |
1042 | ||
5fbcae57 HC |
1043 | static ssize_t dispatching_show(struct sysdev_class *class, |
1044 | struct sysdev_class_attribute *attr, | |
1045 | char *buf) | |
c10fde0d HC |
1046 | { |
1047 | ssize_t count; | |
1048 | ||
1049 | mutex_lock(&smp_cpu_state_mutex); | |
1050 | count = sprintf(buf, "%d\n", cpu_management); | |
1051 | mutex_unlock(&smp_cpu_state_mutex); | |
1052 | return count; | |
1053 | } | |
1054 | ||
c9be0a36 AK |
1055 | static ssize_t dispatching_store(struct sysdev_class *dev, |
1056 | struct sysdev_class_attribute *attr, | |
1057 | const char *buf, | |
da5aae70 | 1058 | size_t count) |
c10fde0d HC |
1059 | { |
1060 | int val, rc; | |
1061 | char delim; | |
1062 | ||
1063 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
1064 | return -EINVAL; | |
1065 | if (val != 0 && val != 1) | |
1066 | return -EINVAL; | |
1067 | rc = 0; | |
c10fde0d | 1068 | get_online_cpus(); |
0b18d318 | 1069 | mutex_lock(&smp_cpu_state_mutex); |
c10fde0d HC |
1070 | if (cpu_management == val) |
1071 | goto out; | |
1072 | rc = topology_set_cpu_management(val); | |
1073 | if (!rc) | |
1074 | cpu_management = val; | |
1075 | out: | |
c10fde0d | 1076 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1077 | put_online_cpus(); |
c10fde0d HC |
1078 | return rc ? rc : count; |
1079 | } | |
da5aae70 HC |
1080 | static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show, |
1081 | dispatching_store); | |
c10fde0d | 1082 | |
1da177e4 LT |
1083 | static int __init topology_init(void) |
1084 | { | |
1085 | int cpu; | |
fae8b22d | 1086 | int rc; |
2fc2d1e9 HC |
1087 | |
1088 | register_cpu_notifier(&smp_cpu_nb); | |
1da177e4 | 1089 | |
08d07968 | 1090 | #ifdef CONFIG_HOTPLUG_CPU |
da5aae70 | 1091 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan); |
08d07968 HC |
1092 | if (rc) |
1093 | return rc; | |
1094 | #endif | |
da5aae70 | 1095 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching); |
c10fde0d HC |
1096 | if (rc) |
1097 | return rc; | |
08d07968 HC |
1098 | for_each_present_cpu(cpu) { |
1099 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1100 | if (rc) |
1101 | return rc; | |
1da177e4 LT |
1102 | } |
1103 | return 0; | |
1104 | } | |
1da177e4 | 1105 | subsys_initcall(topology_init); |