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Commit | Line | Data |
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1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
27f6b416 | 41 | #include <asm/vtimer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
b5f87f15 | 48 | #include <asm/idle.h> |
a806170e | 49 | #include "entry.h" |
1da177e4 | 50 | |
8b646bd7 MS |
51 | enum { |
52 | ec_schedule = 0, | |
8b646bd7 MS |
53 | ec_call_function_single, |
54 | ec_stop_cpu, | |
55 | }; | |
08d07968 | 56 | |
8b646bd7 | 57 | enum { |
08d07968 HC |
58 | CPU_STATE_STANDBY, |
59 | CPU_STATE_CONFIGURED, | |
60 | }; | |
61 | ||
8b646bd7 | 62 | struct pcpu { |
96619fc1 | 63 | struct cpu *cpu; |
8b646bd7 MS |
64 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
65 | unsigned long async_stack; /* async stack for the cpu */ | |
66 | unsigned long panic_stack; /* panic stack for the cpu */ | |
67 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
68 | int state; /* physical cpu state */ | |
50ab9a9a | 69 | int polarization; /* physical polarization */ |
8b646bd7 MS |
70 | u16 address; /* physical cpu address */ |
71 | }; | |
72 | ||
73 | static u8 boot_cpu_type; | |
74 | static u16 boot_cpu_address; | |
75 | static struct pcpu pcpu_devices[NR_CPUS]; | |
76 | ||
50ab9a9a HC |
77 | /* |
78 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
79 | * member of a pcpu data structure within the pcpu_devices arreay. | |
80 | */ | |
dbd70fb4 | 81 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 82 | |
8b646bd7 MS |
83 | /* |
84 | * Signal processor helper functions. | |
85 | */ | |
a62bc073 MH |
86 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm, |
87 | u32 *status) | |
5c0b912e | 88 | { |
8b646bd7 | 89 | int cc; |
5c0b912e | 90 | |
8b646bd7 | 91 | while (1) { |
c5e3acd6 | 92 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 93 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
94 | return cc; |
95 | cpu_relax(); | |
5c0b912e | 96 | } |
5c0b912e HC |
97 | } |
98 | ||
8b646bd7 | 99 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 100 | { |
8b646bd7 MS |
101 | int cc, retry; |
102 | ||
103 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 104 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 105 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
106 | break; |
107 | if (retry >= 3) | |
108 | udelay(10); | |
109 | } | |
110 | return cc; | |
111 | } | |
112 | ||
113 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
114 | { | |
41459d36 | 115 | u32 uninitialized_var(status); |
c5e3acd6 | 116 | |
a9ae32c3 | 117 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 118 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 119 | return 0; |
c5e3acd6 | 120 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
121 | } |
122 | ||
123 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 124 | { |
a9ae32c3 | 125 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 126 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 127 | return 1; |
524b24ad HC |
128 | /* Status stored condition code is equivalent to cpu not running. */ |
129 | return 0; | |
a93b8ec1 HC |
130 | } |
131 | ||
1943f53c | 132 | /* |
8b646bd7 | 133 | * Find struct pcpu by cpu address. |
1943f53c | 134 | */ |
8b646bd7 | 135 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
136 | { |
137 | int cpu; | |
138 | ||
8b646bd7 MS |
139 | for_each_cpu(cpu, mask) |
140 | if (pcpu_devices[cpu].address == address) | |
141 | return pcpu_devices + cpu; | |
142 | return NULL; | |
143 | } | |
144 | ||
145 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
146 | { | |
147 | int order; | |
148 | ||
dea24190 HC |
149 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
150 | return; | |
151 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
8b646bd7 MS |
152 | pcpu_sigp_retry(pcpu, order, 0); |
153 | } | |
154 | ||
e2741f17 | 155 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 MS |
156 | { |
157 | struct _lowcore *lc; | |
158 | ||
159 | if (pcpu != &pcpu_devices[0]) { | |
160 | pcpu->lowcore = (struct _lowcore *) | |
161 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
162 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
163 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
164 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
165 | goto out; | |
1943f53c | 166 | } |
8b646bd7 MS |
167 | lc = pcpu->lowcore; |
168 | memcpy(lc, &S390_lowcore, 512); | |
169 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
dc7ee00d MS |
170 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE |
171 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
172 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE | |
173 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 | 174 | lc->cpu_nr = cpu; |
6c8cd5bb | 175 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
8b646bd7 MS |
176 | #ifndef CONFIG_64BIT |
177 | if (MACHINE_HAS_IEEE) { | |
178 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
179 | if (!lc->extended_save_area_addr) | |
180 | goto out; | |
181 | } | |
182 | #else | |
80703617 MS |
183 | if (MACHINE_HAS_VX) |
184 | lc->vector_save_area_addr = | |
185 | (unsigned long) &lc->vector_save_area; | |
8b646bd7 MS |
186 | if (vdso_alloc_per_cpu(lc)) |
187 | goto out; | |
188 | #endif | |
189 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 190 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
191 | return 0; |
192 | out: | |
193 | if (pcpu != &pcpu_devices[0]) { | |
194 | free_page(pcpu->panic_stack); | |
195 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
196 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
197 | } | |
198 | return -ENOMEM; | |
1943f53c MH |
199 | } |
200 | ||
9d0f46af HC |
201 | #ifdef CONFIG_HOTPLUG_CPU |
202 | ||
8b646bd7 | 203 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 204 | { |
a9ae32c3 | 205 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
206 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
207 | #ifndef CONFIG_64BIT | |
208 | if (MACHINE_HAS_IEEE) { | |
209 | struct _lowcore *lc = pcpu->lowcore; | |
210 | ||
211 | free_page((unsigned long) lc->extended_save_area_addr); | |
212 | lc->extended_save_area_addr = 0; | |
213 | } | |
214 | #else | |
215 | vdso_free_per_cpu(pcpu->lowcore); | |
216 | #endif | |
217 | if (pcpu != &pcpu_devices[0]) { | |
218 | free_page(pcpu->panic_stack); | |
219 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
220 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
221 | } | |
222 | } | |
223 | ||
9d0f46af HC |
224 | #endif /* CONFIG_HOTPLUG_CPU */ |
225 | ||
8b646bd7 MS |
226 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
227 | { | |
228 | struct _lowcore *lc = pcpu->lowcore; | |
229 | ||
1b948d6c MS |
230 | if (MACHINE_HAS_TLB_LC) |
231 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
232 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); | |
8b646bd7 MS |
233 | atomic_inc(&init_mm.context.attach_count); |
234 | lc->cpu_nr = cpu; | |
6c8cd5bb | 235 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
8b646bd7 MS |
236 | lc->percpu_offset = __per_cpu_offset[cpu]; |
237 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
238 | lc->machine_flags = S390_lowcore.machine_flags; | |
8b646bd7 MS |
239 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; |
240 | __ctl_store(lc->cregs_save_area, 0, 15); | |
241 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
242 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
243 | MAX_FACILITY_BIT/8); | |
244 | } | |
245 | ||
246 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
247 | { | |
248 | struct _lowcore *lc = pcpu->lowcore; | |
249 | struct thread_info *ti = task_thread_info(tsk); | |
250 | ||
dc7ee00d MS |
251 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
252 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
253 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
254 | lc->current_task = (unsigned long) tsk; | |
255 | lc->user_timer = ti->user_timer; | |
256 | lc->system_timer = ti->system_timer; | |
257 | lc->steal_timer = 0; | |
258 | } | |
259 | ||
260 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
261 | { | |
262 | struct _lowcore *lc = pcpu->lowcore; | |
263 | ||
264 | lc->restart_stack = lc->kernel_stack; | |
265 | lc->restart_fn = (unsigned long) func; | |
266 | lc->restart_data = (unsigned long) data; | |
267 | lc->restart_source = -1UL; | |
a9ae32c3 | 268 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
269 | } |
270 | ||
271 | /* | |
272 | * Call function via PSW restart on pcpu and stop the current cpu. | |
273 | */ | |
274 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
275 | void *data, unsigned long stack) | |
276 | { | |
061da3df | 277 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 278 | unsigned long source_cpu = stap(); |
8b646bd7 | 279 | |
e258d719 | 280 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 281 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
282 | func(data); /* should not return */ |
283 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 284 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 285 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
286 | mem_assign_absolute(lc->restart_stack, stack); |
287 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
288 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
289 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 290 | asm volatile( |
eb546195 | 291 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 292 | " brc 2,0b # busy, try again\n" |
eb546195 | 293 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 294 | " brc 2,1b # busy, try again\n" |
fbe76568 | 295 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
296 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
297 | : "0", "1", "cc"); | |
8b646bd7 MS |
298 | for (;;) ; |
299 | } | |
300 | ||
301 | /* | |
302 | * Call function on an online CPU. | |
303 | */ | |
304 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
305 | { | |
306 | struct pcpu *pcpu; | |
307 | ||
308 | /* Use the current cpu if it is online. */ | |
309 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
310 | if (!pcpu) | |
311 | /* Use the first online cpu. */ | |
312 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
313 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
314 | } | |
315 | ||
316 | /* | |
317 | * Call function on the ipl CPU. | |
318 | */ | |
319 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
320 | { | |
c6da39f2 MH |
321 | pcpu_delegate(&pcpu_devices[0], func, data, |
322 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
323 | } |
324 | ||
325 | int smp_find_processor_id(u16 address) | |
326 | { | |
327 | int cpu; | |
328 | ||
329 | for_each_present_cpu(cpu) | |
330 | if (pcpu_devices[cpu].address == address) | |
331 | return cpu; | |
332 | return -1; | |
2c2df118 HC |
333 | } |
334 | ||
8b646bd7 | 335 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 336 | { |
8b646bd7 MS |
337 | return pcpu_running(pcpu_devices + cpu); |
338 | } | |
339 | ||
8b646bd7 | 340 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 341 | { |
8b646bd7 MS |
342 | if (MACHINE_HAS_DIAG9C) |
343 | asm volatile("diag %0,0,0x9c" | |
344 | : : "d" (pcpu_devices[cpu].address)); | |
345 | else if (MACHINE_HAS_DIAG44) | |
346 | asm volatile("diag 0,0,0x44"); | |
347 | } | |
348 | ||
349 | /* | |
350 | * Send cpus emergency shutdown signal. This gives the cpus the | |
351 | * opportunity to complete outstanding interrupts. | |
352 | */ | |
63df41d6 | 353 | static void smp_emergency_stop(cpumask_t *cpumask) |
8b646bd7 MS |
354 | { |
355 | u64 end; | |
356 | int cpu; | |
357 | ||
1aae0560 | 358 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
359 | for_each_cpu(cpu, cpumask) { |
360 | struct pcpu *pcpu = pcpu_devices + cpu; | |
361 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
362 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
363 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 364 | get_tod_clock() < end) |
8b646bd7 MS |
365 | cpu_relax(); |
366 | } | |
1aae0560 | 367 | while (get_tod_clock() < end) { |
8b646bd7 MS |
368 | for_each_cpu(cpu, cpumask) |
369 | if (pcpu_stopped(pcpu_devices + cpu)) | |
370 | cpumask_clear_cpu(cpu, cpumask); | |
371 | if (cpumask_empty(cpumask)) | |
372 | break; | |
85ac7ca5 | 373 | cpu_relax(); |
8b646bd7 | 374 | } |
85ac7ca5 MS |
375 | } |
376 | ||
8b646bd7 MS |
377 | /* |
378 | * Stop all cpus but the current one. | |
379 | */ | |
677d7623 | 380 | void smp_send_stop(void) |
1da177e4 | 381 | { |
85ac7ca5 MS |
382 | cpumask_t cpumask; |
383 | int cpu; | |
1da177e4 | 384 | |
677d7623 | 385 | /* Disable all interrupts/machine checks */ |
e258d719 | 386 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 387 | trace_hardirqs_off(); |
1da177e4 | 388 | |
3ab121ab | 389 | debug_set_critical(); |
85ac7ca5 MS |
390 | cpumask_copy(&cpumask, cpu_online_mask); |
391 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
392 | ||
8b646bd7 MS |
393 | if (oops_in_progress) |
394 | smp_emergency_stop(&cpumask); | |
1da177e4 | 395 | |
85ac7ca5 MS |
396 | /* stop all processors */ |
397 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 398 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 399 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 400 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
401 | cpu_relax(); |
402 | } | |
403 | } | |
404 | ||
1da177e4 LT |
405 | /* |
406 | * This is the main routine where commands issued by other | |
407 | * cpus are handled. | |
408 | */ | |
9acf73b7 | 409 | static void smp_handle_ext_call(void) |
1da177e4 | 410 | { |
39ce010d | 411 | unsigned long bits; |
1da177e4 | 412 | |
9acf73b7 HC |
413 | /* handle bit signal external calls */ |
414 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
415 | if (test_bit(ec_stop_cpu, &bits)) |
416 | smp_stop_cpu(); | |
184748cc PZ |
417 | if (test_bit(ec_schedule, &bits)) |
418 | scheduler_ipi(); | |
ca9fc75a HC |
419 | if (test_bit(ec_call_function_single, &bits)) |
420 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 421 | } |
85ac7ca5 | 422 | |
9acf73b7 HC |
423 | static void do_ext_call_interrupt(struct ext_code ext_code, |
424 | unsigned int param32, unsigned long param64) | |
425 | { | |
426 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
427 | smp_handle_ext_call(); | |
1da177e4 LT |
428 | } |
429 | ||
630cd046 | 430 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
431 | { |
432 | int cpu; | |
433 | ||
630cd046 | 434 | for_each_cpu(cpu, mask) |
b6ed49e0 | 435 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
436 | } |
437 | ||
438 | void arch_send_call_function_single_ipi(int cpu) | |
439 | { | |
8b646bd7 | 440 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
441 | } |
442 | ||
347a8dc3 | 443 | #ifndef CONFIG_64BIT |
1da177e4 LT |
444 | /* |
445 | * this function sends a 'purge tlb' signal to another CPU. | |
446 | */ | |
a806170e | 447 | static void smp_ptlb_callback(void *info) |
1da177e4 | 448 | { |
ba8a9229 | 449 | __tlb_flush_local(); |
1da177e4 LT |
450 | } |
451 | ||
452 | void smp_ptlb_all(void) | |
453 | { | |
15c8b6c1 | 454 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
455 | } |
456 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 457 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
458 | |
459 | /* | |
460 | * this function sends a 'reschedule' IPI to another CPU. | |
461 | * it goes straight through and wastes no time serializing | |
462 | * anything. Worst case is that we lose a reschedule ... | |
463 | */ | |
464 | void smp_send_reschedule(int cpu) | |
465 | { | |
8b646bd7 | 466 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
467 | } |
468 | ||
469 | /* | |
470 | * parameter area for the set/clear control bit callbacks | |
471 | */ | |
94c12cc7 | 472 | struct ec_creg_mask_parms { |
8b646bd7 MS |
473 | unsigned long orval; |
474 | unsigned long andval; | |
475 | int cr; | |
94c12cc7 | 476 | }; |
1da177e4 LT |
477 | |
478 | /* | |
479 | * callback for setting/clearing control bits | |
480 | */ | |
39ce010d HC |
481 | static void smp_ctl_bit_callback(void *info) |
482 | { | |
94c12cc7 | 483 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 484 | unsigned long cregs[16]; |
39ce010d | 485 | |
94c12cc7 | 486 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 487 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 488 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
489 | } |
490 | ||
491 | /* | |
492 | * Set a bit in a control register of all cpus | |
493 | */ | |
94c12cc7 MS |
494 | void smp_ctl_set_bit(int cr, int bit) |
495 | { | |
8b646bd7 | 496 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 497 | |
15c8b6c1 | 498 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 499 | } |
39ce010d | 500 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
501 | |
502 | /* | |
503 | * Clear a bit in a control register of all cpus | |
504 | */ | |
94c12cc7 MS |
505 | void smp_ctl_clear_bit(int cr, int bit) |
506 | { | |
8b646bd7 | 507 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 508 | |
15c8b6c1 | 509 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 510 | } |
39ce010d | 511 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 512 | |
bf28a597 | 513 | #ifdef CONFIG_CRASH_DUMP |
411ed322 | 514 | |
8b646bd7 | 515 | static void __init smp_get_save_area(int cpu, u16 address) |
411ed322 | 516 | { |
8b646bd7 | 517 | void *lc = pcpu_devices[0].lowcore; |
a62bc073 MH |
518 | struct save_area_ext *sa_ext; |
519 | unsigned long vx_sa; | |
8b646bd7 | 520 | |
60a0c68d | 521 | if (is_kdump_kernel()) |
411ed322 | 522 | return; |
8b646bd7 MS |
523 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
524 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
525 | return; | |
a62bc073 MH |
526 | sa_ext = dump_save_area_create(cpu); |
527 | if (!sa_ext) | |
8b646bd7 | 528 | panic("could not allocate memory for save area\n"); |
8b646bd7 MS |
529 | if (address == boot_cpu_address) { |
530 | /* Copy the registers of the boot cpu. */ | |
a62bc073 | 531 | copy_oldmem_page(1, (void *) &sa_ext->sa, sizeof(sa_ext->sa), |
8b646bd7 | 532 | SAVE_AREA_BASE - PAGE_SIZE, 0); |
a62bc073 MH |
533 | if (MACHINE_HAS_VX) |
534 | save_vx_regs_safe(sa_ext->vx_regs); | |
8b646bd7 MS |
535 | return; |
536 | } | |
8b646bd7 | 537 | /* Get the registers of a non-boot cpu. */ |
a9ae32c3 | 538 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
a62bc073 MH |
539 | memcpy_real(&sa_ext->sa, lc + SAVE_AREA_BASE, sizeof(sa_ext->sa)); |
540 | if (!MACHINE_HAS_VX) | |
541 | return; | |
542 | /* Get the VX registers */ | |
543 | vx_sa = __get_free_page(GFP_KERNEL); | |
544 | if (!vx_sa) | |
545 | panic("could not allocate memory for VX save area\n"); | |
546 | __pcpu_sigp_relax(address, SIGP_STORE_ADDITIONAL_STATUS, vx_sa, NULL); | |
547 | memcpy(sa_ext->vx_regs, (void *) vx_sa, sizeof(sa_ext->vx_regs)); | |
548 | free_page(vx_sa); | |
411ed322 MH |
549 | } |
550 | ||
8b646bd7 | 551 | int smp_store_status(int cpu) |
08d07968 | 552 | { |
a62bc073 | 553 | unsigned long vx_sa; |
8b646bd7 | 554 | struct pcpu *pcpu; |
08d07968 | 555 | |
8b646bd7 | 556 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
557 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
558 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 559 | return -EIO; |
a62bc073 MH |
560 | if (!MACHINE_HAS_VX) |
561 | return 0; | |
562 | vx_sa = __pa(pcpu->lowcore->vector_save_area_addr); | |
563 | __pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, | |
564 | vx_sa, NULL); | |
08d07968 HC |
565 | return 0; |
566 | } | |
567 | ||
bf28a597 | 568 | #else /* CONFIG_CRASH_DUMP */ |
08d07968 | 569 | |
8b646bd7 | 570 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 571 | |
bf28a597 | 572 | #endif /* CONFIG_CRASH_DUMP */ |
08d07968 | 573 | |
50ab9a9a HC |
574 | void smp_cpu_set_polarization(int cpu, int val) |
575 | { | |
576 | pcpu_devices[cpu].polarization = val; | |
577 | } | |
578 | ||
579 | int smp_cpu_get_polarization(int cpu) | |
580 | { | |
581 | return pcpu_devices[cpu].polarization; | |
582 | } | |
583 | ||
8b646bd7 | 584 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 585 | { |
8b646bd7 | 586 | static int use_sigp_detection; |
08d07968 | 587 | struct sclp_cpu_info *info; |
8b646bd7 MS |
588 | int address; |
589 | ||
590 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
591 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
592 | use_sigp_detection = 1; | |
593 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
594 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
595 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
596 | continue; |
597 | info->cpu[info->configured].address = address; | |
598 | info->configured++; | |
599 | } | |
600 | info->combined = info->configured; | |
08d07968 | 601 | } |
8b646bd7 | 602 | return info; |
08d07968 HC |
603 | } |
604 | ||
e2741f17 | 605 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 606 | |
e2741f17 | 607 | static int __smp_rescan_cpus(struct sclp_cpu_info *info, int sysfs_add) |
08d07968 | 608 | { |
8b646bd7 | 609 | struct pcpu *pcpu; |
08d07968 | 610 | cpumask_t avail; |
8b646bd7 | 611 | int cpu, nr, i; |
08d07968 | 612 | |
8b646bd7 | 613 | nr = 0; |
0f1959f5 | 614 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
615 | cpu = cpumask_first(&avail); |
616 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
617 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
618 | continue; | |
619 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
620 | continue; | |
621 | pcpu = pcpu_devices + cpu; | |
622 | pcpu->address = info->cpu[i].address; | |
a4eeea4e | 623 | pcpu->state = (i >= info->configured) ? |
8b646bd7 | 624 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; |
50ab9a9a | 625 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
626 | set_cpu_present(cpu, true); |
627 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
628 | set_cpu_present(cpu, false); | |
629 | else | |
630 | nr++; | |
631 | cpu = cpumask_next(cpu, &avail); | |
632 | } | |
633 | return nr; | |
1da177e4 LT |
634 | } |
635 | ||
48483b32 HC |
636 | static void __init smp_detect_cpus(void) |
637 | { | |
638 | unsigned int cpu, c_cpus, s_cpus; | |
639 | struct sclp_cpu_info *info; | |
48483b32 | 640 | |
8b646bd7 | 641 | info = smp_get_cpu_info(); |
48483b32 HC |
642 | if (!info) |
643 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
644 | if (info->has_cpu_type) { |
645 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
646 | if (info->cpu[cpu].address != boot_cpu_address) |
647 | continue; | |
648 | /* The boot cpu dictates the cpu type. */ | |
649 | boot_cpu_type = info->cpu[cpu].type; | |
650 | break; | |
48483b32 HC |
651 | } |
652 | } | |
8b646bd7 | 653 | c_cpus = s_cpus = 0; |
48483b32 | 654 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 655 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 656 | continue; |
8b646bd7 MS |
657 | if (cpu < info->configured) { |
658 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
659 | c_cpus++; | |
660 | } else | |
48483b32 | 661 | s_cpus++; |
48483b32 | 662 | } |
395d31d4 | 663 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 664 | get_online_cpus(); |
8b646bd7 | 665 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 666 | put_online_cpus(); |
8b646bd7 | 667 | kfree(info); |
48483b32 HC |
668 | } |
669 | ||
1da177e4 | 670 | /* |
39ce010d | 671 | * Activate a secondary processor. |
1da177e4 | 672 | */ |
e2741f17 | 673 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 674 | { |
1aae0560 | 675 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
676 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
677 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
678 | S390_lowcore.restart_data = 0; | |
679 | S390_lowcore.restart_source = -1UL; | |
680 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
681 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 682 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 683 | cpu_init(); |
5bfb5d69 | 684 | preempt_disable(); |
39ce010d | 685 | init_cpu_timer(); |
b5f87f15 | 686 | vtime_init(); |
29b08d2b | 687 | pfault_init(); |
e545a614 | 688 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 689 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 690 | inc_irq_stat(CPU_RST); |
1da177e4 | 691 | local_irq_enable(); |
52c00659 | 692 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
693 | } |
694 | ||
1da177e4 | 695 | /* Upping and downing of CPUs */ |
e2741f17 | 696 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 697 | { |
8b646bd7 MS |
698 | struct pcpu *pcpu; |
699 | int rc; | |
1da177e4 | 700 | |
8b646bd7 MS |
701 | pcpu = pcpu_devices + cpu; |
702 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 703 | return -EIO; |
a9ae32c3 HC |
704 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
705 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 706 | return -EIO; |
e80e7813 | 707 | |
8b646bd7 MS |
708 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
709 | if (rc) | |
710 | return rc; | |
711 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 712 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 713 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
714 | while (!cpu_online(cpu)) |
715 | cpu_relax(); | |
716 | return 0; | |
717 | } | |
718 | ||
d80512f8 | 719 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 720 | |
d80512f8 HC |
721 | static int __init _setup_possible_cpus(char *s) |
722 | { | |
723 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
724 | return 0; |
725 | } | |
d80512f8 | 726 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 727 | |
48483b32 HC |
728 | #ifdef CONFIG_HOTPLUG_CPU |
729 | ||
39ce010d | 730 | int __cpu_disable(void) |
1da177e4 | 731 | { |
8b646bd7 | 732 | unsigned long cregs[16]; |
1da177e4 | 733 | |
9acf73b7 HC |
734 | /* Handle possible pending IPIs */ |
735 | smp_handle_ext_call(); | |
8b646bd7 MS |
736 | set_cpu_online(smp_processor_id(), false); |
737 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 738 | pfault_fini(); |
8b646bd7 MS |
739 | /* Disable interrupt sources via control register. */ |
740 | __ctl_store(cregs, 0, 15); | |
741 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
742 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
743 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
744 | __ctl_load(cregs, 0, 15); | |
fe0f4976 | 745 | clear_cpu_flag(CIF_NOHZ_DELAY); |
1da177e4 LT |
746 | return 0; |
747 | } | |
748 | ||
39ce010d | 749 | void __cpu_die(unsigned int cpu) |
1da177e4 | 750 | { |
8b646bd7 MS |
751 | struct pcpu *pcpu; |
752 | ||
1da177e4 | 753 | /* Wait until target cpu is down */ |
8b646bd7 MS |
754 | pcpu = pcpu_devices + cpu; |
755 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 756 | cpu_relax(); |
8b646bd7 | 757 | pcpu_free_lowcore(pcpu); |
050eef36 | 758 | atomic_dec(&init_mm.context.attach_count); |
1b948d6c MS |
759 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
760 | if (MACHINE_HAS_TLB_LC) | |
761 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
1da177e4 LT |
762 | } |
763 | ||
b456d94a | 764 | void __noreturn cpu_die(void) |
1da177e4 LT |
765 | { |
766 | idle_task_exit(); | |
a9ae32c3 | 767 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 768 | for (;;) ; |
1da177e4 LT |
769 | } |
770 | ||
255acee7 HC |
771 | #endif /* CONFIG_HOTPLUG_CPU */ |
772 | ||
d80512f8 HC |
773 | void __init smp_fill_possible_mask(void) |
774 | { | |
cf813db0 | 775 | unsigned int possible, sclp, cpu; |
d80512f8 | 776 | |
cf813db0 HC |
777 | sclp = sclp_get_max_cpu() ?: nr_cpu_ids; |
778 | possible = setup_possible_cpus ?: nr_cpu_ids; | |
779 | possible = min(possible, sclp); | |
d80512f8 HC |
780 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
781 | set_cpu_possible(cpu, true); | |
782 | } | |
783 | ||
1da177e4 LT |
784 | void __init smp_prepare_cpus(unsigned int max_cpus) |
785 | { | |
39ce010d | 786 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 787 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 788 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 789 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 790 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 791 | panic("Couldn't request external interrupt 0x1202"); |
8b646bd7 | 792 | smp_detect_cpus(); |
1da177e4 LT |
793 | } |
794 | ||
ea1f4eec | 795 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 796 | { |
8b646bd7 MS |
797 | struct pcpu *pcpu = pcpu_devices; |
798 | ||
799 | boot_cpu_address = stap(); | |
8b646bd7 MS |
800 | pcpu->state = CPU_STATE_CONFIGURED; |
801 | pcpu->address = boot_cpu_address; | |
802 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
dc7ee00d MS |
803 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE |
804 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
805 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE | |
806 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
1da177e4 | 807 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 808 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
809 | set_cpu_present(0, true); |
810 | set_cpu_online(0, true); | |
1da177e4 LT |
811 | } |
812 | ||
ea1f4eec | 813 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 814 | { |
1da177e4 LT |
815 | } |
816 | ||
02beaccc HC |
817 | void __init smp_setup_processor_id(void) |
818 | { | |
819 | S390_lowcore.cpu_nr = 0; | |
6c8cd5bb | 820 | S390_lowcore.spinlock_lockval = arch_spin_lockval(0); |
02beaccc HC |
821 | } |
822 | ||
1da177e4 LT |
823 | /* |
824 | * the frequency of the profiling timer can be changed | |
825 | * by writing a multiplier value into /proc/profile. | |
826 | * | |
827 | * usually you want to run this on all CPUs ;) | |
828 | */ | |
829 | int setup_profiling_timer(unsigned int multiplier) | |
830 | { | |
39ce010d | 831 | return 0; |
1da177e4 LT |
832 | } |
833 | ||
08d07968 | 834 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 835 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 836 | struct device_attribute *attr, char *buf) |
08d07968 HC |
837 | { |
838 | ssize_t count; | |
839 | ||
840 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 841 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
842 | mutex_unlock(&smp_cpu_state_mutex); |
843 | return count; | |
844 | } | |
845 | ||
8a25a2fd | 846 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
847 | struct device_attribute *attr, |
848 | const char *buf, size_t count) | |
08d07968 | 849 | { |
8b646bd7 MS |
850 | struct pcpu *pcpu; |
851 | int cpu, val, rc; | |
08d07968 HC |
852 | char delim; |
853 | ||
854 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
855 | return -EINVAL; | |
856 | if (val != 0 && val != 1) | |
857 | return -EINVAL; | |
9d40d2e3 | 858 | get_online_cpus(); |
0b18d318 | 859 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 860 | rc = -EBUSY; |
2c2df118 | 861 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 862 | cpu = dev->id; |
2c2df118 | 863 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 864 | goto out; |
8b646bd7 | 865 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
866 | rc = 0; |
867 | switch (val) { | |
868 | case 0: | |
8b646bd7 MS |
869 | if (pcpu->state != CPU_STATE_CONFIGURED) |
870 | break; | |
871 | rc = sclp_cpu_deconfigure(pcpu->address); | |
872 | if (rc) | |
873 | break; | |
874 | pcpu->state = CPU_STATE_STANDBY; | |
50ab9a9a | 875 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 876 | topology_expect_change(); |
08d07968 HC |
877 | break; |
878 | case 1: | |
8b646bd7 MS |
879 | if (pcpu->state != CPU_STATE_STANDBY) |
880 | break; | |
881 | rc = sclp_cpu_configure(pcpu->address); | |
882 | if (rc) | |
883 | break; | |
884 | pcpu->state = CPU_STATE_CONFIGURED; | |
50ab9a9a | 885 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 886 | topology_expect_change(); |
08d07968 HC |
887 | break; |
888 | default: | |
889 | break; | |
890 | } | |
891 | out: | |
08d07968 | 892 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 893 | put_online_cpus(); |
08d07968 HC |
894 | return rc ? rc : count; |
895 | } | |
8a25a2fd | 896 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
897 | #endif /* CONFIG_HOTPLUG_CPU */ |
898 | ||
8a25a2fd KS |
899 | static ssize_t show_cpu_address(struct device *dev, |
900 | struct device_attribute *attr, char *buf) | |
08d07968 | 901 | { |
8b646bd7 | 902 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 903 | } |
8a25a2fd | 904 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 905 | |
08d07968 HC |
906 | static struct attribute *cpu_common_attrs[] = { |
907 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 908 | &dev_attr_configure.attr, |
08d07968 | 909 | #endif |
8a25a2fd | 910 | &dev_attr_address.attr, |
08d07968 HC |
911 | NULL, |
912 | }; | |
913 | ||
914 | static struct attribute_group cpu_common_attr_group = { | |
915 | .attrs = cpu_common_attrs, | |
916 | }; | |
1da177e4 | 917 | |
08d07968 | 918 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
919 | &dev_attr_idle_count.attr, |
920 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
921 | NULL, |
922 | }; | |
923 | ||
08d07968 HC |
924 | static struct attribute_group cpu_online_attr_group = { |
925 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
926 | }; |
927 | ||
e2741f17 PG |
928 | static int smp_cpu_notify(struct notifier_block *self, unsigned long action, |
929 | void *hcpu) | |
2fc2d1e9 HC |
930 | { |
931 | unsigned int cpu = (unsigned int)(long)hcpu; | |
96619fc1 | 932 | struct cpu *c = pcpu_devices[cpu].cpu; |
8a25a2fd | 933 | struct device *s = &c->dev; |
d882ba69 | 934 | int err = 0; |
2fc2d1e9 | 935 | |
1c725922 | 936 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 937 | case CPU_ONLINE: |
d882ba69 | 938 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
939 | break; |
940 | case CPU_DEAD: | |
08d07968 | 941 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
942 | break; |
943 | } | |
d882ba69 | 944 | return notifier_from_errno(err); |
2fc2d1e9 HC |
945 | } |
946 | ||
e2741f17 | 947 | static int smp_add_present_cpu(int cpu) |
08d07968 | 948 | { |
96619fc1 HC |
949 | struct device *s; |
950 | struct cpu *c; | |
08d07968 HC |
951 | int rc; |
952 | ||
96619fc1 HC |
953 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
954 | if (!c) | |
955 | return -ENOMEM; | |
956 | pcpu_devices[cpu].cpu = c; | |
957 | s = &c->dev; | |
08d07968 HC |
958 | c->hotpluggable = 1; |
959 | rc = register_cpu(c, cpu); | |
960 | if (rc) | |
961 | goto out; | |
962 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
963 | if (rc) | |
964 | goto out_cpu; | |
83a24e32 HC |
965 | if (cpu_online(cpu)) { |
966 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
967 | if (rc) | |
968 | goto out_online; | |
969 | } | |
970 | rc = topology_cpu_init(c); | |
971 | if (rc) | |
972 | goto out_topology; | |
973 | return 0; | |
974 | ||
975 | out_topology: | |
976 | if (cpu_online(cpu)) | |
977 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
978 | out_online: | |
08d07968 HC |
979 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
980 | out_cpu: | |
981 | #ifdef CONFIG_HOTPLUG_CPU | |
982 | unregister_cpu(c); | |
983 | #endif | |
984 | out: | |
985 | return rc; | |
986 | } | |
987 | ||
988 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 989 | |
67060d9c | 990 | int __ref smp_rescan_cpus(void) |
08d07968 | 991 | { |
8b646bd7 MS |
992 | struct sclp_cpu_info *info; |
993 | int nr; | |
08d07968 | 994 | |
8b646bd7 MS |
995 | info = smp_get_cpu_info(); |
996 | if (!info) | |
997 | return -ENOMEM; | |
9d40d2e3 | 998 | get_online_cpus(); |
0b18d318 | 999 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1000 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1001 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1002 | put_online_cpus(); |
8b646bd7 MS |
1003 | kfree(info); |
1004 | if (nr) | |
c10fde0d | 1005 | topology_schedule_update(); |
8b646bd7 | 1006 | return 0; |
1e489518 HC |
1007 | } |
1008 | ||
8a25a2fd KS |
1009 | static ssize_t __ref rescan_store(struct device *dev, |
1010 | struct device_attribute *attr, | |
c9be0a36 | 1011 | const char *buf, |
1e489518 HC |
1012 | size_t count) |
1013 | { | |
1014 | int rc; | |
1015 | ||
1016 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1017 | return rc ? rc : count; |
1018 | } | |
8a25a2fd | 1019 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1020 | #endif /* CONFIG_HOTPLUG_CPU */ |
1021 | ||
83a24e32 | 1022 | static int __init s390_smp_init(void) |
1da177e4 | 1023 | { |
f4edbcd5 | 1024 | int cpu, rc = 0; |
2fc2d1e9 | 1025 | |
08d07968 | 1026 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1027 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1028 | if (rc) |
1029 | return rc; | |
1030 | #endif | |
f4edbcd5 | 1031 | cpu_notifier_register_begin(); |
08d07968 HC |
1032 | for_each_present_cpu(cpu) { |
1033 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1034 | if (rc) |
f4edbcd5 | 1035 | goto out; |
1da177e4 | 1036 | } |
f4edbcd5 SB |
1037 | |
1038 | __hotcpu_notifier(smp_cpu_notify, 0); | |
1039 | ||
1040 | out: | |
1041 | cpu_notifier_register_done(); | |
1042 | return rc; | |
1da177e4 | 1043 | } |
83a24e32 | 1044 | subsys_initcall(s390_smp_init); |