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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/smp.c | |
3 | * | |
155af2f9 | 4 | * Copyright IBM Corp. 1999, 2009 |
1da177e4 | 5 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), |
39ce010d HC |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) |
7 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
13 | * We work with logical cpu numbering everywhere we can. The only | |
14 | * functions using the real cpu address (got from STAP) are the sigp | |
15 | * functions. For all other functions we use the identity mapping. | |
16 | * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is | |
17 | * used e.g. to find the idle task belonging to a logical cpu. Every array | |
18 | * in the kernel is sorted by the logical cpu number and not by the physical | |
19 | * one which is causing all the confusion with __cpu_logical_map and | |
20 | * cpu_number_map in other architectures. | |
21 | */ | |
22 | ||
395d31d4 MS |
23 | #define KMSG_COMPONENT "cpu" |
24 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
25 | ||
f230886b | 26 | #include <linux/workqueue.h> |
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
1da177e4 | 29 | #include <linux/mm.h> |
4e950f6f | 30 | #include <linux/err.h> |
1da177e4 LT |
31 | #include <linux/spinlock.h> |
32 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/cache.h> | |
35 | #include <linux/interrupt.h> | |
3324e60a | 36 | #include <linux/irqflags.h> |
1da177e4 | 37 | #include <linux/cpu.h> |
2b67fc46 | 38 | #include <linux/timex.h> |
411ed322 | 39 | #include <linux/bootmem.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
60a0c68d | 41 | #include <linux/crash_dump.h> |
cbb870c8 | 42 | #include <asm/asm-offsets.h> |
46b05d26 | 43 | #include <asm/ipl.h> |
2b67fc46 | 44 | #include <asm/setup.h> |
1da177e4 LT |
45 | #include <asm/sigp.h> |
46 | #include <asm/pgalloc.h> | |
47 | #include <asm/irq.h> | |
1da177e4 LT |
48 | #include <asm/cpcmd.h> |
49 | #include <asm/tlbflush.h> | |
2b67fc46 | 50 | #include <asm/timer.h> |
411ed322 | 51 | #include <asm/lowcore.h> |
08d07968 | 52 | #include <asm/sclp.h> |
76d4e00a | 53 | #include <asm/cputime.h> |
c742b31c | 54 | #include <asm/vdso.h> |
4bb5e07b | 55 | #include <asm/cpu.h> |
a806170e | 56 | #include "entry.h" |
1da177e4 | 57 | |
fb380aad | 58 | /* logical cpu to cpu address */ |
a93b8ec1 | 59 | unsigned short __cpu_logical_map[NR_CPUS]; |
fb380aad | 60 | |
1da177e4 LT |
61 | static struct task_struct *current_set[NR_CPUS]; |
62 | ||
08d07968 HC |
63 | static u8 smp_cpu_type; |
64 | static int smp_use_sigp_detection; | |
65 | ||
66 | enum s390_cpu_state { | |
67 | CPU_STATE_STANDBY, | |
68 | CPU_STATE_CONFIGURED, | |
69 | }; | |
70 | ||
dbd70fb4 | 71 | DEFINE_MUTEX(smp_cpu_state_mutex); |
c10fde0d | 72 | int smp_cpu_polarization[NR_CPUS]; |
08d07968 | 73 | static int smp_cpu_state[NR_CPUS]; |
c10fde0d | 74 | static int cpu_management; |
08d07968 HC |
75 | |
76 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
08d07968 | 77 | |
a93b8ec1 | 78 | static void smp_ext_bitcall(int, int); |
1da177e4 | 79 | |
a93b8ec1 | 80 | static int raw_cpu_stopped(int cpu) |
5c0b912e | 81 | { |
a93b8ec1 | 82 | u32 status; |
5c0b912e | 83 | |
a93b8ec1 | 84 | switch (raw_sigp_ps(&status, 0, cpu, sigp_sense)) { |
5c0b912e HC |
85 | case sigp_status_stored: |
86 | /* Check for stopped and check stop state */ | |
87 | if (status & 0x50) | |
88 | return 1; | |
89 | break; | |
90 | default: | |
91 | break; | |
92 | } | |
93 | return 0; | |
94 | } | |
95 | ||
a93b8ec1 HC |
96 | static inline int cpu_stopped(int cpu) |
97 | { | |
98 | return raw_cpu_stopped(cpu_logical_map(cpu)); | |
99 | } | |
100 | ||
1943f53c MH |
101 | /* |
102 | * Ensure that PSW restart is done on an online CPU | |
103 | */ | |
104 | void smp_restart_with_online_cpu(void) | |
105 | { | |
106 | int cpu; | |
107 | ||
108 | for_each_online_cpu(cpu) { | |
109 | if (stap() == __cpu_logical_map[cpu]) { | |
110 | /* We are online: Enable DAT again and return */ | |
b50511e4 | 111 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
1943f53c MH |
112 | return; |
113 | } | |
114 | } | |
115 | /* We are not online: Do PSW restart on an online CPU */ | |
116 | while (sigp(cpu, sigp_restart) == sigp_busy) | |
117 | cpu_relax(); | |
118 | /* And stop ourself */ | |
119 | while (raw_sigp(stap(), sigp_stop) == sigp_busy) | |
120 | cpu_relax(); | |
121 | for (;;); | |
122 | } | |
123 | ||
2c2df118 HC |
124 | void smp_switch_to_ipl_cpu(void (*func)(void *), void *data) |
125 | { | |
126 | struct _lowcore *lc, *current_lc; | |
127 | struct stack_frame *sf; | |
128 | struct pt_regs *regs; | |
129 | unsigned long sp; | |
130 | ||
131 | if (smp_processor_id() == 0) | |
132 | func(data); | |
b50511e4 MS |
133 | __load_psw_mask(PSW_DEFAULT_KEY | PSW_MASK_BASE | |
134 | PSW_MASK_EA | PSW_MASK_BA); | |
2c2df118 HC |
135 | /* Disable lowcore protection */ |
136 | __ctl_clear_bit(0, 28); | |
137 | current_lc = lowcore_ptr[smp_processor_id()]; | |
138 | lc = lowcore_ptr[0]; | |
139 | if (!lc) | |
140 | lc = current_lc; | |
b50511e4 MS |
141 | lc->restart_psw.mask = |
142 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
2c2df118 HC |
143 | lc->restart_psw.addr = PSW_ADDR_AMODE | (unsigned long) smp_restart_cpu; |
144 | if (!cpu_online(0)) | |
145 | smp_switch_to_cpu(func, data, 0, stap(), __cpu_logical_map[0]); | |
a93b8ec1 | 146 | while (sigp(0, sigp_stop_and_store_status) == sigp_busy) |
2c2df118 HC |
147 | cpu_relax(); |
148 | sp = lc->panic_stack; | |
149 | sp -= sizeof(struct pt_regs); | |
150 | regs = (struct pt_regs *) sp; | |
151 | memcpy(®s->gprs, ¤t_lc->gpregs_save_area, sizeof(regs->gprs)); | |
3931723f | 152 | regs->psw = current_lc->psw_save_area; |
2c2df118 HC |
153 | sp -= STACK_FRAME_OVERHEAD; |
154 | sf = (struct stack_frame *) sp; | |
3931723f | 155 | sf->back_chain = 0; |
2c2df118 HC |
156 | smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]); |
157 | } | |
158 | ||
677d7623 | 159 | void smp_send_stop(void) |
1da177e4 | 160 | { |
39ce010d | 161 | int cpu, rc; |
1da177e4 | 162 | |
677d7623 | 163 | /* Disable all interrupts/machine checks */ |
b50511e4 | 164 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 165 | trace_hardirqs_off(); |
1da177e4 | 166 | |
677d7623 | 167 | /* stop all processors */ |
1da177e4 LT |
168 | for_each_online_cpu(cpu) { |
169 | if (cpu == smp_processor_id()) | |
170 | continue; | |
171 | do { | |
a93b8ec1 | 172 | rc = sigp(cpu, sigp_stop); |
39ce010d | 173 | } while (rc == sigp_busy); |
1da177e4 | 174 | |
5c0b912e | 175 | while (!cpu_stopped(cpu)) |
c6b5b847 HC |
176 | cpu_relax(); |
177 | } | |
178 | } | |
179 | ||
1da177e4 LT |
180 | /* |
181 | * This is the main routine where commands issued by other | |
182 | * cpus are handled. | |
183 | */ | |
184 | ||
f6649a7e MS |
185 | static void do_ext_call_interrupt(unsigned int ext_int_code, |
186 | unsigned int param32, unsigned long param64) | |
1da177e4 | 187 | { |
39ce010d | 188 | unsigned long bits; |
1da177e4 | 189 | |
272f01bf | 190 | if ((ext_int_code & 0xffff) == 0x1202) |
2a3a2d66 HC |
191 | kstat_cpu(smp_processor_id()).irqs[EXTINT_EXC]++; |
192 | else | |
193 | kstat_cpu(smp_processor_id()).irqs[EXTINT_EMS]++; | |
39ce010d HC |
194 | /* |
195 | * handle bit signal external calls | |
39ce010d | 196 | */ |
1da177e4 LT |
197 | bits = xchg(&S390_lowcore.ext_call_fast, 0); |
198 | ||
184748cc PZ |
199 | if (test_bit(ec_schedule, &bits)) |
200 | scheduler_ipi(); | |
201 | ||
39ce010d | 202 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
203 | generic_smp_call_function_interrupt(); |
204 | ||
205 | if (test_bit(ec_call_function_single, &bits)) | |
206 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
207 | } |
208 | ||
209 | /* | |
210 | * Send an external call sigp to another cpu and return without waiting | |
211 | * for its completion. | |
212 | */ | |
a93b8ec1 | 213 | static void smp_ext_bitcall(int cpu, int sig) |
1da177e4 | 214 | { |
d98e19cc MS |
215 | int order; |
216 | ||
39ce010d HC |
217 | /* |
218 | * Set signaling bit in lowcore of target cpu and kick it | |
219 | */ | |
1da177e4 | 220 | set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); |
d98e19cc MS |
221 | while (1) { |
222 | order = smp_vcpu_scheduled(cpu) ? | |
223 | sigp_external_call : sigp_emergency_signal; | |
224 | if (sigp(cpu, order) != sigp_busy) | |
225 | break; | |
1da177e4 | 226 | udelay(10); |
d98e19cc | 227 | } |
1da177e4 LT |
228 | } |
229 | ||
630cd046 | 230 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
231 | { |
232 | int cpu; | |
233 | ||
630cd046 | 234 | for_each_cpu(cpu, mask) |
ca9fc75a HC |
235 | smp_ext_bitcall(cpu, ec_call_function); |
236 | } | |
237 | ||
238 | void arch_send_call_function_single_ipi(int cpu) | |
239 | { | |
240 | smp_ext_bitcall(cpu, ec_call_function_single); | |
241 | } | |
242 | ||
347a8dc3 | 243 | #ifndef CONFIG_64BIT |
1da177e4 LT |
244 | /* |
245 | * this function sends a 'purge tlb' signal to another CPU. | |
246 | */ | |
a806170e | 247 | static void smp_ptlb_callback(void *info) |
1da177e4 | 248 | { |
ba8a9229 | 249 | __tlb_flush_local(); |
1da177e4 LT |
250 | } |
251 | ||
252 | void smp_ptlb_all(void) | |
253 | { | |
15c8b6c1 | 254 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
255 | } |
256 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 257 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
258 | |
259 | /* | |
260 | * this function sends a 'reschedule' IPI to another CPU. | |
261 | * it goes straight through and wastes no time serializing | |
262 | * anything. Worst case is that we lose a reschedule ... | |
263 | */ | |
264 | void smp_send_reschedule(int cpu) | |
265 | { | |
39ce010d | 266 | smp_ext_bitcall(cpu, ec_schedule); |
1da177e4 LT |
267 | } |
268 | ||
269 | /* | |
270 | * parameter area for the set/clear control bit callbacks | |
271 | */ | |
94c12cc7 | 272 | struct ec_creg_mask_parms { |
1da177e4 LT |
273 | unsigned long orvals[16]; |
274 | unsigned long andvals[16]; | |
94c12cc7 | 275 | }; |
1da177e4 LT |
276 | |
277 | /* | |
278 | * callback for setting/clearing control bits | |
279 | */ | |
39ce010d HC |
280 | static void smp_ctl_bit_callback(void *info) |
281 | { | |
94c12cc7 | 282 | struct ec_creg_mask_parms *pp = info; |
1da177e4 LT |
283 | unsigned long cregs[16]; |
284 | int i; | |
39ce010d | 285 | |
94c12cc7 MS |
286 | __ctl_store(cregs, 0, 15); |
287 | for (i = 0; i <= 15; i++) | |
1da177e4 | 288 | cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i]; |
94c12cc7 | 289 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
290 | } |
291 | ||
292 | /* | |
293 | * Set a bit in a control register of all cpus | |
294 | */ | |
94c12cc7 MS |
295 | void smp_ctl_set_bit(int cr, int bit) |
296 | { | |
297 | struct ec_creg_mask_parms parms; | |
1da177e4 | 298 | |
94c12cc7 MS |
299 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
300 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
859c9651 | 301 | parms.orvals[cr] = 1UL << bit; |
15c8b6c1 | 302 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 303 | } |
39ce010d | 304 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
305 | |
306 | /* | |
307 | * Clear a bit in a control register of all cpus | |
308 | */ | |
94c12cc7 MS |
309 | void smp_ctl_clear_bit(int cr, int bit) |
310 | { | |
311 | struct ec_creg_mask_parms parms; | |
1da177e4 | 312 | |
94c12cc7 MS |
313 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
314 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
859c9651 | 315 | parms.andvals[cr] = ~(1UL << bit); |
15c8b6c1 | 316 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 317 | } |
39ce010d | 318 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 319 | |
60a0c68d | 320 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 321 | |
285f6722 | 322 | static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) |
411ed322 | 323 | { |
60a0c68d MH |
324 | if (ipl_info.type != IPL_TYPE_FCP_DUMP && !OLDMEM_BASE) |
325 | return; | |
326 | if (is_kdump_kernel()) | |
411ed322 | 327 | return; |
285f6722 | 328 | if (cpu >= NR_CPUS) { |
395d31d4 MS |
329 | pr_warning("CPU %i exceeds the maximum %i and is excluded from " |
330 | "the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 331 | return; |
411ed322 | 332 | } |
f64ca217 | 333 | zfcpdump_save_areas[cpu] = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
a93b8ec1 | 334 | while (raw_sigp(phy_cpu, sigp_stop_and_store_status) == sigp_busy) |
285f6722 | 335 | cpu_relax(); |
92fe3132 MH |
336 | memcpy_real(zfcpdump_save_areas[cpu], |
337 | (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE, | |
338 | sizeof(struct save_area)); | |
411ed322 MH |
339 | } |
340 | ||
f64ca217 | 341 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
411ed322 MH |
342 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); |
343 | ||
344 | #else | |
285f6722 HC |
345 | |
346 | static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { } | |
347 | ||
59f2e69d | 348 | #endif /* CONFIG_ZFCPDUMP */ |
411ed322 | 349 | |
08d07968 HC |
350 | static int cpu_known(int cpu_id) |
351 | { | |
352 | int cpu; | |
353 | ||
354 | for_each_present_cpu(cpu) { | |
355 | if (__cpu_logical_map[cpu] == cpu_id) | |
356 | return 1; | |
357 | } | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static int smp_rescan_cpus_sigp(cpumask_t avail) | |
362 | { | |
363 | int cpu_id, logical_cpu; | |
364 | ||
93632d1b RR |
365 | logical_cpu = cpumask_first(&avail); |
366 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 367 | return 0; |
4bb5e07b | 368 | for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) { |
08d07968 HC |
369 | if (cpu_known(cpu_id)) |
370 | continue; | |
371 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 372 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
08d07968 HC |
373 | if (!cpu_stopped(logical_cpu)) |
374 | continue; | |
0f1959f5 | 375 | set_cpu_present(logical_cpu, true); |
08d07968 | 376 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; |
93632d1b RR |
377 | logical_cpu = cpumask_next(logical_cpu, &avail); |
378 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
379 | break; |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
48483b32 | 384 | static int smp_rescan_cpus_sclp(cpumask_t avail) |
08d07968 HC |
385 | { |
386 | struct sclp_cpu_info *info; | |
387 | int cpu_id, logical_cpu, cpu; | |
388 | int rc; | |
389 | ||
93632d1b RR |
390 | logical_cpu = cpumask_first(&avail); |
391 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 392 | return 0; |
48483b32 | 393 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
08d07968 HC |
394 | if (!info) |
395 | return -ENOMEM; | |
396 | rc = sclp_get_cpu_info(info); | |
397 | if (rc) | |
398 | goto out; | |
399 | for (cpu = 0; cpu < info->combined; cpu++) { | |
400 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
401 | continue; | |
402 | cpu_id = info->cpu[cpu].address; | |
403 | if (cpu_known(cpu_id)) | |
404 | continue; | |
405 | __cpu_logical_map[logical_cpu] = cpu_id; | |
c10fde0d | 406 | smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN; |
0f1959f5 | 407 | set_cpu_present(logical_cpu, true); |
08d07968 HC |
408 | if (cpu >= info->configured) |
409 | smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY; | |
410 | else | |
411 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
412 | logical_cpu = cpumask_next(logical_cpu, &avail); |
413 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
414 | break; |
415 | } | |
416 | out: | |
48483b32 | 417 | kfree(info); |
08d07968 HC |
418 | return rc; |
419 | } | |
420 | ||
1e489518 | 421 | static int __smp_rescan_cpus(void) |
08d07968 HC |
422 | { |
423 | cpumask_t avail; | |
424 | ||
0f1959f5 | 425 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
08d07968 HC |
426 | if (smp_use_sigp_detection) |
427 | return smp_rescan_cpus_sigp(avail); | |
428 | else | |
429 | return smp_rescan_cpus_sclp(avail); | |
1da177e4 LT |
430 | } |
431 | ||
48483b32 HC |
432 | static void __init smp_detect_cpus(void) |
433 | { | |
434 | unsigned int cpu, c_cpus, s_cpus; | |
435 | struct sclp_cpu_info *info; | |
436 | u16 boot_cpu_addr, cpu_addr; | |
437 | ||
438 | c_cpus = 1; | |
439 | s_cpus = 0; | |
7b468488 | 440 | boot_cpu_addr = __cpu_logical_map[0]; |
48483b32 HC |
441 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
442 | if (!info) | |
443 | panic("smp_detect_cpus failed to allocate memory\n"); | |
60a0c68d MH |
444 | #ifdef CONFIG_CRASH_DUMP |
445 | if (OLDMEM_BASE && !is_kdump_kernel()) { | |
446 | struct save_area *save_area; | |
447 | ||
448 | save_area = kmalloc(sizeof(*save_area), GFP_KERNEL); | |
449 | if (!save_area) | |
450 | panic("could not allocate memory for save area\n"); | |
451 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
452 | 0x200, 0); | |
453 | zfcpdump_save_areas[0] = save_area; | |
454 | } | |
455 | #endif | |
48483b32 HC |
456 | /* Use sigp detection algorithm if sclp doesn't work. */ |
457 | if (sclp_get_cpu_info(info)) { | |
458 | smp_use_sigp_detection = 1; | |
4bb5e07b | 459 | for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) { |
48483b32 HC |
460 | if (cpu == boot_cpu_addr) |
461 | continue; | |
a93b8ec1 | 462 | if (!raw_cpu_stopped(cpu)) |
48483b32 HC |
463 | continue; |
464 | smp_get_save_area(c_cpus, cpu); | |
465 | c_cpus++; | |
466 | } | |
467 | goto out; | |
468 | } | |
469 | ||
470 | if (info->has_cpu_type) { | |
471 | for (cpu = 0; cpu < info->combined; cpu++) { | |
472 | if (info->cpu[cpu].address == boot_cpu_addr) { | |
473 | smp_cpu_type = info->cpu[cpu].type; | |
474 | break; | |
475 | } | |
476 | } | |
477 | } | |
478 | ||
479 | for (cpu = 0; cpu < info->combined; cpu++) { | |
480 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
481 | continue; | |
482 | cpu_addr = info->cpu[cpu].address; | |
483 | if (cpu_addr == boot_cpu_addr) | |
484 | continue; | |
a93b8ec1 | 485 | if (!raw_cpu_stopped(cpu_addr)) { |
48483b32 HC |
486 | s_cpus++; |
487 | continue; | |
488 | } | |
489 | smp_get_save_area(c_cpus, cpu_addr); | |
490 | c_cpus++; | |
491 | } | |
492 | out: | |
493 | kfree(info); | |
395d31d4 | 494 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 495 | get_online_cpus(); |
1e489518 | 496 | __smp_rescan_cpus(); |
9d40d2e3 | 497 | put_online_cpus(); |
48483b32 HC |
498 | } |
499 | ||
1da177e4 | 500 | /* |
39ce010d | 501 | * Activate a secondary processor. |
1da177e4 | 502 | */ |
ea1f4eec | 503 | int __cpuinit start_secondary(void *cpuvoid) |
1da177e4 | 504 | { |
39ce010d | 505 | cpu_init(); |
5bfb5d69 | 506 | preempt_disable(); |
39ce010d | 507 | init_cpu_timer(); |
39ce010d | 508 | init_cpu_vtimer(); |
29b08d2b HC |
509 | pfault_init(); |
510 | ||
e545a614 | 511 | notify_cpu_starting(smp_processor_id()); |
ca9fc75a | 512 | ipi_call_lock(); |
0f1959f5 | 513 | set_cpu_online(smp_processor_id(), true); |
ca9fc75a | 514 | ipi_call_unlock(); |
7dd6b334 | 515 | __ctl_clear_bit(0, 28); /* Disable lowcore protection */ |
b50511e4 MS |
516 | S390_lowcore.restart_psw.mask = |
517 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
7dd6b334 MH |
518 | S390_lowcore.restart_psw.addr = |
519 | PSW_ADDR_AMODE | (unsigned long) psw_restart_int_handler; | |
520 | __ctl_set_bit(0, 28); /* Enable lowcore protection */ | |
cc34321d HC |
521 | /* |
522 | * Wait until the cpu which brought this one up marked it | |
523 | * active before enabling interrupts. | |
524 | */ | |
525 | while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask)) | |
526 | cpu_relax(); | |
1da177e4 | 527 | local_irq_enable(); |
39ce010d HC |
528 | /* cpu_idle will call schedule for us */ |
529 | cpu_idle(); | |
530 | return 0; | |
1da177e4 LT |
531 | } |
532 | ||
f230886b HC |
533 | struct create_idle { |
534 | struct work_struct work; | |
535 | struct task_struct *idle; | |
536 | struct completion done; | |
537 | int cpu; | |
538 | }; | |
539 | ||
540 | static void __cpuinit smp_fork_idle(struct work_struct *work) | |
1da177e4 | 541 | { |
f230886b | 542 | struct create_idle *c_idle; |
1da177e4 | 543 | |
f230886b HC |
544 | c_idle = container_of(work, struct create_idle, work); |
545 | c_idle->idle = fork_idle(c_idle->cpu); | |
546 | complete(&c_idle->done); | |
1da177e4 LT |
547 | } |
548 | ||
1cb6bb4b HC |
549 | static int __cpuinit smp_alloc_lowcore(int cpu) |
550 | { | |
551 | unsigned long async_stack, panic_stack; | |
552 | struct _lowcore *lowcore; | |
1cb6bb4b | 553 | |
3fd26a77 | 554 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
1cb6bb4b HC |
555 | if (!lowcore) |
556 | return -ENOMEM; | |
557 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
1cb6bb4b | 558 | panic_stack = __get_free_page(GFP_KERNEL); |
591bb4f6 HC |
559 | if (!panic_stack || !async_stack) |
560 | goto out; | |
98c7b388 HC |
561 | memcpy(lowcore, &S390_lowcore, 512); |
562 | memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512); | |
1cb6bb4b HC |
563 | lowcore->async_stack = async_stack + ASYNC_SIZE; |
564 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
b50511e4 MS |
565 | lowcore->restart_psw.mask = |
566 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
7dd6b334 MH |
567 | lowcore->restart_psw.addr = |
568 | PSW_ADDR_AMODE | (unsigned long) restart_int_handler; | |
569 | if (user_mode != HOME_SPACE_MODE) | |
570 | lowcore->restart_psw.mask |= PSW_ASC_HOME; | |
1cb6bb4b HC |
571 | #ifndef CONFIG_64BIT |
572 | if (MACHINE_HAS_IEEE) { | |
573 | unsigned long save_area; | |
574 | ||
575 | save_area = get_zeroed_page(GFP_KERNEL); | |
576 | if (!save_area) | |
33b1d09e | 577 | goto out; |
1cb6bb4b HC |
578 | lowcore->extended_save_area_addr = (u32) save_area; |
579 | } | |
c742b31c MS |
580 | #else |
581 | if (vdso_alloc_per_cpu(cpu, lowcore)) | |
582 | goto out; | |
1cb6bb4b HC |
583 | #endif |
584 | lowcore_ptr[cpu] = lowcore; | |
585 | return 0; | |
586 | ||
591bb4f6 | 587 | out: |
33b1d09e | 588 | free_page(panic_stack); |
1cb6bb4b | 589 | free_pages(async_stack, ASYNC_ORDER); |
3fd26a77 | 590 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
591 | return -ENOMEM; |
592 | } | |
593 | ||
1cb6bb4b HC |
594 | static void smp_free_lowcore(int cpu) |
595 | { | |
596 | struct _lowcore *lowcore; | |
1cb6bb4b | 597 | |
1cb6bb4b HC |
598 | lowcore = lowcore_ptr[cpu]; |
599 | #ifndef CONFIG_64BIT | |
600 | if (MACHINE_HAS_IEEE) | |
601 | free_page((unsigned long) lowcore->extended_save_area_addr); | |
c742b31c MS |
602 | #else |
603 | vdso_free_per_cpu(cpu, lowcore); | |
1cb6bb4b HC |
604 | #endif |
605 | free_page(lowcore->panic_stack - PAGE_SIZE); | |
606 | free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER); | |
3fd26a77 | 607 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
608 | lowcore_ptr[cpu] = NULL; |
609 | } | |
1cb6bb4b | 610 | |
1da177e4 | 611 | /* Upping and downing of CPUs */ |
1cb6bb4b | 612 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 | 613 | { |
39ce010d | 614 | struct _lowcore *cpu_lowcore; |
f230886b | 615 | struct create_idle c_idle; |
a93b8ec1 | 616 | struct task_struct *idle; |
1da177e4 | 617 | struct stack_frame *sf; |
d0d3cdf4 | 618 | u32 lowcore; |
a93b8ec1 | 619 | int ccode; |
1da177e4 | 620 | |
08d07968 HC |
621 | if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) |
622 | return -EIO; | |
f230886b HC |
623 | idle = current_set[cpu]; |
624 | if (!idle) { | |
625 | c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done); | |
626 | INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle); | |
627 | c_idle.cpu = cpu; | |
628 | schedule_work(&c_idle.work); | |
629 | wait_for_completion(&c_idle.done); | |
630 | if (IS_ERR(c_idle.idle)) | |
631 | return PTR_ERR(c_idle.idle); | |
632 | idle = c_idle.idle; | |
633 | current_set[cpu] = c_idle.idle; | |
634 | } | |
da7f51c1 | 635 | init_idle(idle, cpu); |
1cb6bb4b HC |
636 | if (smp_alloc_lowcore(cpu)) |
637 | return -ENOMEM; | |
d0d3cdf4 | 638 | do { |
a93b8ec1 | 639 | ccode = sigp(cpu, sigp_initial_cpu_reset); |
d0d3cdf4 HC |
640 | if (ccode == sigp_busy) |
641 | udelay(10); | |
642 | if (ccode == sigp_not_operational) | |
643 | goto err_out; | |
644 | } while (ccode == sigp_busy); | |
645 | ||
646 | lowcore = (u32)(unsigned long)lowcore_ptr[cpu]; | |
a93b8ec1 | 647 | while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy) |
d0d3cdf4 | 648 | udelay(10); |
1da177e4 | 649 | |
39ce010d | 650 | cpu_lowcore = lowcore_ptr[cpu]; |
1da177e4 | 651 | cpu_lowcore->kernel_stack = (unsigned long) |
39ce010d | 652 | task_stack_page(idle) + THREAD_SIZE; |
1cb6bb4b | 653 | cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle); |
1da177e4 LT |
654 | sf = (struct stack_frame *) (cpu_lowcore->kernel_stack |
655 | - sizeof(struct pt_regs) | |
656 | - sizeof(struct stack_frame)); | |
657 | memset(sf, 0, sizeof(struct stack_frame)); | |
658 | sf->gprs[9] = (unsigned long) sf; | |
659 | cpu_lowcore->save_area[15] = (unsigned long) sf; | |
24d3e210 | 660 | __ctl_store(cpu_lowcore->cregs_save_area, 0, 15); |
050eef36 | 661 | atomic_inc(&init_mm.context.attach_count); |
94c12cc7 MS |
662 | asm volatile( |
663 | " stam 0,15,0(%0)" | |
664 | : : "a" (&cpu_lowcore->access_regs_save_area) : "memory"); | |
1da177e4 | 665 | cpu_lowcore->percpu_offset = __per_cpu_offset[cpu]; |
39ce010d | 666 | cpu_lowcore->current_task = (unsigned long) idle; |
7b468488 | 667 | cpu_lowcore->cpu_nr = cpu; |
591bb4f6 | 668 | cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce; |
25097bf1 | 669 | cpu_lowcore->machine_flags = S390_lowcore.machine_flags; |
dfd9f7ab | 670 | cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func; |
14375bc4 MS |
671 | memcpy(cpu_lowcore->stfle_fac_list, S390_lowcore.stfle_fac_list, |
672 | MAX_FACILITY_BIT/8); | |
1da177e4 | 673 | eieio(); |
699ff13f | 674 | |
a93b8ec1 | 675 | while (sigp(cpu, sigp_restart) == sigp_busy) |
699ff13f | 676 | udelay(10); |
1da177e4 LT |
677 | |
678 | while (!cpu_online(cpu)) | |
679 | cpu_relax(); | |
680 | return 0; | |
d0d3cdf4 HC |
681 | |
682 | err_out: | |
683 | smp_free_lowcore(cpu); | |
684 | return -EIO; | |
1da177e4 LT |
685 | } |
686 | ||
48483b32 | 687 | static int __init setup_possible_cpus(char *s) |
255acee7 | 688 | { |
48483b32 | 689 | int pcpus, cpu; |
255acee7 | 690 | |
48483b32 | 691 | pcpus = simple_strtoul(s, NULL, 0); |
88e01285 HC |
692 | init_cpu_possible(cpumask_of(0)); |
693 | for (cpu = 1; cpu < pcpus && cpu < nr_cpu_ids; cpu++) | |
def6cfb7 | 694 | set_cpu_possible(cpu, true); |
37a33026 HC |
695 | return 0; |
696 | } | |
697 | early_param("possible_cpus", setup_possible_cpus); | |
698 | ||
48483b32 HC |
699 | #ifdef CONFIG_HOTPLUG_CPU |
700 | ||
39ce010d | 701 | int __cpu_disable(void) |
1da177e4 | 702 | { |
94c12cc7 | 703 | struct ec_creg_mask_parms cr_parms; |
f3705136 | 704 | int cpu = smp_processor_id(); |
1da177e4 | 705 | |
0f1959f5 | 706 | set_cpu_online(cpu, false); |
1da177e4 | 707 | |
1da177e4 | 708 | /* Disable pfault pseudo page faults on this cpu. */ |
29b08d2b | 709 | pfault_fini(); |
1da177e4 | 710 | |
94c12cc7 MS |
711 | memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals)); |
712 | memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals)); | |
1da177e4 | 713 | |
94c12cc7 | 714 | /* disable all external interrupts */ |
1da177e4 | 715 | cr_parms.orvals[0] = 0; |
5bd41878 | 716 | cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 11 | |
cadfce72 JG |
717 | 1 << 10 | 1 << 9 | 1 << 6 | 1 << 5 | |
718 | 1 << 4); | |
1da177e4 | 719 | /* disable all I/O interrupts */ |
1da177e4 | 720 | cr_parms.orvals[6] = 0; |
39ce010d HC |
721 | cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | |
722 | 1 << 27 | 1 << 26 | 1 << 25 | 1 << 24); | |
1da177e4 | 723 | /* disable most machine checks */ |
1da177e4 | 724 | cr_parms.orvals[14] = 0; |
39ce010d HC |
725 | cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 | |
726 | 1 << 25 | 1 << 24); | |
94c12cc7 | 727 | |
1da177e4 LT |
728 | smp_ctl_bit_callback(&cr_parms); |
729 | ||
1da177e4 LT |
730 | return 0; |
731 | } | |
732 | ||
39ce010d | 733 | void __cpu_die(unsigned int cpu) |
1da177e4 LT |
734 | { |
735 | /* Wait until target cpu is down */ | |
5c0b912e | 736 | while (!cpu_stopped(cpu)) |
1da177e4 | 737 | cpu_relax(); |
a93b8ec1 | 738 | while (sigp_p(0, cpu, sigp_set_prefix) == sigp_busy) |
4f8048ee | 739 | udelay(10); |
1cb6bb4b | 740 | smp_free_lowcore(cpu); |
050eef36 | 741 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
742 | } |
743 | ||
b456d94a | 744 | void __noreturn cpu_die(void) |
1da177e4 LT |
745 | { |
746 | idle_task_exit(); | |
a93b8ec1 | 747 | while (sigp(smp_processor_id(), sigp_stop) == sigp_busy) |
f8501ba7 | 748 | cpu_relax(); |
39ce010d | 749 | for (;;); |
1da177e4 LT |
750 | } |
751 | ||
255acee7 HC |
752 | #endif /* CONFIG_HOTPLUG_CPU */ |
753 | ||
1da177e4 LT |
754 | void __init smp_prepare_cpus(unsigned int max_cpus) |
755 | { | |
591bb4f6 HC |
756 | #ifndef CONFIG_64BIT |
757 | unsigned long save_area = 0; | |
758 | #endif | |
759 | unsigned long async_stack, panic_stack; | |
760 | struct _lowcore *lowcore; | |
39ce010d | 761 | |
48483b32 HC |
762 | smp_detect_cpus(); |
763 | ||
39ce010d HC |
764 | /* request the 0x1201 emergency signal external interrupt */ |
765 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
766 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
767 | /* request the 0x1202 external call external interrupt */ |
768 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
769 | panic("Couldn't request external interrupt 0x1202"); | |
1da177e4 | 770 | |
591bb4f6 | 771 | /* Reallocate current lowcore, but keep its contents. */ |
3fd26a77 | 772 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
591bb4f6 HC |
773 | panic_stack = __get_free_page(GFP_KERNEL); |
774 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
c742b31c | 775 | BUG_ON(!lowcore || !panic_stack || !async_stack); |
347a8dc3 | 776 | #ifndef CONFIG_64BIT |
77fa2245 | 777 | if (MACHINE_HAS_IEEE) |
591bb4f6 | 778 | save_area = get_zeroed_page(GFP_KERNEL); |
77fa2245 | 779 | #endif |
591bb4f6 HC |
780 | local_irq_disable(); |
781 | local_mcck_disable(); | |
782 | lowcore_ptr[smp_processor_id()] = lowcore; | |
783 | *lowcore = S390_lowcore; | |
784 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
785 | lowcore->async_stack = async_stack + ASYNC_SIZE; | |
786 | #ifndef CONFIG_64BIT | |
787 | if (MACHINE_HAS_IEEE) | |
788 | lowcore->extended_save_area_addr = (u32) save_area; | |
789 | #endif | |
790 | set_prefix((u32)(unsigned long) lowcore); | |
791 | local_mcck_enable(); | |
792 | local_irq_enable(); | |
3a6ba460 HC |
793 | #ifdef CONFIG_64BIT |
794 | if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore)) | |
795 | BUG(); | |
796 | #endif | |
1da177e4 LT |
797 | } |
798 | ||
ea1f4eec | 799 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
800 | { |
801 | BUG_ON(smp_processor_id() != 0); | |
802 | ||
48483b32 | 803 | current_thread_info()->cpu = 0; |
0f1959f5 KM |
804 | set_cpu_present(0, true); |
805 | set_cpu_online(0, true); | |
1da177e4 LT |
806 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
807 | current_set[0] = current; | |
08d07968 | 808 | smp_cpu_state[0] = CPU_STATE_CONFIGURED; |
c10fde0d | 809 | smp_cpu_polarization[0] = POLARIZATION_UNKNWN; |
1da177e4 LT |
810 | } |
811 | ||
ea1f4eec | 812 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 813 | { |
1da177e4 LT |
814 | } |
815 | ||
02beaccc HC |
816 | void __init smp_setup_processor_id(void) |
817 | { | |
818 | S390_lowcore.cpu_nr = 0; | |
819 | __cpu_logical_map[0] = stap(); | |
820 | } | |
821 | ||
1da177e4 LT |
822 | /* |
823 | * the frequency of the profiling timer can be changed | |
824 | * by writing a multiplier value into /proc/profile. | |
825 | * | |
826 | * usually you want to run this on all CPUs ;) | |
827 | */ | |
828 | int setup_profiling_timer(unsigned int multiplier) | |
829 | { | |
39ce010d | 830 | return 0; |
1da177e4 LT |
831 | } |
832 | ||
08d07968 | 833 | #ifdef CONFIG_HOTPLUG_CPU |
4a0b2b4d AK |
834 | static ssize_t cpu_configure_show(struct sys_device *dev, |
835 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
836 | { |
837 | ssize_t count; | |
838 | ||
839 | mutex_lock(&smp_cpu_state_mutex); | |
840 | count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]); | |
841 | mutex_unlock(&smp_cpu_state_mutex); | |
842 | return count; | |
843 | } | |
844 | ||
4a0b2b4d AK |
845 | static ssize_t cpu_configure_store(struct sys_device *dev, |
846 | struct sysdev_attribute *attr, | |
847 | const char *buf, size_t count) | |
08d07968 HC |
848 | { |
849 | int cpu = dev->id; | |
850 | int val, rc; | |
851 | char delim; | |
852 | ||
853 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
854 | return -EINVAL; | |
855 | if (val != 0 && val != 1) | |
856 | return -EINVAL; | |
857 | ||
9d40d2e3 | 858 | get_online_cpus(); |
0b18d318 | 859 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 860 | rc = -EBUSY; |
2c2df118 HC |
861 | /* disallow configuration changes of online cpus and cpu 0 */ |
862 | if (cpu_online(cpu) || cpu == 0) | |
08d07968 HC |
863 | goto out; |
864 | rc = 0; | |
865 | switch (val) { | |
866 | case 0: | |
867 | if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) { | |
868 | rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]); | |
c10fde0d | 869 | if (!rc) { |
08d07968 | 870 | smp_cpu_state[cpu] = CPU_STATE_STANDBY; |
c10fde0d HC |
871 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
872 | } | |
08d07968 HC |
873 | } |
874 | break; | |
875 | case 1: | |
876 | if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) { | |
877 | rc = sclp_cpu_configure(__cpu_logical_map[cpu]); | |
c10fde0d | 878 | if (!rc) { |
08d07968 | 879 | smp_cpu_state[cpu] = CPU_STATE_CONFIGURED; |
c10fde0d HC |
880 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
881 | } | |
08d07968 HC |
882 | } |
883 | break; | |
884 | default: | |
885 | break; | |
886 | } | |
887 | out: | |
08d07968 | 888 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 889 | put_online_cpus(); |
08d07968 HC |
890 | return rc ? rc : count; |
891 | } | |
892 | static SYSDEV_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); | |
893 | #endif /* CONFIG_HOTPLUG_CPU */ | |
894 | ||
4a0b2b4d AK |
895 | static ssize_t cpu_polarization_show(struct sys_device *dev, |
896 | struct sysdev_attribute *attr, char *buf) | |
c10fde0d HC |
897 | { |
898 | int cpu = dev->id; | |
899 | ssize_t count; | |
900 | ||
901 | mutex_lock(&smp_cpu_state_mutex); | |
902 | switch (smp_cpu_polarization[cpu]) { | |
903 | case POLARIZATION_HRZ: | |
904 | count = sprintf(buf, "horizontal\n"); | |
905 | break; | |
906 | case POLARIZATION_VL: | |
907 | count = sprintf(buf, "vertical:low\n"); | |
908 | break; | |
909 | case POLARIZATION_VM: | |
910 | count = sprintf(buf, "vertical:medium\n"); | |
911 | break; | |
912 | case POLARIZATION_VH: | |
913 | count = sprintf(buf, "vertical:high\n"); | |
914 | break; | |
915 | default: | |
916 | count = sprintf(buf, "unknown\n"); | |
917 | break; | |
918 | } | |
919 | mutex_unlock(&smp_cpu_state_mutex); | |
920 | return count; | |
921 | } | |
922 | static SYSDEV_ATTR(polarization, 0444, cpu_polarization_show, NULL); | |
923 | ||
4a0b2b4d AK |
924 | static ssize_t show_cpu_address(struct sys_device *dev, |
925 | struct sysdev_attribute *attr, char *buf) | |
08d07968 HC |
926 | { |
927 | return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]); | |
928 | } | |
929 | static SYSDEV_ATTR(address, 0444, show_cpu_address, NULL); | |
930 | ||
931 | ||
932 | static struct attribute *cpu_common_attrs[] = { | |
933 | #ifdef CONFIG_HOTPLUG_CPU | |
934 | &attr_configure.attr, | |
935 | #endif | |
936 | &attr_address.attr, | |
c10fde0d | 937 | &attr_polarization.attr, |
08d07968 HC |
938 | NULL, |
939 | }; | |
940 | ||
941 | static struct attribute_group cpu_common_attr_group = { | |
942 | .attrs = cpu_common_attrs, | |
943 | }; | |
1da177e4 | 944 | |
4a0b2b4d AK |
945 | static ssize_t show_capability(struct sys_device *dev, |
946 | struct sysdev_attribute *attr, char *buf) | |
2fc2d1e9 HC |
947 | { |
948 | unsigned int capability; | |
949 | int rc; | |
950 | ||
951 | rc = get_cpu_capability(&capability); | |
952 | if (rc) | |
953 | return rc; | |
954 | return sprintf(buf, "%u\n", capability); | |
955 | } | |
956 | static SYSDEV_ATTR(capability, 0444, show_capability, NULL); | |
957 | ||
4a0b2b4d AK |
958 | static ssize_t show_idle_count(struct sys_device *dev, |
959 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
960 | { |
961 | struct s390_idle_data *idle; | |
962 | unsigned long long idle_count; | |
e98bbaaf | 963 | unsigned int sequence; |
fae8b22d HC |
964 | |
965 | idle = &per_cpu(s390_idle, dev->id); | |
e98bbaaf MS |
966 | repeat: |
967 | sequence = idle->sequence; | |
968 | smp_rmb(); | |
969 | if (sequence & 1) | |
970 | goto repeat; | |
fae8b22d | 971 | idle_count = idle->idle_count; |
6f430924 MS |
972 | if (idle->idle_enter) |
973 | idle_count++; | |
e98bbaaf MS |
974 | smp_rmb(); |
975 | if (idle->sequence != sequence) | |
976 | goto repeat; | |
fae8b22d HC |
977 | return sprintf(buf, "%llu\n", idle_count); |
978 | } | |
979 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); | |
980 | ||
4a0b2b4d AK |
981 | static ssize_t show_idle_time(struct sys_device *dev, |
982 | struct sysdev_attribute *attr, char *buf) | |
fae8b22d HC |
983 | { |
984 | struct s390_idle_data *idle; | |
6f430924 | 985 | unsigned long long now, idle_time, idle_enter; |
e98bbaaf | 986 | unsigned int sequence; |
fae8b22d HC |
987 | |
988 | idle = &per_cpu(s390_idle, dev->id); | |
6f430924 | 989 | now = get_clock(); |
e98bbaaf MS |
990 | repeat: |
991 | sequence = idle->sequence; | |
992 | smp_rmb(); | |
993 | if (sequence & 1) | |
994 | goto repeat; | |
6f430924 MS |
995 | idle_time = idle->idle_time; |
996 | idle_enter = idle->idle_enter; | |
997 | if (idle_enter != 0ULL && idle_enter < now) | |
998 | idle_time += now - idle_enter; | |
e98bbaaf MS |
999 | smp_rmb(); |
1000 | if (idle->sequence != sequence) | |
1001 | goto repeat; | |
6f430924 | 1002 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 1003 | } |
69d39d66 | 1004 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 1005 | |
08d07968 | 1006 | static struct attribute *cpu_online_attrs[] = { |
fae8b22d HC |
1007 | &attr_capability.attr, |
1008 | &attr_idle_count.attr, | |
69d39d66 | 1009 | &attr_idle_time_us.attr, |
fae8b22d HC |
1010 | NULL, |
1011 | }; | |
1012 | ||
08d07968 HC |
1013 | static struct attribute_group cpu_online_attr_group = { |
1014 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1015 | }; |
1016 | ||
2fc2d1e9 HC |
1017 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
1018 | unsigned long action, void *hcpu) | |
1019 | { | |
1020 | unsigned int cpu = (unsigned int)(long)hcpu; | |
1021 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
1022 | struct sys_device *s = &c->sysdev; | |
fae8b22d | 1023 | struct s390_idle_data *idle; |
d882ba69 | 1024 | int err = 0; |
2fc2d1e9 HC |
1025 | |
1026 | switch (action) { | |
1027 | case CPU_ONLINE: | |
8bb78442 | 1028 | case CPU_ONLINE_FROZEN: |
fae8b22d | 1029 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 1030 | memset(idle, 0, sizeof(struct s390_idle_data)); |
d882ba69 | 1031 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1032 | break; |
1033 | case CPU_DEAD: | |
8bb78442 | 1034 | case CPU_DEAD_FROZEN: |
08d07968 | 1035 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1036 | break; |
1037 | } | |
d882ba69 | 1038 | return notifier_from_errno(err); |
2fc2d1e9 HC |
1039 | } |
1040 | ||
1041 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 1042 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
1043 | }; |
1044 | ||
2bc89b5e | 1045 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 HC |
1046 | { |
1047 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
1048 | struct sys_device *s = &c->sysdev; | |
1049 | int rc; | |
1050 | ||
1051 | c->hotpluggable = 1; | |
1052 | rc = register_cpu(c, cpu); | |
1053 | if (rc) | |
1054 | goto out; | |
1055 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1056 | if (rc) | |
1057 | goto out_cpu; | |
1058 | if (!cpu_online(cpu)) | |
1059 | goto out; | |
1060 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1061 | if (!rc) | |
1062 | return 0; | |
1063 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); | |
1064 | out_cpu: | |
1065 | #ifdef CONFIG_HOTPLUG_CPU | |
1066 | unregister_cpu(c); | |
1067 | #endif | |
1068 | out: | |
1069 | return rc; | |
1070 | } | |
1071 | ||
1072 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1073 | |
67060d9c | 1074 | int __ref smp_rescan_cpus(void) |
08d07968 HC |
1075 | { |
1076 | cpumask_t newcpus; | |
1077 | int cpu; | |
1078 | int rc; | |
1079 | ||
9d40d2e3 | 1080 | get_online_cpus(); |
0b18d318 | 1081 | mutex_lock(&smp_cpu_state_mutex); |
0f1959f5 | 1082 | cpumask_copy(&newcpus, cpu_present_mask); |
1e489518 | 1083 | rc = __smp_rescan_cpus(); |
08d07968 HC |
1084 | if (rc) |
1085 | goto out; | |
0f1959f5 KM |
1086 | cpumask_andnot(&newcpus, cpu_present_mask, &newcpus); |
1087 | for_each_cpu(cpu, &newcpus) { | |
08d07968 HC |
1088 | rc = smp_add_present_cpu(cpu); |
1089 | if (rc) | |
0f1959f5 | 1090 | set_cpu_present(cpu, false); |
08d07968 HC |
1091 | } |
1092 | rc = 0; | |
1093 | out: | |
08d07968 | 1094 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1095 | put_online_cpus(); |
0f1959f5 | 1096 | if (!cpumask_empty(&newcpus)) |
c10fde0d | 1097 | topology_schedule_update(); |
1e489518 HC |
1098 | return rc; |
1099 | } | |
1100 | ||
c9be0a36 AK |
1101 | static ssize_t __ref rescan_store(struct sysdev_class *class, |
1102 | struct sysdev_class_attribute *attr, | |
1103 | const char *buf, | |
1e489518 HC |
1104 | size_t count) |
1105 | { | |
1106 | int rc; | |
1107 | ||
1108 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1109 | return rc ? rc : count; |
1110 | } | |
da5aae70 | 1111 | static SYSDEV_CLASS_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1112 | #endif /* CONFIG_HOTPLUG_CPU */ |
1113 | ||
5fbcae57 HC |
1114 | static ssize_t dispatching_show(struct sysdev_class *class, |
1115 | struct sysdev_class_attribute *attr, | |
1116 | char *buf) | |
c10fde0d HC |
1117 | { |
1118 | ssize_t count; | |
1119 | ||
1120 | mutex_lock(&smp_cpu_state_mutex); | |
1121 | count = sprintf(buf, "%d\n", cpu_management); | |
1122 | mutex_unlock(&smp_cpu_state_mutex); | |
1123 | return count; | |
1124 | } | |
1125 | ||
c9be0a36 AK |
1126 | static ssize_t dispatching_store(struct sysdev_class *dev, |
1127 | struct sysdev_class_attribute *attr, | |
1128 | const char *buf, | |
da5aae70 | 1129 | size_t count) |
c10fde0d HC |
1130 | { |
1131 | int val, rc; | |
1132 | char delim; | |
1133 | ||
1134 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
1135 | return -EINVAL; | |
1136 | if (val != 0 && val != 1) | |
1137 | return -EINVAL; | |
1138 | rc = 0; | |
c10fde0d | 1139 | get_online_cpus(); |
0b18d318 | 1140 | mutex_lock(&smp_cpu_state_mutex); |
c10fde0d HC |
1141 | if (cpu_management == val) |
1142 | goto out; | |
1143 | rc = topology_set_cpu_management(val); | |
1144 | if (!rc) | |
1145 | cpu_management = val; | |
1146 | out: | |
c10fde0d | 1147 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1148 | put_online_cpus(); |
c10fde0d HC |
1149 | return rc ? rc : count; |
1150 | } | |
da5aae70 HC |
1151 | static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show, |
1152 | dispatching_store); | |
c10fde0d | 1153 | |
1da177e4 LT |
1154 | static int __init topology_init(void) |
1155 | { | |
1156 | int cpu; | |
fae8b22d | 1157 | int rc; |
2fc2d1e9 HC |
1158 | |
1159 | register_cpu_notifier(&smp_cpu_nb); | |
1da177e4 | 1160 | |
08d07968 | 1161 | #ifdef CONFIG_HOTPLUG_CPU |
da5aae70 | 1162 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_rescan); |
08d07968 HC |
1163 | if (rc) |
1164 | return rc; | |
1165 | #endif | |
da5aae70 | 1166 | rc = sysdev_class_create_file(&cpu_sysdev_class, &attr_dispatching); |
c10fde0d HC |
1167 | if (rc) |
1168 | return rc; | |
08d07968 HC |
1169 | for_each_present_cpu(cpu) { |
1170 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1171 | if (rc) |
1172 | return rc; | |
1da177e4 LT |
1173 | } |
1174 | return 0; | |
1175 | } | |
1da177e4 | 1176 | subsys_initcall(topology_init); |