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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
8b646bd7 3 * SMP related functions
1da177e4 4 *
a53c8fab 5 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
6 * Author(s): Denis Joseph Barrow,
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
8 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 9 *
39ce010d 10 * based on other smp stuff by
1da177e4
LT
11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
12 * (c) 1998 Ingo Molnar
13 *
8b646bd7
MS
14 * The code outside of smp.c uses logical cpu numbers, only smp.c does
15 * the translation of logical to physical cpu ids. All new code that
16 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
17 */
18
395d31d4
MS
19#define KMSG_COMPONENT "cpu"
20#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
f230886b 22#include <linux/workqueue.h>
57c8a661 23#include <linux/memblock.h>
3994a52b 24#include <linux/export.h>
1da177e4 25#include <linux/init.h>
1da177e4 26#include <linux/mm.h>
4e950f6f 27#include <linux/err.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/kernel_stat.h>
1da177e4 30#include <linux/delay.h>
1da177e4 31#include <linux/interrupt.h>
3324e60a 32#include <linux/irqflags.h>
1da177e4 33#include <linux/cpu.h>
5a0e3ad6 34#include <linux/slab.h>
ef8bd77f 35#include <linux/sched/hotplug.h>
68db0cf1 36#include <linux/sched/task_stack.h>
60a0c68d 37#include <linux/crash_dump.h>
00a8f886 38#include <linux/kprobes.h>
cbb870c8 39#include <asm/asm-offsets.h>
1ec2772e 40#include <asm/diag.h>
1e3cab2f
HC
41#include <asm/switch_to.h>
42#include <asm/facility.h>
46b05d26 43#include <asm/ipl.h>
2b67fc46 44#include <asm/setup.h>
1da177e4 45#include <asm/irq.h>
1da177e4 46#include <asm/tlbflush.h>
27f6b416 47#include <asm/vtimer.h>
411ed322 48#include <asm/lowcore.h>
08d07968 49#include <asm/sclp.h>
c742b31c 50#include <asm/vdso.h>
3ab121ab 51#include <asm/debug.h>
4857d4bb 52#include <asm/os_info.h>
a9ae32c3 53#include <asm/sigp.h>
b5f87f15 54#include <asm/idle.h>
916cda1a 55#include <asm/nmi.h>
78c98f90 56#include <asm/stacktrace.h>
38389ec8 57#include <asm/topology.h>
a806170e 58#include "entry.h"
1da177e4 59
8b646bd7
MS
60enum {
61 ec_schedule = 0,
8b646bd7
MS
62 ec_call_function_single,
63 ec_stop_cpu,
11886c19 64 ec_mcck_pending,
8b646bd7 65};
08d07968 66
8b646bd7 67enum {
08d07968
HC
68 CPU_STATE_STANDBY,
69 CPU_STATE_CONFIGURED,
70};
71
2f859d0d
HC
72static DEFINE_PER_CPU(struct cpu *, cpu_device);
73
8b646bd7 74struct pcpu {
c667aeac 75 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 76 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 77 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
78 signed char state; /* physical cpu state */
79 signed char polarization; /* physical polarization */
8b646bd7
MS
80 u16 address; /* physical cpu address */
81};
82
d08d9430 83static u8 boot_core_type;
8b646bd7
MS
84static struct pcpu pcpu_devices[NR_CPUS];
85
10ad34bc
MS
86unsigned int smp_cpu_mt_shift;
87EXPORT_SYMBOL(smp_cpu_mt_shift);
88
89unsigned int smp_cpu_mtid;
90EXPORT_SYMBOL(smp_cpu_mtid);
91
1a36a39e
MS
92#ifdef CONFIG_CRASH_DUMP
93__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
94#endif
95
10ad34bc
MS
96static unsigned int smp_max_threads __initdata = -1U;
97
98static int __init early_nosmt(char *s)
99{
100 smp_max_threads = 1;
101 return 0;
102}
103early_param("nosmt", early_nosmt);
104
105static int __init early_smt(char *s)
106{
107 get_option(&s, &smp_max_threads);
108 return 0;
109}
110early_param("smt", early_smt);
111
50ab9a9a
HC
112/*
113 * The smp_cpu_state_mutex must be held when changing the state or polarization
114 * member of a pcpu data structure within the pcpu_devices arreay.
115 */
dbd70fb4 116DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 117
8b646bd7
MS
118/*
119 * Signal processor helper functions.
120 */
1a36a39e 121static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 122{
8b646bd7 123 int cc;
5c0b912e 124
8b646bd7 125 while (1) {
c5e3acd6 126 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 127 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
128 return cc;
129 cpu_relax();
5c0b912e 130 }
5c0b912e
HC
131}
132
8b646bd7 133static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 134{
8b646bd7
MS
135 int cc, retry;
136
137 for (retry = 0; ; retry++) {
c5e3acd6 138 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 139 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
140 break;
141 if (retry >= 3)
142 udelay(10);
143 }
144 return cc;
145}
146
147static inline int pcpu_stopped(struct pcpu *pcpu)
148{
3f649ab7 149 u32 status;
c5e3acd6 150
a9ae32c3 151 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 152 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 153 return 0;
c5e3acd6 154 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
155}
156
157static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 158{
a9ae32c3 159 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 160 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 161 return 1;
524b24ad
HC
162 /* Status stored condition code is equivalent to cpu not running. */
163 return 0;
a93b8ec1
HC
164}
165
1943f53c 166/*
8b646bd7 167 * Find struct pcpu by cpu address.
1943f53c 168 */
10ad34bc 169static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
170{
171 int cpu;
172
8b646bd7
MS
173 for_each_cpu(cpu, mask)
174 if (pcpu_devices[cpu].address == address)
175 return pcpu_devices + cpu;
176 return NULL;
177}
178
179static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
180{
181 int order;
182
dea24190
HC
183 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
184 return;
185 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 186 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
187 pcpu_sigp_retry(pcpu, order, 0);
188}
189
e2741f17 190static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 191{
ce3dc447 192 unsigned long async_stack, nodat_stack;
c667aeac 193 struct lowcore *lc;
8b646bd7
MS
194
195 if (pcpu != &pcpu_devices[0]) {
c667aeac 196 pcpu->lowcore = (struct lowcore *)
8b646bd7 197 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
32ce55a6 198 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
ce3dc447 199 if (!pcpu->lowcore || !nodat_stack)
8b646bd7 200 goto out;
2f859d0d 201 } else {
ce3dc447 202 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
1943f53c 203 }
ce3dc447
MS
204 async_stack = stack_alloc();
205 if (!async_stack)
206 goto out;
8b646bd7
MS
207 lc = pcpu->lowcore;
208 memcpy(lc, &S390_lowcore, 512);
209 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
ce3dc447
MS
210 lc->async_stack = async_stack + STACK_INIT_OFFSET;
211 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET;
8b646bd7 212 lc->cpu_nr = cpu;
6c8cd5bb 213 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 214 lc->spinlock_index = 0;
f19fbd5e 215 lc->br_r1_trampoline = 0x07f1; /* br %r1 */
0b38b5e1
SS
216 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW);
217 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW);
6c81511c 218 if (nmi_alloc_per_cpu(lc))
ce3dc447 219 goto out_async;
6c81511c
MS
220 if (vdso_alloc_per_cpu(lc))
221 goto out_mcesa;
8b646bd7 222 lowcore_ptr[cpu] = lc;
a9ae32c3 223 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7 224 return 0;
6c81511c
MS
225
226out_mcesa:
227 nmi_free_per_cpu(lc);
ce3dc447
MS
228out_async:
229 stack_free(async_stack);
8b646bd7
MS
230out:
231 if (pcpu != &pcpu_devices[0]) {
32ce55a6 232 free_pages(nodat_stack, THREAD_SIZE_ORDER);
8b646bd7
MS
233 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
234 }
235 return -ENOMEM;
1943f53c
MH
236}
237
8b646bd7 238static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 239{
ce3dc447
MS
240 unsigned long async_stack, nodat_stack, lowcore;
241
242 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
243 async_stack = pcpu->lowcore->async_stack - STACK_INIT_OFFSET;
244 lowcore = (unsigned long) pcpu->lowcore;
245
a9ae32c3 246 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 247 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 248 vdso_free_per_cpu(pcpu->lowcore);
6c81511c 249 nmi_free_per_cpu(pcpu->lowcore);
ce3dc447 250 stack_free(async_stack);
2f859d0d
HC
251 if (pcpu == &pcpu_devices[0])
252 return;
32ce55a6 253 free_pages(nodat_stack, THREAD_SIZE_ORDER);
ce3dc447 254 free_pages(lowcore, LC_ORDER);
8b646bd7
MS
255}
256
257static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
258{
c667aeac 259 struct lowcore *lc = pcpu->lowcore;
8b646bd7 260
64f31d58 261 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 262 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 263 lc->cpu_nr = cpu;
6c8cd5bb 264 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 265 lc->spinlock_index = 0;
8b646bd7
MS
266 lc->percpu_offset = __per_cpu_offset[cpu];
267 lc->kernel_asce = S390_lowcore.kernel_asce;
a2308c11 268 lc->user_asce = S390_lowcore.kernel_asce;
8b646bd7 269 lc->machine_flags = S390_lowcore.machine_flags;
152e9b86
MS
270 lc->user_timer = lc->system_timer =
271 lc->steal_timer = lc->avg_steal_timer = 0;
8b646bd7 272 __ctl_store(lc->cregs_save_area, 0, 15);
a2308c11
HC
273 lc->cregs_save_area[1] = lc->kernel_asce;
274 lc->cregs_save_area[7] = lc->vdso_asce;
8b646bd7
MS
275 save_access_regs((unsigned int *) lc->access_regs_save_area);
276 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
cf148998
MS
277 sizeof(lc->stfle_fac_list));
278 memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list,
279 sizeof(lc->alt_stfle_fac_list));
b96f7d88 280 arch_spin_lock_setup(cpu);
8b646bd7
MS
281}
282
283static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
284{
c667aeac 285 struct lowcore *lc = pcpu->lowcore;
8b646bd7 286
dc7ee00d
MS
287 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
288 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 289 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
290 lc->lpp = LPP_MAGIC;
291 lc->current_pid = tsk->pid;
90c53e65 292 lc->user_timer = tsk->thread.user_timer;
b7662eef 293 lc->guest_timer = tsk->thread.guest_timer;
90c53e65 294 lc->system_timer = tsk->thread.system_timer;
b7662eef
CB
295 lc->hardirq_timer = tsk->thread.hardirq_timer;
296 lc->softirq_timer = tsk->thread.softirq_timer;
8b646bd7
MS
297 lc->steal_timer = 0;
298}
299
300static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
301{
c667aeac 302 struct lowcore *lc = pcpu->lowcore;
8b646bd7 303
ce3dc447 304 lc->restart_stack = lc->nodat_stack;
8b646bd7
MS
305 lc->restart_fn = (unsigned long) func;
306 lc->restart_data = (unsigned long) data;
307 lc->restart_source = -1UL;
a9ae32c3 308 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
309}
310
311/*
312 * Call function via PSW restart on pcpu and stop the current cpu.
313 */
ce3dc447
MS
314static void __pcpu_delegate(void (*func)(void*), void *data)
315{
316 func(data); /* should not return */
317}
318
ac1256f8
VG
319static void __no_sanitize_address pcpu_delegate(struct pcpu *pcpu,
320 void (*func)(void *),
321 void *data, unsigned long stack)
8b646bd7 322{
c667aeac 323 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 324 unsigned long source_cpu = stap();
8b646bd7 325
ce3dc447 326 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
fbe76568 327 if (pcpu->address == source_cpu)
ce3dc447 328 CALL_ON_STACK(__pcpu_delegate, stack, 2, func, data);
8b646bd7 329 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 330 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 331 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
332 mem_assign_absolute(lc->restart_stack, stack);
333 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
334 mem_assign_absolute(lc->restart_data, (unsigned long) data);
335 mem_assign_absolute(lc->restart_source, source_cpu);
d768bd89 336 __bpon();
8b646bd7 337 asm volatile(
eb546195 338 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 339 " brc 2,0b # busy, try again\n"
eb546195 340 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 341 " brc 2,1b # busy, try again\n"
fbe76568 342 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
343 "K" (SIGP_RESTART), "K" (SIGP_STOP)
344 : "0", "1", "cc");
8b646bd7
MS
345 for (;;) ;
346}
347
10ad34bc
MS
348/*
349 * Enable additional logical cpus for multi-threading.
350 */
351static int pcpu_set_smt(unsigned int mtid)
352{
10ad34bc
MS
353 int cc;
354
355 if (smp_cpu_mtid == mtid)
356 return 0;
80a60f6e 357 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
358 if (cc == 0) {
359 smp_cpu_mtid = mtid;
360 smp_cpu_mt_shift = 0;
361 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
362 smp_cpu_mt_shift++;
363 pcpu_devices[0].address = stap();
364 }
365 return cc;
366}
367
8b646bd7
MS
368/*
369 * Call function on an online CPU.
370 */
371void smp_call_online_cpu(void (*func)(void *), void *data)
372{
373 struct pcpu *pcpu;
374
375 /* Use the current cpu if it is online. */
376 pcpu = pcpu_find_address(cpu_online_mask, stap());
377 if (!pcpu)
378 /* Use the first online cpu. */
379 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
380 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
381}
382
383/*
384 * Call function on the ipl CPU.
385 */
386void smp_call_ipl_cpu(void (*func)(void *), void *data)
387{
60f1bf29
DH
388 struct lowcore *lc = pcpu_devices->lowcore;
389
390 if (pcpu_devices[0].address == stap())
391 lc = &S390_lowcore;
392
c6da39f2 393 pcpu_delegate(&pcpu_devices[0], func, data,
60f1bf29 394 lc->nodat_stack);
8b646bd7
MS
395}
396
397int smp_find_processor_id(u16 address)
398{
399 int cpu;
400
401 for_each_present_cpu(cpu)
402 if (pcpu_devices[cpu].address == address)
403 return cpu;
404 return -1;
2c2df118
HC
405}
406
11886c19
SS
407void schedule_mcck_handler(void)
408{
409 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending);
410}
411
8ebf6da9 412bool notrace arch_vcpu_is_preempted(int cpu)
85ac7ca5 413{
760928c0
CB
414 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
415 return false;
416 if (pcpu_running(pcpu_devices + cpu))
417 return false;
418 return true;
8b646bd7 419}
760928c0 420EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 421
8ebf6da9 422void notrace smp_yield_cpu(int cpu)
85ac7ca5 423{
1b68ac86
HC
424 if (!MACHINE_HAS_DIAG9C)
425 return;
426 diag_stat_inc_norecursion(DIAG_STAT_X09C);
427 asm volatile("diag %0,0,0x9c"
428 : : "d" (pcpu_devices[cpu].address));
8b646bd7
MS
429}
430
431/*
432 * Send cpus emergency shutdown signal. This gives the cpus the
433 * opportunity to complete outstanding interrupts.
434 */
00a8f886 435void notrace smp_emergency_stop(void)
8b646bd7 436{
00a8f886 437 cpumask_t cpumask;
8b646bd7
MS
438 u64 end;
439 int cpu;
440
00a8f886
MS
441 cpumask_copy(&cpumask, cpu_online_mask);
442 cpumask_clear_cpu(smp_processor_id(), &cpumask);
443
1aae0560 444 end = get_tod_clock() + (1000000UL << 12);
00a8f886 445 for_each_cpu(cpu, &cpumask) {
8b646bd7
MS
446 struct pcpu *pcpu = pcpu_devices + cpu;
447 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
448 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
449 0, NULL) == SIGP_CC_BUSY &&
1aae0560 450 get_tod_clock() < end)
8b646bd7
MS
451 cpu_relax();
452 }
1aae0560 453 while (get_tod_clock() < end) {
00a8f886 454 for_each_cpu(cpu, &cpumask)
8b646bd7 455 if (pcpu_stopped(pcpu_devices + cpu))
00a8f886
MS
456 cpumask_clear_cpu(cpu, &cpumask);
457 if (cpumask_empty(&cpumask))
8b646bd7 458 break;
85ac7ca5 459 cpu_relax();
8b646bd7 460 }
85ac7ca5 461}
00a8f886 462NOKPROBE_SYMBOL(smp_emergency_stop);
85ac7ca5 463
8b646bd7
MS
464/*
465 * Stop all cpus but the current one.
466 */
677d7623 467void smp_send_stop(void)
1da177e4 468{
85ac7ca5 469 int cpu;
1da177e4 470
677d7623 471 /* Disable all interrupts/machine checks */
e258d719 472 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 473 trace_hardirqs_off();
1da177e4 474
3ab121ab 475 debug_set_critical();
85ac7ca5 476
8b646bd7 477 if (oops_in_progress)
00a8f886 478 smp_emergency_stop();
1da177e4 479
85ac7ca5 480 /* stop all processors */
00a8f886
MS
481 for_each_online_cpu(cpu) {
482 if (cpu == smp_processor_id())
483 continue;
484 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
485 while (!pcpu_stopped(pcpu_devices + cpu))
c6b5b847
HC
486 cpu_relax();
487 }
488}
489
1da177e4
LT
490/*
491 * This is the main routine where commands issued by other
492 * cpus are handled.
493 */
9acf73b7 494static void smp_handle_ext_call(void)
1da177e4 495{
39ce010d 496 unsigned long bits;
1da177e4 497
9acf73b7
HC
498 /* handle bit signal external calls */
499 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
500 if (test_bit(ec_stop_cpu, &bits))
501 smp_stop_cpu();
184748cc
PZ
502 if (test_bit(ec_schedule, &bits))
503 scheduler_ipi();
ca9fc75a
HC
504 if (test_bit(ec_call_function_single, &bits))
505 generic_smp_call_function_single_interrupt();
11886c19
SS
506 if (test_bit(ec_mcck_pending, &bits))
507 s390_handle_mcck();
9acf73b7 508}
85ac7ca5 509
9acf73b7
HC
510static void do_ext_call_interrupt(struct ext_code ext_code,
511 unsigned int param32, unsigned long param64)
512{
513 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
514 smp_handle_ext_call();
1da177e4
LT
515}
516
630cd046 517void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
518{
519 int cpu;
520
630cd046 521 for_each_cpu(cpu, mask)
b6ed49e0 522 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
523}
524
525void arch_send_call_function_single_ipi(int cpu)
526{
8b646bd7 527 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
528}
529
1da177e4
LT
530/*
531 * this function sends a 'reschedule' IPI to another CPU.
532 * it goes straight through and wastes no time serializing
533 * anything. Worst case is that we lose a reschedule ...
534 */
535void smp_send_reschedule(int cpu)
536{
8b646bd7 537 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
538}
539
540/*
541 * parameter area for the set/clear control bit callbacks
542 */
94c12cc7 543struct ec_creg_mask_parms {
8b646bd7
MS
544 unsigned long orval;
545 unsigned long andval;
546 int cr;
94c12cc7 547};
1da177e4
LT
548
549/*
550 * callback for setting/clearing control bits
551 */
39ce010d
HC
552static void smp_ctl_bit_callback(void *info)
553{
94c12cc7 554 struct ec_creg_mask_parms *pp = info;
1da177e4 555 unsigned long cregs[16];
39ce010d 556
94c12cc7 557 __ctl_store(cregs, 0, 15);
8b646bd7 558 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 559 __ctl_load(cregs, 0, 15);
1da177e4
LT
560}
561
562/*
563 * Set a bit in a control register of all cpus
564 */
94c12cc7
MS
565void smp_ctl_set_bit(int cr, int bit)
566{
8b646bd7 567 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 568
15c8b6c1 569 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 570}
39ce010d 571EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
572
573/*
574 * Clear a bit in a control register of all cpus
575 */
94c12cc7
MS
576void smp_ctl_clear_bit(int cr, int bit)
577{
8b646bd7 578 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 579
15c8b6c1 580 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 581}
39ce010d 582EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 583
bf28a597 584#ifdef CONFIG_CRASH_DUMP
411ed322 585
1af135a1
HC
586int smp_store_status(int cpu)
587{
1a36a39e
MS
588 struct pcpu *pcpu = pcpu_devices + cpu;
589 unsigned long pa;
1af135a1 590
1a36a39e
MS
591 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
592 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
593 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1 594 return -EIO;
916cda1a 595 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
1af135a1 596 return 0;
916cda1a
MS
597 pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
598 if (MACHINE_HAS_GS)
599 pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
1a36a39e
MS
600 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
601 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
602 return -EIO;
1af135a1
HC
603 return 0;
604}
605
10ad34bc
MS
606/*
607 * Collect CPU state of the previous, crashed system.
608 * There are four cases:
609 * 1) standard zfcp dump
610 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
611 * The state for all CPUs except the boot CPU needs to be collected
612 * with sigp stop-and-store-status. The boot CPU state is located in
613 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 614 * will copy the boot CPU state from the HSA.
10ad34bc
MS
615 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
616 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
617 * The state for all CPUs except the boot CPU needs to be collected
618 * with sigp stop-and-store-status. The firmware or the boot-loader
619 * stored the registers of the boot CPU in the absolute lowcore in the
620 * memory of the old system.
621 * 3) kdump and the old kernel did not store the CPU state,
622 * or stand-alone kdump for DASD
623 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
624 * The state for all CPUs except the boot CPU needs to be collected
625 * with sigp stop-and-store-status. The kexec code or the boot-loader
626 * stored the registers of the boot CPU in the memory of the old system.
627 * 4) kdump and the old kernel stored the CPU state
628 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
629 * This case does not exist for s390 anymore, setup_arch explicitly
630 * deactivates the elfcorehdr= kernel parameter
10ad34bc 631 */
1a2c5840 632static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
633 bool is_boot_cpu, unsigned long page)
634{
635 __vector128 *vxrs = (__vector128 *) page;
636
637 if (is_boot_cpu)
638 vxrs = boot_cpu_vector_save_area;
639 else
640 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 641 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
642}
643
1a2c5840 644static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
645 bool is_boot_cpu, unsigned long page)
646{
647 void *regs = (void *) page;
648
649 if (is_boot_cpu)
650 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
651 else
652 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 653 save_area_add_regs(sa, regs);
1a36a39e
MS
654}
655
1592a8e4 656void __init smp_save_dump_cpus(void)
10ad34bc 657{
1a2c5840
MS
658 int addr, boot_cpu_addr, max_cpu_addr;
659 struct save_area *sa;
1a36a39e 660 unsigned long page;
1592a8e4 661 bool is_boot_cpu;
10ad34bc 662
10ad34bc
MS
663 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
664 /* No previous system present, normal boot. */
665 return;
1a36a39e 666 /* Allocate a page as dumping area for the store status sigps */
0ba9e6ed
MR
667 page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31);
668 if (!page)
8a7f97b9 669 panic("ERROR: Failed to allocate %lx bytes below %lx\n",
0ba9e6ed
MR
670 PAGE_SIZE, 1UL << 31);
671
10ad34bc 672 /* Set multi-threading state to the previous system. */
37c5f6c8 673 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 674 boot_cpu_addr = stap();
1a2c5840
MS
675 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
676 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 677 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
678 SIGP_CC_NOT_OPERATIONAL)
679 continue;
1592a8e4 680 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
681 /* Allocate save area */
682 sa = save_area_alloc(is_boot_cpu);
683 if (!sa)
684 panic("could not allocate memory for save area\n");
1a36a39e
MS
685 if (MACHINE_HAS_VX)
686 /* Get the vector registers */
1a2c5840 687 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
688 /*
689 * For a zfcp dump OLDMEM_BASE == NULL and the registers
690 * of the boot CPU are stored in the HSA. To retrieve
691 * these registers an SCLP request is required which is
692 * done by drivers/s390/char/zcore.c:init_cpu_info()
693 */
694 if (!is_boot_cpu || OLDMEM_BASE)
695 /* Get the CPU registers */
1a2c5840 696 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 697 }
1a36a39e 698 memblock_free(page, PAGE_SIZE);
a80313ff 699 diag_dma_ops.diag308_reset();
1592a8e4 700 pcpu_set_smt(0);
1af135a1 701}
1a36a39e 702#endif /* CONFIG_CRASH_DUMP */
08d07968 703
50ab9a9a
HC
704void smp_cpu_set_polarization(int cpu, int val)
705{
706 pcpu_devices[cpu].polarization = val;
707}
708
709int smp_cpu_get_polarization(int cpu)
710{
711 return pcpu_devices[cpu].polarization;
712}
713
42d211a1
AG
714int smp_cpu_get_cpu_address(int cpu)
715{
716 return pcpu_devices[cpu].address;
717}
718
af51160e 719static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 720{
8b646bd7 721 static int use_sigp_detection;
8b646bd7
MS
722 int address;
723
af51160e 724 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 725 use_sigp_detection = 1;
e7086eb1 726 for (address = 0;
d08d9430 727 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 728 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 729 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 730 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 731 continue;
d08d9430 732 info->core[info->configured].core_id =
10ad34bc 733 address >> smp_cpu_mt_shift;
8b646bd7
MS
734 info->configured++;
735 }
736 info->combined = info->configured;
08d07968 737 }
08d07968
HC
738}
739
e2741f17 740static int smp_add_present_cpu(int cpu);
8b646bd7 741
72a81ad9
HC
742static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
743 bool configured, bool early)
08d07968 744{
8b646bd7 745 struct pcpu *pcpu;
72a81ad9 746 int cpu, nr, i;
10ad34bc 747 u16 address;
08d07968 748
8b646bd7 749 nr = 0;
72a81ad9
HC
750 if (sclp.has_core_type && core->type != boot_core_type)
751 return nr;
752 cpu = cpumask_first(avail);
753 address = core->core_id << smp_cpu_mt_shift;
754 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) {
755 if (pcpu_find_address(cpu_present_mask, address + i))
8b646bd7 756 continue;
72a81ad9
HC
757 pcpu = pcpu_devices + cpu;
758 pcpu->address = address + i;
759 if (configured)
760 pcpu->state = CPU_STATE_CONFIGURED;
761 else
762 pcpu->state = CPU_STATE_STANDBY;
763 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
764 set_cpu_present(cpu, true);
765 if (!early && smp_add_present_cpu(cpu) != 0)
766 set_cpu_present(cpu, false);
767 else
768 nr++;
769 cpumask_clear_cpu(cpu, avail);
770 cpu = cpumask_next(cpu, avail);
771 }
772 return nr;
773}
774
775static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
776{
777 struct sclp_core_entry *core;
778 cpumask_t avail;
779 bool configured;
780 u16 core_id;
781 int nr, i;
782
783 nr = 0;
784 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
785 /*
786 * Add IPL core first (which got logical CPU number 0) to make sure
787 * that all SMT threads get subsequent logical CPU numbers.
788 */
789 if (early) {
790 core_id = pcpu_devices[0].address >> smp_cpu_mt_shift;
791 for (i = 0; i < info->configured; i++) {
792 core = &info->core[i];
793 if (core->core_id == core_id) {
794 nr += smp_add_core(core, &avail, true, early);
10ad34bc 795 break;
72a81ad9 796 }
10ad34bc 797 }
8b646bd7 798 }
72a81ad9
HC
799 for (i = 0; i < info->combined; i++) {
800 configured = i < info->configured;
801 nr += smp_add_core(&info->core[i], &avail, configured, early);
802 }
8b646bd7 803 return nr;
1da177e4
LT
804}
805
af51160e 806void __init smp_detect_cpus(void)
48483b32 807{
10ad34bc 808 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 809 struct sclp_core_info *info;
10ad34bc 810 u16 address;
48483b32 811
10ad34bc 812 /* Get CPU information */
eb31d559 813 info = memblock_alloc(sizeof(*info), 8);
8a7f97b9
MR
814 if (!info)
815 panic("%s: Failed to allocate %zu bytes align=0x%x\n",
816 __func__, sizeof(*info), 8);
af51160e 817 smp_get_core_info(info, 1);
10ad34bc 818 /* Find boot CPU type */
d08d9430 819 if (sclp.has_core_type) {
10ad34bc
MS
820 address = stap();
821 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 822 if (info->core[cpu].core_id == address) {
10ad34bc 823 /* The boot cpu dictates the cpu type. */
d08d9430 824 boot_core_type = info->core[cpu].type;
10ad34bc
MS
825 break;
826 }
827 if (cpu >= info->combined)
828 panic("Could not find boot CPU type");
48483b32 829 }
10ad34bc 830
10ad34bc 831 /* Set multi-threading state for the current system */
d08d9430 832 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
833 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
834 pcpu_set_smt(mtid);
835
836 /* Print number of CPUs */
8b646bd7 837 c_cpus = s_cpus = 0;
48483b32 838 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
839 if (sclp.has_core_type &&
840 info->core[cpu].type != boot_core_type)
48483b32 841 continue;
10ad34bc
MS
842 if (cpu < info->configured)
843 c_cpus += smp_cpu_mtid + 1;
844 else
845 s_cpus += smp_cpu_mtid + 1;
48483b32 846 }
395d31d4 847 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
848
849 /* Add CPUs present at boot */
9d40d2e3 850 get_online_cpus();
72a81ad9 851 __smp_rescan_cpus(info, true);
9d40d2e3 852 put_online_cpus();
af51160e 853 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
854}
855
ce3dc447 856static void smp_init_secondary(void)
1da177e4 857{
1887aa07
MS
858 int cpu = smp_processor_id();
859
9e8df6da
VG
860 S390_lowcore.last_update_clock = get_tod_clock();
861 restore_access_regs(S390_lowcore.access_regs_save_area);
a2308c11
HC
862 set_cpu_flag(CIF_ASCE_PRIMARY);
863 set_cpu_flag(CIF_ASCE_SECONDARY);
39ce010d 864 cpu_init();
5bfb5d69 865 preempt_disable();
39ce010d 866 init_cpu_timer();
b5f87f15 867 vtime_init();
29b08d2b 868 pfault_init();
52aeda7a 869 notify_cpu_starting(cpu);
1887aa07
MS
870 if (topology_cpu_dedicated(cpu))
871 set_cpu_flag(CIF_DEDICATED_CPU);
872 else
873 clear_cpu_flag(CIF_DEDICATED_CPU);
52aeda7a
AG
874 set_cpu_online(cpu, true);
875 update_cpu_masks();
93f3b2ee 876 inc_irq_stat(CPU_RST);
1da177e4 877 local_irq_enable();
fc6d73d6 878 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
879}
880
ce3dc447
MS
881/*
882 * Activate a secondary processor.
883 */
9e8df6da 884static void __no_sanitize_address smp_start_secondary(void *cpuvoid)
ce3dc447 885{
ce3dc447
MS
886 S390_lowcore.restart_stack = (unsigned long) restart_stack;
887 S390_lowcore.restart_fn = (unsigned long) do_restart;
888 S390_lowcore.restart_data = 0;
889 S390_lowcore.restart_source = -1UL;
ce3dc447
MS
890 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
891 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
7bcaad1f 892 CALL_ON_STACK_NORETURN(smp_init_secondary, S390_lowcore.kernel_stack);
ce3dc447
MS
893}
894
1da177e4 895/* Upping and downing of CPUs */
e2741f17 896int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 897{
8b646bd7 898 struct pcpu *pcpu;
10ad34bc 899 int base, i, rc;
1da177e4 900
8b646bd7
MS
901 pcpu = pcpu_devices + cpu;
902 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 903 return -EIO;
5423145f 904 base = smp_get_base_cpu(cpu);
10ad34bc
MS
905 for (i = 0; i <= smp_cpu_mtid; i++) {
906 if (base + i < nr_cpu_ids)
907 if (cpu_online(base + i))
908 break;
909 }
910 /*
911 * If this is the first CPU of the core to get online
912 * do an initial CPU reset.
913 */
914 if (i > smp_cpu_mtid &&
915 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 916 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 917 return -EIO;
e80e7813 918
8b646bd7
MS
919 rc = pcpu_alloc_lowcore(pcpu, cpu);
920 if (rc)
921 return rc;
922 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 923 pcpu_attach_task(pcpu, tidle);
8b646bd7 924 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 925 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 926 while (!cpu_online(cpu))
1da177e4
LT
927 cpu_relax();
928 return 0;
929}
930
d80512f8 931static unsigned int setup_possible_cpus __initdata;
255acee7 932
d80512f8
HC
933static int __init _setup_possible_cpus(char *s)
934{
935 get_option(&s, &setup_possible_cpus);
37a33026
HC
936 return 0;
937}
d80512f8 938early_param("possible_cpus", _setup_possible_cpus);
37a33026 939
39ce010d 940int __cpu_disable(void)
1da177e4 941{
8b646bd7 942 unsigned long cregs[16];
1da177e4 943
9acf73b7
HC
944 /* Handle possible pending IPIs */
945 smp_handle_ext_call();
8b646bd7 946 set_cpu_online(smp_processor_id(), false);
52aeda7a 947 update_cpu_masks();
8b646bd7 948 /* Disable pseudo page faults on this cpu. */
29b08d2b 949 pfault_fini();
8b646bd7
MS
950 /* Disable interrupt sources via control register. */
951 __ctl_store(cregs, 0, 15);
952 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
953 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
954 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
955 __ctl_load(cregs, 0, 15);
fe0f4976 956 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
957 return 0;
958}
959
39ce010d 960void __cpu_die(unsigned int cpu)
1da177e4 961{
8b646bd7
MS
962 struct pcpu *pcpu;
963
1da177e4 964 /* Wait until target cpu is down */
8b646bd7
MS
965 pcpu = pcpu_devices + cpu;
966 while (!pcpu_stopped(pcpu))
1da177e4 967 cpu_relax();
8b646bd7 968 pcpu_free_lowcore(pcpu);
1b948d6c 969 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 970 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
971}
972
b456d94a 973void __noreturn cpu_die(void)
1da177e4
LT
974{
975 idle_task_exit();
d768bd89 976 __bpon();
a9ae32c3 977 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 978 for (;;) ;
1da177e4
LT
979}
980
d80512f8
HC
981void __init smp_fill_possible_mask(void)
982{
9747bc47 983 unsigned int possible, sclp_max, cpu;
d80512f8 984
3a9f3fe6
DH
985 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
986 sclp_max = min(smp_max_threads, sclp_max);
61282aff 987 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 988 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 989 possible = min(possible, sclp_max);
d80512f8
HC
990 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
991 set_cpu_possible(cpu, true);
992}
993
1da177e4
LT
994void __init smp_prepare_cpus(unsigned int max_cpus)
995{
39ce010d 996 /* request the 0x1201 emergency signal external interrupt */
1dad093b 997 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 998 panic("Couldn't request external interrupt 0x1201");
d98e19cc 999 /* request the 0x1202 external call external interrupt */
1dad093b 1000 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 1001 panic("Couldn't request external interrupt 0x1202");
1da177e4
LT
1002}
1003
ea1f4eec 1004void __init smp_prepare_boot_cpu(void)
1da177e4 1005{
8b646bd7
MS
1006 struct pcpu *pcpu = pcpu_devices;
1007
0861b5a7 1008 WARN_ON(!cpu_present(0) || !cpu_online(0));
8b646bd7 1009 pcpu->state = CPU_STATE_CONFIGURED;
c667aeac 1010 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 1011 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 1012 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1da177e4
LT
1013}
1014
ea1f4eec 1015void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 1016{
1da177e4
LT
1017}
1018
02beaccc
HC
1019void __init smp_setup_processor_id(void)
1020{
0861b5a7 1021 pcpu_devices[0].address = stap();
02beaccc 1022 S390_lowcore.cpu_nr = 0;
6c8cd5bb 1023 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
b96f7d88 1024 S390_lowcore.spinlock_index = 0;
02beaccc
HC
1025}
1026
1da177e4
LT
1027/*
1028 * the frequency of the profiling timer can be changed
1029 * by writing a multiplier value into /proc/profile.
1030 *
1031 * usually you want to run this on all CPUs ;)
1032 */
1033int setup_profiling_timer(unsigned int multiplier)
1034{
39ce010d 1035 return 0;
1da177e4
LT
1036}
1037
8a25a2fd 1038static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 1039 struct device_attribute *attr, char *buf)
08d07968
HC
1040{
1041 ssize_t count;
1042
1043 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1044 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
1045 mutex_unlock(&smp_cpu_state_mutex);
1046 return count;
1047}
1048
8a25a2fd 1049static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
1050 struct device_attribute *attr,
1051 const char *buf, size_t count)
08d07968 1052{
8b646bd7 1053 struct pcpu *pcpu;
10ad34bc 1054 int cpu, val, rc, i;
08d07968
HC
1055 char delim;
1056
1057 if (sscanf(buf, "%d %c", &val, &delim) != 1)
1058 return -EINVAL;
1059 if (val != 0 && val != 1)
1060 return -EINVAL;
9d40d2e3 1061 get_online_cpus();
0b18d318 1062 mutex_lock(&smp_cpu_state_mutex);
08d07968 1063 rc = -EBUSY;
2c2df118 1064 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 1065 cpu = dev->id;
5423145f 1066 cpu = smp_get_base_cpu(cpu);
10ad34bc 1067 if (cpu == 0)
08d07968 1068 goto out;
10ad34bc
MS
1069 for (i = 0; i <= smp_cpu_mtid; i++)
1070 if (cpu_online(cpu + i))
1071 goto out;
8b646bd7 1072 pcpu = pcpu_devices + cpu;
08d07968
HC
1073 rc = 0;
1074 switch (val) {
1075 case 0:
8b646bd7
MS
1076 if (pcpu->state != CPU_STATE_CONFIGURED)
1077 break;
d08d9430 1078 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1079 if (rc)
1080 break;
10ad34bc
MS
1081 for (i = 0; i <= smp_cpu_mtid; i++) {
1082 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1083 continue;
1084 pcpu[i].state = CPU_STATE_STANDBY;
1085 smp_cpu_set_polarization(cpu + i,
1086 POLARIZATION_UNKNOWN);
1087 }
8b646bd7 1088 topology_expect_change();
08d07968
HC
1089 break;
1090 case 1:
8b646bd7
MS
1091 if (pcpu->state != CPU_STATE_STANDBY)
1092 break;
d08d9430 1093 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1094 if (rc)
1095 break;
10ad34bc
MS
1096 for (i = 0; i <= smp_cpu_mtid; i++) {
1097 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1098 continue;
1099 pcpu[i].state = CPU_STATE_CONFIGURED;
1100 smp_cpu_set_polarization(cpu + i,
1101 POLARIZATION_UNKNOWN);
1102 }
8b646bd7 1103 topology_expect_change();
08d07968
HC
1104 break;
1105 default:
1106 break;
1107 }
1108out:
08d07968 1109 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1110 put_online_cpus();
08d07968
HC
1111 return rc ? rc : count;
1112}
8a25a2fd 1113static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968 1114
8a25a2fd
KS
1115static ssize_t show_cpu_address(struct device *dev,
1116 struct device_attribute *attr, char *buf)
08d07968 1117{
8b646bd7 1118 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1119}
8a25a2fd 1120static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1121
08d07968 1122static struct attribute *cpu_common_attrs[] = {
8a25a2fd 1123 &dev_attr_configure.attr,
8a25a2fd 1124 &dev_attr_address.attr,
08d07968
HC
1125 NULL,
1126};
1127
1128static struct attribute_group cpu_common_attr_group = {
1129 .attrs = cpu_common_attrs,
1130};
1da177e4 1131
08d07968 1132static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1133 &dev_attr_idle_count.attr,
1134 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1135 NULL,
1136};
1137
08d07968
HC
1138static struct attribute_group cpu_online_attr_group = {
1139 .attrs = cpu_online_attrs,
fae8b22d
HC
1140};
1141
dfbbd86a 1142static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1143{
2f859d0d 1144 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1145
dfbbd86a
SAS
1146 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1147}
1148static int smp_cpu_pre_down(unsigned int cpu)
1149{
1150 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1151
1152 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1153 return 0;
2fc2d1e9
HC
1154}
1155
e2741f17 1156static int smp_add_present_cpu(int cpu)
08d07968 1157{
96619fc1
HC
1158 struct device *s;
1159 struct cpu *c;
08d07968
HC
1160 int rc;
1161
96619fc1
HC
1162 c = kzalloc(sizeof(*c), GFP_KERNEL);
1163 if (!c)
1164 return -ENOMEM;
2f859d0d 1165 per_cpu(cpu_device, cpu) = c;
96619fc1 1166 s = &c->dev;
08d07968
HC
1167 c->hotpluggable = 1;
1168 rc = register_cpu(c, cpu);
1169 if (rc)
1170 goto out;
1171 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1172 if (rc)
1173 goto out_cpu;
83a24e32
HC
1174 rc = topology_cpu_init(c);
1175 if (rc)
1176 goto out_topology;
1177 return 0;
1178
1179out_topology:
08d07968
HC
1180 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1181out_cpu:
08d07968 1182 unregister_cpu(c);
08d07968
HC
1183out:
1184 return rc;
1185}
1186
67060d9c 1187int __ref smp_rescan_cpus(void)
08d07968 1188{
d08d9430 1189 struct sclp_core_info *info;
8b646bd7 1190 int nr;
08d07968 1191
af51160e 1192 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1193 if (!info)
1194 return -ENOMEM;
af51160e 1195 smp_get_core_info(info, 0);
9d40d2e3 1196 get_online_cpus();
0b18d318 1197 mutex_lock(&smp_cpu_state_mutex);
72a81ad9 1198 nr = __smp_rescan_cpus(info, false);
08d07968 1199 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1200 put_online_cpus();
8b646bd7
MS
1201 kfree(info);
1202 if (nr)
c10fde0d 1203 topology_schedule_update();
8b646bd7 1204 return 0;
1e489518
HC
1205}
1206
8a25a2fd
KS
1207static ssize_t __ref rescan_store(struct device *dev,
1208 struct device_attribute *attr,
c9be0a36 1209 const char *buf,
1e489518
HC
1210 size_t count)
1211{
1212 int rc;
1213
b7cb707c
GS
1214 rc = lock_device_hotplug_sysfs();
1215 if (rc)
1216 return rc;
1e489518 1217 rc = smp_rescan_cpus();
b7cb707c 1218 unlock_device_hotplug();
08d07968
HC
1219 return rc ? rc : count;
1220}
6cbaefb4 1221static DEVICE_ATTR_WO(rescan);
08d07968 1222
83a24e32 1223static int __init s390_smp_init(void)
1da177e4 1224{
f4edbcd5 1225 int cpu, rc = 0;
2fc2d1e9 1226
8a25a2fd 1227 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1228 if (rc)
1229 return rc;
08d07968
HC
1230 for_each_present_cpu(cpu) {
1231 rc = smp_add_present_cpu(cpu);
fae8b22d 1232 if (rc)
f4edbcd5 1233 goto out;
1da177e4 1234 }
f4edbcd5 1235
dfbbd86a
SAS
1236 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1237 smp_cpu_online, smp_cpu_pre_down);
e1108e8f 1238 rc = rc <= 0 ? rc : 0;
f4edbcd5 1239out:
f4edbcd5 1240 return rc;
1da177e4 1241}
83a24e32 1242subsys_initcall(s390_smp_init);