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Commit | Line | Data |
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1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
27f6b416 | 41 | #include <asm/vtimer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
a806170e | 48 | #include "entry.h" |
1da177e4 | 49 | |
8b646bd7 MS |
50 | enum { |
51 | ec_schedule = 0, | |
8b646bd7 MS |
52 | ec_call_function_single, |
53 | ec_stop_cpu, | |
54 | }; | |
08d07968 | 55 | |
8b646bd7 | 56 | enum { |
08d07968 HC |
57 | CPU_STATE_STANDBY, |
58 | CPU_STATE_CONFIGURED, | |
59 | }; | |
60 | ||
8b646bd7 | 61 | struct pcpu { |
96619fc1 | 62 | struct cpu *cpu; |
8b646bd7 MS |
63 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
64 | unsigned long async_stack; /* async stack for the cpu */ | |
65 | unsigned long panic_stack; /* panic stack for the cpu */ | |
66 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
67 | int state; /* physical cpu state */ | |
50ab9a9a | 68 | int polarization; /* physical polarization */ |
8b646bd7 MS |
69 | u16 address; /* physical cpu address */ |
70 | }; | |
71 | ||
72 | static u8 boot_cpu_type; | |
73 | static u16 boot_cpu_address; | |
74 | static struct pcpu pcpu_devices[NR_CPUS]; | |
75 | ||
50ab9a9a HC |
76 | /* |
77 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
78 | * member of a pcpu data structure within the pcpu_devices arreay. | |
79 | */ | |
dbd70fb4 | 80 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 81 | |
8b646bd7 MS |
82 | /* |
83 | * Signal processor helper functions. | |
84 | */ | |
8b646bd7 | 85 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 86 | { |
8b646bd7 | 87 | int cc; |
5c0b912e | 88 | |
8b646bd7 | 89 | while (1) { |
c5e3acd6 | 90 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 91 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
92 | return cc; |
93 | cpu_relax(); | |
5c0b912e | 94 | } |
5c0b912e HC |
95 | } |
96 | ||
8b646bd7 | 97 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 98 | { |
8b646bd7 MS |
99 | int cc, retry; |
100 | ||
101 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 102 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 103 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
104 | break; |
105 | if (retry >= 3) | |
106 | udelay(10); | |
107 | } | |
108 | return cc; | |
109 | } | |
110 | ||
111 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
112 | { | |
41459d36 | 113 | u32 uninitialized_var(status); |
c5e3acd6 | 114 | |
a9ae32c3 | 115 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 116 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 117 | return 0; |
c5e3acd6 | 118 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
119 | } |
120 | ||
121 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 122 | { |
a9ae32c3 | 123 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 124 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 125 | return 1; |
524b24ad HC |
126 | /* Status stored condition code is equivalent to cpu not running. */ |
127 | return 0; | |
a93b8ec1 HC |
128 | } |
129 | ||
1943f53c | 130 | /* |
8b646bd7 | 131 | * Find struct pcpu by cpu address. |
1943f53c | 132 | */ |
8b646bd7 | 133 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
134 | { |
135 | int cpu; | |
136 | ||
8b646bd7 MS |
137 | for_each_cpu(cpu, mask) |
138 | if (pcpu_devices[cpu].address == address) | |
139 | return pcpu_devices + cpu; | |
140 | return NULL; | |
141 | } | |
142 | ||
143 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
144 | { | |
145 | int order; | |
146 | ||
dea24190 HC |
147 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
148 | return; | |
149 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
8b646bd7 MS |
150 | pcpu_sigp_retry(pcpu, order, 0); |
151 | } | |
152 | ||
e2741f17 | 153 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 MS |
154 | { |
155 | struct _lowcore *lc; | |
156 | ||
157 | if (pcpu != &pcpu_devices[0]) { | |
158 | pcpu->lowcore = (struct _lowcore *) | |
159 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
160 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
161 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
162 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
163 | goto out; | |
1943f53c | 164 | } |
8b646bd7 MS |
165 | lc = pcpu->lowcore; |
166 | memcpy(lc, &S390_lowcore, 512); | |
167 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
dc7ee00d MS |
168 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE |
169 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
170 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE | |
171 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
172 | lc->cpu_nr = cpu; |
173 | #ifndef CONFIG_64BIT | |
174 | if (MACHINE_HAS_IEEE) { | |
175 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
176 | if (!lc->extended_save_area_addr) | |
177 | goto out; | |
178 | } | |
179 | #else | |
180 | if (vdso_alloc_per_cpu(lc)) | |
181 | goto out; | |
182 | #endif | |
183 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 184 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
185 | return 0; |
186 | out: | |
187 | if (pcpu != &pcpu_devices[0]) { | |
188 | free_page(pcpu->panic_stack); | |
189 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
190 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
191 | } | |
192 | return -ENOMEM; | |
1943f53c MH |
193 | } |
194 | ||
9d0f46af HC |
195 | #ifdef CONFIG_HOTPLUG_CPU |
196 | ||
8b646bd7 | 197 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 198 | { |
a9ae32c3 | 199 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
200 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
201 | #ifndef CONFIG_64BIT | |
202 | if (MACHINE_HAS_IEEE) { | |
203 | struct _lowcore *lc = pcpu->lowcore; | |
204 | ||
205 | free_page((unsigned long) lc->extended_save_area_addr); | |
206 | lc->extended_save_area_addr = 0; | |
207 | } | |
208 | #else | |
209 | vdso_free_per_cpu(pcpu->lowcore); | |
210 | #endif | |
211 | if (pcpu != &pcpu_devices[0]) { | |
212 | free_page(pcpu->panic_stack); | |
213 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
214 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
215 | } | |
216 | } | |
217 | ||
9d0f46af HC |
218 | #endif /* CONFIG_HOTPLUG_CPU */ |
219 | ||
8b646bd7 MS |
220 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
221 | { | |
222 | struct _lowcore *lc = pcpu->lowcore; | |
223 | ||
1b948d6c MS |
224 | if (MACHINE_HAS_TLB_LC) |
225 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
226 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); | |
8b646bd7 MS |
227 | atomic_inc(&init_mm.context.attach_count); |
228 | lc->cpu_nr = cpu; | |
229 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
230 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
231 | lc->machine_flags = S390_lowcore.machine_flags; | |
232 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
233 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
234 | __ctl_store(lc->cregs_save_area, 0, 15); | |
235 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
236 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
237 | MAX_FACILITY_BIT/8); | |
238 | } | |
239 | ||
240 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
241 | { | |
242 | struct _lowcore *lc = pcpu->lowcore; | |
243 | struct thread_info *ti = task_thread_info(tsk); | |
244 | ||
dc7ee00d MS |
245 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
246 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
247 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
248 | lc->current_task = (unsigned long) tsk; | |
249 | lc->user_timer = ti->user_timer; | |
250 | lc->system_timer = ti->system_timer; | |
251 | lc->steal_timer = 0; | |
252 | } | |
253 | ||
254 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
255 | { | |
256 | struct _lowcore *lc = pcpu->lowcore; | |
257 | ||
258 | lc->restart_stack = lc->kernel_stack; | |
259 | lc->restart_fn = (unsigned long) func; | |
260 | lc->restart_data = (unsigned long) data; | |
261 | lc->restart_source = -1UL; | |
a9ae32c3 | 262 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
263 | } |
264 | ||
265 | /* | |
266 | * Call function via PSW restart on pcpu and stop the current cpu. | |
267 | */ | |
268 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
269 | void *data, unsigned long stack) | |
270 | { | |
061da3df | 271 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 272 | unsigned long source_cpu = stap(); |
8b646bd7 | 273 | |
e258d719 | 274 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 275 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
276 | func(data); /* should not return */ |
277 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 278 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 279 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
280 | mem_assign_absolute(lc->restart_stack, stack); |
281 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
282 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
283 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 284 | asm volatile( |
eb546195 | 285 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 286 | " brc 2,0b # busy, try again\n" |
eb546195 | 287 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 288 | " brc 2,1b # busy, try again\n" |
fbe76568 | 289 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
290 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
291 | : "0", "1", "cc"); | |
8b646bd7 MS |
292 | for (;;) ; |
293 | } | |
294 | ||
295 | /* | |
296 | * Call function on an online CPU. | |
297 | */ | |
298 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
299 | { | |
300 | struct pcpu *pcpu; | |
301 | ||
302 | /* Use the current cpu if it is online. */ | |
303 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
304 | if (!pcpu) | |
305 | /* Use the first online cpu. */ | |
306 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
307 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
308 | } | |
309 | ||
310 | /* | |
311 | * Call function on the ipl CPU. | |
312 | */ | |
313 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
314 | { | |
c6da39f2 MH |
315 | pcpu_delegate(&pcpu_devices[0], func, data, |
316 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
317 | } |
318 | ||
319 | int smp_find_processor_id(u16 address) | |
320 | { | |
321 | int cpu; | |
322 | ||
323 | for_each_present_cpu(cpu) | |
324 | if (pcpu_devices[cpu].address == address) | |
325 | return cpu; | |
326 | return -1; | |
2c2df118 HC |
327 | } |
328 | ||
8b646bd7 | 329 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 330 | { |
8b646bd7 MS |
331 | return pcpu_running(pcpu_devices + cpu); |
332 | } | |
333 | ||
334 | void smp_yield(void) | |
335 | { | |
336 | if (MACHINE_HAS_DIAG44) | |
337 | asm volatile("diag 0,0,0x44"); | |
2c2df118 HC |
338 | } |
339 | ||
8b646bd7 | 340 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 341 | { |
8b646bd7 MS |
342 | if (MACHINE_HAS_DIAG9C) |
343 | asm volatile("diag %0,0,0x9c" | |
344 | : : "d" (pcpu_devices[cpu].address)); | |
345 | else if (MACHINE_HAS_DIAG44) | |
346 | asm volatile("diag 0,0,0x44"); | |
347 | } | |
348 | ||
349 | /* | |
350 | * Send cpus emergency shutdown signal. This gives the cpus the | |
351 | * opportunity to complete outstanding interrupts. | |
352 | */ | |
63df41d6 | 353 | static void smp_emergency_stop(cpumask_t *cpumask) |
8b646bd7 MS |
354 | { |
355 | u64 end; | |
356 | int cpu; | |
357 | ||
1aae0560 | 358 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
359 | for_each_cpu(cpu, cpumask) { |
360 | struct pcpu *pcpu = pcpu_devices + cpu; | |
361 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
362 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
363 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 364 | get_tod_clock() < end) |
8b646bd7 MS |
365 | cpu_relax(); |
366 | } | |
1aae0560 | 367 | while (get_tod_clock() < end) { |
8b646bd7 MS |
368 | for_each_cpu(cpu, cpumask) |
369 | if (pcpu_stopped(pcpu_devices + cpu)) | |
370 | cpumask_clear_cpu(cpu, cpumask); | |
371 | if (cpumask_empty(cpumask)) | |
372 | break; | |
85ac7ca5 | 373 | cpu_relax(); |
8b646bd7 | 374 | } |
85ac7ca5 MS |
375 | } |
376 | ||
8b646bd7 MS |
377 | /* |
378 | * Stop all cpus but the current one. | |
379 | */ | |
677d7623 | 380 | void smp_send_stop(void) |
1da177e4 | 381 | { |
85ac7ca5 MS |
382 | cpumask_t cpumask; |
383 | int cpu; | |
1da177e4 | 384 | |
677d7623 | 385 | /* Disable all interrupts/machine checks */ |
e258d719 | 386 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 387 | trace_hardirqs_off(); |
1da177e4 | 388 | |
3ab121ab | 389 | debug_set_critical(); |
85ac7ca5 MS |
390 | cpumask_copy(&cpumask, cpu_online_mask); |
391 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
392 | ||
8b646bd7 MS |
393 | if (oops_in_progress) |
394 | smp_emergency_stop(&cpumask); | |
1da177e4 | 395 | |
85ac7ca5 MS |
396 | /* stop all processors */ |
397 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 398 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 399 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 400 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
401 | cpu_relax(); |
402 | } | |
403 | } | |
404 | ||
8b646bd7 MS |
405 | /* |
406 | * Stop the current cpu. | |
407 | */ | |
408 | void smp_stop_cpu(void) | |
409 | { | |
a9ae32c3 | 410 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 MS |
411 | for (;;) ; |
412 | } | |
413 | ||
1da177e4 LT |
414 | /* |
415 | * This is the main routine where commands issued by other | |
416 | * cpus are handled. | |
417 | */ | |
9acf73b7 | 418 | static void smp_handle_ext_call(void) |
1da177e4 | 419 | { |
39ce010d | 420 | unsigned long bits; |
1da177e4 | 421 | |
9acf73b7 HC |
422 | /* handle bit signal external calls */ |
423 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
424 | if (test_bit(ec_stop_cpu, &bits)) |
425 | smp_stop_cpu(); | |
184748cc PZ |
426 | if (test_bit(ec_schedule, &bits)) |
427 | scheduler_ipi(); | |
ca9fc75a HC |
428 | if (test_bit(ec_call_function_single, &bits)) |
429 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 430 | } |
85ac7ca5 | 431 | |
9acf73b7 HC |
432 | static void do_ext_call_interrupt(struct ext_code ext_code, |
433 | unsigned int param32, unsigned long param64) | |
434 | { | |
435 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
436 | smp_handle_ext_call(); | |
1da177e4 LT |
437 | } |
438 | ||
630cd046 | 439 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
440 | { |
441 | int cpu; | |
442 | ||
630cd046 | 443 | for_each_cpu(cpu, mask) |
b6ed49e0 | 444 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
445 | } |
446 | ||
447 | void arch_send_call_function_single_ipi(int cpu) | |
448 | { | |
8b646bd7 | 449 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
450 | } |
451 | ||
347a8dc3 | 452 | #ifndef CONFIG_64BIT |
1da177e4 LT |
453 | /* |
454 | * this function sends a 'purge tlb' signal to another CPU. | |
455 | */ | |
a806170e | 456 | static void smp_ptlb_callback(void *info) |
1da177e4 | 457 | { |
ba8a9229 | 458 | __tlb_flush_local(); |
1da177e4 LT |
459 | } |
460 | ||
461 | void smp_ptlb_all(void) | |
462 | { | |
15c8b6c1 | 463 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
464 | } |
465 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 466 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
467 | |
468 | /* | |
469 | * this function sends a 'reschedule' IPI to another CPU. | |
470 | * it goes straight through and wastes no time serializing | |
471 | * anything. Worst case is that we lose a reschedule ... | |
472 | */ | |
473 | void smp_send_reschedule(int cpu) | |
474 | { | |
8b646bd7 | 475 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
476 | } |
477 | ||
478 | /* | |
479 | * parameter area for the set/clear control bit callbacks | |
480 | */ | |
94c12cc7 | 481 | struct ec_creg_mask_parms { |
8b646bd7 MS |
482 | unsigned long orval; |
483 | unsigned long andval; | |
484 | int cr; | |
94c12cc7 | 485 | }; |
1da177e4 LT |
486 | |
487 | /* | |
488 | * callback for setting/clearing control bits | |
489 | */ | |
39ce010d HC |
490 | static void smp_ctl_bit_callback(void *info) |
491 | { | |
94c12cc7 | 492 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 493 | unsigned long cregs[16]; |
39ce010d | 494 | |
94c12cc7 | 495 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 496 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 497 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
498 | } |
499 | ||
500 | /* | |
501 | * Set a bit in a control register of all cpus | |
502 | */ | |
94c12cc7 MS |
503 | void smp_ctl_set_bit(int cr, int bit) |
504 | { | |
8b646bd7 | 505 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 506 | |
15c8b6c1 | 507 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 508 | } |
39ce010d | 509 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
510 | |
511 | /* | |
512 | * Clear a bit in a control register of all cpus | |
513 | */ | |
94c12cc7 MS |
514 | void smp_ctl_clear_bit(int cr, int bit) |
515 | { | |
8b646bd7 | 516 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 517 | |
15c8b6c1 | 518 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 519 | } |
39ce010d | 520 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 521 | |
60a0c68d | 522 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 523 | |
8b646bd7 | 524 | static void __init smp_get_save_area(int cpu, u16 address) |
411ed322 | 525 | { |
8b646bd7 MS |
526 | void *lc = pcpu_devices[0].lowcore; |
527 | struct save_area *save_area; | |
528 | ||
60a0c68d | 529 | if (is_kdump_kernel()) |
411ed322 | 530 | return; |
8b646bd7 MS |
531 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
532 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
533 | return; | |
58952942 | 534 | save_area = dump_save_area_create(cpu); |
8b646bd7 MS |
535 | if (!save_area) |
536 | panic("could not allocate memory for save area\n"); | |
8b646bd7 MS |
537 | #ifdef CONFIG_CRASH_DUMP |
538 | if (address == boot_cpu_address) { | |
539 | /* Copy the registers of the boot cpu. */ | |
540 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
541 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
542 | return; | |
543 | } | |
544 | #endif | |
545 | /* Get the registers of a non-boot cpu. */ | |
a9ae32c3 | 546 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
8b646bd7 | 547 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); |
411ed322 MH |
548 | } |
549 | ||
8b646bd7 | 550 | int smp_store_status(int cpu) |
08d07968 | 551 | { |
8b646bd7 | 552 | struct pcpu *pcpu; |
08d07968 | 553 | |
8b646bd7 | 554 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
555 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
556 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 557 | return -EIO; |
08d07968 HC |
558 | return 0; |
559 | } | |
560 | ||
8b646bd7 | 561 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 562 | |
8b646bd7 | 563 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 564 | |
8b646bd7 | 565 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 566 | |
50ab9a9a HC |
567 | void smp_cpu_set_polarization(int cpu, int val) |
568 | { | |
569 | pcpu_devices[cpu].polarization = val; | |
570 | } | |
571 | ||
572 | int smp_cpu_get_polarization(int cpu) | |
573 | { | |
574 | return pcpu_devices[cpu].polarization; | |
575 | } | |
576 | ||
8b646bd7 | 577 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 578 | { |
8b646bd7 | 579 | static int use_sigp_detection; |
08d07968 | 580 | struct sclp_cpu_info *info; |
8b646bd7 MS |
581 | int address; |
582 | ||
583 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
584 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
585 | use_sigp_detection = 1; | |
586 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
587 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
588 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
589 | continue; |
590 | info->cpu[info->configured].address = address; | |
591 | info->configured++; | |
592 | } | |
593 | info->combined = info->configured; | |
08d07968 | 594 | } |
8b646bd7 | 595 | return info; |
08d07968 HC |
596 | } |
597 | ||
e2741f17 | 598 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 599 | |
e2741f17 | 600 | static int __smp_rescan_cpus(struct sclp_cpu_info *info, int sysfs_add) |
08d07968 | 601 | { |
8b646bd7 | 602 | struct pcpu *pcpu; |
08d07968 | 603 | cpumask_t avail; |
8b646bd7 | 604 | int cpu, nr, i; |
08d07968 | 605 | |
8b646bd7 | 606 | nr = 0; |
0f1959f5 | 607 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
608 | cpu = cpumask_first(&avail); |
609 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
610 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
611 | continue; | |
612 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
613 | continue; | |
614 | pcpu = pcpu_devices + cpu; | |
615 | pcpu->address = info->cpu[i].address; | |
a4eeea4e | 616 | pcpu->state = (i >= info->configured) ? |
8b646bd7 | 617 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; |
50ab9a9a | 618 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
619 | set_cpu_present(cpu, true); |
620 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
621 | set_cpu_present(cpu, false); | |
622 | else | |
623 | nr++; | |
624 | cpu = cpumask_next(cpu, &avail); | |
625 | } | |
626 | return nr; | |
1da177e4 LT |
627 | } |
628 | ||
48483b32 HC |
629 | static void __init smp_detect_cpus(void) |
630 | { | |
631 | unsigned int cpu, c_cpus, s_cpus; | |
632 | struct sclp_cpu_info *info; | |
48483b32 | 633 | |
8b646bd7 | 634 | info = smp_get_cpu_info(); |
48483b32 HC |
635 | if (!info) |
636 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
637 | if (info->has_cpu_type) { |
638 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
639 | if (info->cpu[cpu].address != boot_cpu_address) |
640 | continue; | |
641 | /* The boot cpu dictates the cpu type. */ | |
642 | boot_cpu_type = info->cpu[cpu].type; | |
643 | break; | |
48483b32 HC |
644 | } |
645 | } | |
8b646bd7 | 646 | c_cpus = s_cpus = 0; |
48483b32 | 647 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 648 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 649 | continue; |
8b646bd7 MS |
650 | if (cpu < info->configured) { |
651 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
652 | c_cpus++; | |
653 | } else | |
48483b32 | 654 | s_cpus++; |
48483b32 | 655 | } |
395d31d4 | 656 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 657 | get_online_cpus(); |
8b646bd7 | 658 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 659 | put_online_cpus(); |
8b646bd7 | 660 | kfree(info); |
48483b32 HC |
661 | } |
662 | ||
1da177e4 | 663 | /* |
39ce010d | 664 | * Activate a secondary processor. |
1da177e4 | 665 | */ |
e2741f17 | 666 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 667 | { |
1aae0560 | 668 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
669 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
670 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
671 | S390_lowcore.restart_data = 0; | |
672 | S390_lowcore.restart_source = -1UL; | |
673 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
674 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 675 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 676 | cpu_init(); |
5bfb5d69 | 677 | preempt_disable(); |
39ce010d | 678 | init_cpu_timer(); |
39ce010d | 679 | init_cpu_vtimer(); |
29b08d2b | 680 | pfault_init(); |
e545a614 | 681 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 682 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 683 | inc_irq_stat(CPU_RST); |
1da177e4 | 684 | local_irq_enable(); |
52c00659 | 685 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
686 | } |
687 | ||
1da177e4 | 688 | /* Upping and downing of CPUs */ |
e2741f17 | 689 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 690 | { |
8b646bd7 MS |
691 | struct pcpu *pcpu; |
692 | int rc; | |
1da177e4 | 693 | |
8b646bd7 MS |
694 | pcpu = pcpu_devices + cpu; |
695 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 696 | return -EIO; |
a9ae32c3 HC |
697 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
698 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 699 | return -EIO; |
e80e7813 | 700 | |
8b646bd7 MS |
701 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
702 | if (rc) | |
703 | return rc; | |
704 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 705 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 706 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
707 | while (!cpu_online(cpu)) |
708 | cpu_relax(); | |
709 | return 0; | |
710 | } | |
711 | ||
d80512f8 | 712 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 713 | |
d80512f8 HC |
714 | static int __init _setup_possible_cpus(char *s) |
715 | { | |
716 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
717 | return 0; |
718 | } | |
d80512f8 | 719 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 720 | |
48483b32 HC |
721 | #ifdef CONFIG_HOTPLUG_CPU |
722 | ||
39ce010d | 723 | int __cpu_disable(void) |
1da177e4 | 724 | { |
8b646bd7 | 725 | unsigned long cregs[16]; |
1da177e4 | 726 | |
9acf73b7 HC |
727 | /* Handle possible pending IPIs */ |
728 | smp_handle_ext_call(); | |
8b646bd7 MS |
729 | set_cpu_online(smp_processor_id(), false); |
730 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 731 | pfault_fini(); |
8b646bd7 MS |
732 | /* Disable interrupt sources via control register. */ |
733 | __ctl_store(cregs, 0, 15); | |
734 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
735 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
736 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
737 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
738 | return 0; |
739 | } | |
740 | ||
39ce010d | 741 | void __cpu_die(unsigned int cpu) |
1da177e4 | 742 | { |
8b646bd7 MS |
743 | struct pcpu *pcpu; |
744 | ||
1da177e4 | 745 | /* Wait until target cpu is down */ |
8b646bd7 MS |
746 | pcpu = pcpu_devices + cpu; |
747 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 748 | cpu_relax(); |
8b646bd7 | 749 | pcpu_free_lowcore(pcpu); |
050eef36 | 750 | atomic_dec(&init_mm.context.attach_count); |
1b948d6c MS |
751 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
752 | if (MACHINE_HAS_TLB_LC) | |
753 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
1da177e4 LT |
754 | } |
755 | ||
b456d94a | 756 | void __noreturn cpu_die(void) |
1da177e4 LT |
757 | { |
758 | idle_task_exit(); | |
a9ae32c3 | 759 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 760 | for (;;) ; |
1da177e4 LT |
761 | } |
762 | ||
255acee7 HC |
763 | #endif /* CONFIG_HOTPLUG_CPU */ |
764 | ||
d80512f8 HC |
765 | void __init smp_fill_possible_mask(void) |
766 | { | |
cf813db0 | 767 | unsigned int possible, sclp, cpu; |
d80512f8 | 768 | |
cf813db0 HC |
769 | sclp = sclp_get_max_cpu() ?: nr_cpu_ids; |
770 | possible = setup_possible_cpus ?: nr_cpu_ids; | |
771 | possible = min(possible, sclp); | |
d80512f8 HC |
772 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
773 | set_cpu_possible(cpu, true); | |
774 | } | |
775 | ||
1da177e4 LT |
776 | void __init smp_prepare_cpus(unsigned int max_cpus) |
777 | { | |
39ce010d | 778 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 779 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 780 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 781 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 782 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 783 | panic("Couldn't request external interrupt 0x1202"); |
8b646bd7 | 784 | smp_detect_cpus(); |
1da177e4 LT |
785 | } |
786 | ||
ea1f4eec | 787 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 788 | { |
8b646bd7 MS |
789 | struct pcpu *pcpu = pcpu_devices; |
790 | ||
791 | boot_cpu_address = stap(); | |
8b646bd7 MS |
792 | pcpu->state = CPU_STATE_CONFIGURED; |
793 | pcpu->address = boot_cpu_address; | |
794 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
dc7ee00d MS |
795 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE |
796 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
797 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE | |
798 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
1da177e4 | 799 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 800 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
801 | set_cpu_present(0, true); |
802 | set_cpu_online(0, true); | |
1da177e4 LT |
803 | } |
804 | ||
ea1f4eec | 805 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 806 | { |
1da177e4 LT |
807 | } |
808 | ||
02beaccc HC |
809 | void __init smp_setup_processor_id(void) |
810 | { | |
811 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
812 | } |
813 | ||
1da177e4 LT |
814 | /* |
815 | * the frequency of the profiling timer can be changed | |
816 | * by writing a multiplier value into /proc/profile. | |
817 | * | |
818 | * usually you want to run this on all CPUs ;) | |
819 | */ | |
820 | int setup_profiling_timer(unsigned int multiplier) | |
821 | { | |
39ce010d | 822 | return 0; |
1da177e4 LT |
823 | } |
824 | ||
08d07968 | 825 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 826 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 827 | struct device_attribute *attr, char *buf) |
08d07968 HC |
828 | { |
829 | ssize_t count; | |
830 | ||
831 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 832 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
833 | mutex_unlock(&smp_cpu_state_mutex); |
834 | return count; | |
835 | } | |
836 | ||
8a25a2fd | 837 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
838 | struct device_attribute *attr, |
839 | const char *buf, size_t count) | |
08d07968 | 840 | { |
8b646bd7 MS |
841 | struct pcpu *pcpu; |
842 | int cpu, val, rc; | |
08d07968 HC |
843 | char delim; |
844 | ||
845 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
846 | return -EINVAL; | |
847 | if (val != 0 && val != 1) | |
848 | return -EINVAL; | |
9d40d2e3 | 849 | get_online_cpus(); |
0b18d318 | 850 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 851 | rc = -EBUSY; |
2c2df118 | 852 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 853 | cpu = dev->id; |
2c2df118 | 854 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 855 | goto out; |
8b646bd7 | 856 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
857 | rc = 0; |
858 | switch (val) { | |
859 | case 0: | |
8b646bd7 MS |
860 | if (pcpu->state != CPU_STATE_CONFIGURED) |
861 | break; | |
862 | rc = sclp_cpu_deconfigure(pcpu->address); | |
863 | if (rc) | |
864 | break; | |
865 | pcpu->state = CPU_STATE_STANDBY; | |
50ab9a9a | 866 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 867 | topology_expect_change(); |
08d07968 HC |
868 | break; |
869 | case 1: | |
8b646bd7 MS |
870 | if (pcpu->state != CPU_STATE_STANDBY) |
871 | break; | |
872 | rc = sclp_cpu_configure(pcpu->address); | |
873 | if (rc) | |
874 | break; | |
875 | pcpu->state = CPU_STATE_CONFIGURED; | |
50ab9a9a | 876 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 877 | topology_expect_change(); |
08d07968 HC |
878 | break; |
879 | default: | |
880 | break; | |
881 | } | |
882 | out: | |
08d07968 | 883 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 884 | put_online_cpus(); |
08d07968 HC |
885 | return rc ? rc : count; |
886 | } | |
8a25a2fd | 887 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
888 | #endif /* CONFIG_HOTPLUG_CPU */ |
889 | ||
8a25a2fd KS |
890 | static ssize_t show_cpu_address(struct device *dev, |
891 | struct device_attribute *attr, char *buf) | |
08d07968 | 892 | { |
8b646bd7 | 893 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 894 | } |
8a25a2fd | 895 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 896 | |
08d07968 HC |
897 | static struct attribute *cpu_common_attrs[] = { |
898 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 899 | &dev_attr_configure.attr, |
08d07968 | 900 | #endif |
8a25a2fd | 901 | &dev_attr_address.attr, |
08d07968 HC |
902 | NULL, |
903 | }; | |
904 | ||
905 | static struct attribute_group cpu_common_attr_group = { | |
906 | .attrs = cpu_common_attrs, | |
907 | }; | |
1da177e4 | 908 | |
8a25a2fd KS |
909 | static ssize_t show_idle_count(struct device *dev, |
910 | struct device_attribute *attr, char *buf) | |
fae8b22d | 911 | { |
4c1051e3 | 912 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
fae8b22d | 913 | unsigned long long idle_count; |
e98bbaaf | 914 | unsigned int sequence; |
fae8b22d | 915 | |
4c1051e3 MS |
916 | do { |
917 | sequence = ACCESS_ONCE(idle->sequence); | |
918 | idle_count = ACCESS_ONCE(idle->idle_count); | |
27f6b416 | 919 | if (ACCESS_ONCE(idle->clock_idle_enter)) |
4c1051e3 | 920 | idle_count++; |
4560e7c3 | 921 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
fae8b22d HC |
922 | return sprintf(buf, "%llu\n", idle_count); |
923 | } | |
8a25a2fd | 924 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 925 | |
8a25a2fd KS |
926 | static ssize_t show_idle_time(struct device *dev, |
927 | struct device_attribute *attr, char *buf) | |
fae8b22d | 928 | { |
4c1051e3 MS |
929 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
930 | unsigned long long now, idle_time, idle_enter, idle_exit; | |
e98bbaaf | 931 | unsigned int sequence; |
fae8b22d | 932 | |
4c1051e3 | 933 | do { |
1aae0560 | 934 | now = get_tod_clock(); |
4c1051e3 MS |
935 | sequence = ACCESS_ONCE(idle->sequence); |
936 | idle_time = ACCESS_ONCE(idle->idle_time); | |
27f6b416 MS |
937 | idle_enter = ACCESS_ONCE(idle->clock_idle_enter); |
938 | idle_exit = ACCESS_ONCE(idle->clock_idle_exit); | |
4560e7c3 | 939 | } while ((sequence & 1) || (ACCESS_ONCE(idle->sequence) != sequence)); |
4c1051e3 | 940 | idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0; |
6f430924 | 941 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 942 | } |
8a25a2fd | 943 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 944 | |
08d07968 | 945 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
946 | &dev_attr_idle_count.attr, |
947 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
948 | NULL, |
949 | }; | |
950 | ||
08d07968 HC |
951 | static struct attribute_group cpu_online_attr_group = { |
952 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
953 | }; |
954 | ||
e2741f17 PG |
955 | static int smp_cpu_notify(struct notifier_block *self, unsigned long action, |
956 | void *hcpu) | |
2fc2d1e9 HC |
957 | { |
958 | unsigned int cpu = (unsigned int)(long)hcpu; | |
96619fc1 | 959 | struct cpu *c = pcpu_devices[cpu].cpu; |
8a25a2fd | 960 | struct device *s = &c->dev; |
d882ba69 | 961 | int err = 0; |
2fc2d1e9 | 962 | |
1c725922 | 963 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 964 | case CPU_ONLINE: |
d882ba69 | 965 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
966 | break; |
967 | case CPU_DEAD: | |
08d07968 | 968 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
969 | break; |
970 | } | |
d882ba69 | 971 | return notifier_from_errno(err); |
2fc2d1e9 HC |
972 | } |
973 | ||
e2741f17 | 974 | static int smp_add_present_cpu(int cpu) |
08d07968 | 975 | { |
96619fc1 HC |
976 | struct device *s; |
977 | struct cpu *c; | |
08d07968 HC |
978 | int rc; |
979 | ||
96619fc1 HC |
980 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
981 | if (!c) | |
982 | return -ENOMEM; | |
983 | pcpu_devices[cpu].cpu = c; | |
984 | s = &c->dev; | |
08d07968 HC |
985 | c->hotpluggable = 1; |
986 | rc = register_cpu(c, cpu); | |
987 | if (rc) | |
988 | goto out; | |
989 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
990 | if (rc) | |
991 | goto out_cpu; | |
83a24e32 HC |
992 | if (cpu_online(cpu)) { |
993 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
994 | if (rc) | |
995 | goto out_online; | |
996 | } | |
997 | rc = topology_cpu_init(c); | |
998 | if (rc) | |
999 | goto out_topology; | |
1000 | return 0; | |
1001 | ||
1002 | out_topology: | |
1003 | if (cpu_online(cpu)) | |
1004 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1005 | out_online: | |
08d07968 HC |
1006 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1007 | out_cpu: | |
1008 | #ifdef CONFIG_HOTPLUG_CPU | |
1009 | unregister_cpu(c); | |
1010 | #endif | |
1011 | out: | |
1012 | return rc; | |
1013 | } | |
1014 | ||
1015 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1016 | |
67060d9c | 1017 | int __ref smp_rescan_cpus(void) |
08d07968 | 1018 | { |
8b646bd7 MS |
1019 | struct sclp_cpu_info *info; |
1020 | int nr; | |
08d07968 | 1021 | |
8b646bd7 MS |
1022 | info = smp_get_cpu_info(); |
1023 | if (!info) | |
1024 | return -ENOMEM; | |
9d40d2e3 | 1025 | get_online_cpus(); |
0b18d318 | 1026 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1027 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1028 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1029 | put_online_cpus(); |
8b646bd7 MS |
1030 | kfree(info); |
1031 | if (nr) | |
c10fde0d | 1032 | topology_schedule_update(); |
8b646bd7 | 1033 | return 0; |
1e489518 HC |
1034 | } |
1035 | ||
8a25a2fd KS |
1036 | static ssize_t __ref rescan_store(struct device *dev, |
1037 | struct device_attribute *attr, | |
c9be0a36 | 1038 | const char *buf, |
1e489518 HC |
1039 | size_t count) |
1040 | { | |
1041 | int rc; | |
1042 | ||
1043 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1044 | return rc ? rc : count; |
1045 | } | |
8a25a2fd | 1046 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1047 | #endif /* CONFIG_HOTPLUG_CPU */ |
1048 | ||
83a24e32 | 1049 | static int __init s390_smp_init(void) |
1da177e4 | 1050 | { |
f4edbcd5 | 1051 | int cpu, rc = 0; |
2fc2d1e9 | 1052 | |
08d07968 | 1053 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1054 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1055 | if (rc) |
1056 | return rc; | |
1057 | #endif | |
f4edbcd5 | 1058 | cpu_notifier_register_begin(); |
08d07968 HC |
1059 | for_each_present_cpu(cpu) { |
1060 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1061 | if (rc) |
f4edbcd5 | 1062 | goto out; |
1da177e4 | 1063 | } |
f4edbcd5 SB |
1064 | |
1065 | __hotcpu_notifier(smp_cpu_notify, 0); | |
1066 | ||
1067 | out: | |
1068 | cpu_notifier_register_done(); | |
1069 | return rc; | |
1da177e4 | 1070 | } |
83a24e32 | 1071 | subsys_initcall(s390_smp_init); |