]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
af51160e | 22 | #include <linux/bootmem.h> |
3994a52b | 23 | #include <linux/export.h> |
1da177e4 | 24 | #include <linux/init.h> |
1da177e4 | 25 | #include <linux/mm.h> |
4e950f6f | 26 | #include <linux/err.h> |
1da177e4 LT |
27 | #include <linux/spinlock.h> |
28 | #include <linux/kernel_stat.h> | |
1da177e4 | 29 | #include <linux/delay.h> |
1da177e4 | 30 | #include <linux/interrupt.h> |
3324e60a | 31 | #include <linux/irqflags.h> |
1da177e4 | 32 | #include <linux/cpu.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
ef8bd77f | 34 | #include <linux/sched/hotplug.h> |
68db0cf1 | 35 | #include <linux/sched/task_stack.h> |
60a0c68d | 36 | #include <linux/crash_dump.h> |
1592a8e4 | 37 | #include <linux/memblock.h> |
cbb870c8 | 38 | #include <asm/asm-offsets.h> |
1ec2772e | 39 | #include <asm/diag.h> |
1e3cab2f HC |
40 | #include <asm/switch_to.h> |
41 | #include <asm/facility.h> | |
46b05d26 | 42 | #include <asm/ipl.h> |
2b67fc46 | 43 | #include <asm/setup.h> |
1da177e4 | 44 | #include <asm/irq.h> |
1da177e4 | 45 | #include <asm/tlbflush.h> |
27f6b416 | 46 | #include <asm/vtimer.h> |
411ed322 | 47 | #include <asm/lowcore.h> |
08d07968 | 48 | #include <asm/sclp.h> |
c742b31c | 49 | #include <asm/vdso.h> |
3ab121ab | 50 | #include <asm/debug.h> |
4857d4bb | 51 | #include <asm/os_info.h> |
a9ae32c3 | 52 | #include <asm/sigp.h> |
b5f87f15 | 53 | #include <asm/idle.h> |
a806170e | 54 | #include "entry.h" |
1da177e4 | 55 | |
8b646bd7 MS |
56 | enum { |
57 | ec_schedule = 0, | |
8b646bd7 MS |
58 | ec_call_function_single, |
59 | ec_stop_cpu, | |
60 | }; | |
08d07968 | 61 | |
8b646bd7 | 62 | enum { |
08d07968 HC |
63 | CPU_STATE_STANDBY, |
64 | CPU_STATE_CONFIGURED, | |
65 | }; | |
66 | ||
2f859d0d HC |
67 | static DEFINE_PER_CPU(struct cpu *, cpu_device); |
68 | ||
8b646bd7 | 69 | struct pcpu { |
c667aeac | 70 | struct lowcore *lowcore; /* lowcore page(s) for the cpu */ |
8b646bd7 | 71 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ |
3dbc78d3 | 72 | unsigned long ec_clk; /* sigp timestamp for ec_xxx */ |
2f859d0d HC |
73 | signed char state; /* physical cpu state */ |
74 | signed char polarization; /* physical polarization */ | |
8b646bd7 MS |
75 | u16 address; /* physical cpu address */ |
76 | }; | |
77 | ||
d08d9430 | 78 | static u8 boot_core_type; |
8b646bd7 MS |
79 | static struct pcpu pcpu_devices[NR_CPUS]; |
80 | ||
10ad34bc MS |
81 | unsigned int smp_cpu_mt_shift; |
82 | EXPORT_SYMBOL(smp_cpu_mt_shift); | |
83 | ||
84 | unsigned int smp_cpu_mtid; | |
85 | EXPORT_SYMBOL(smp_cpu_mtid); | |
86 | ||
1a36a39e MS |
87 | #ifdef CONFIG_CRASH_DUMP |
88 | __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; | |
89 | #endif | |
90 | ||
10ad34bc MS |
91 | static unsigned int smp_max_threads __initdata = -1U; |
92 | ||
93 | static int __init early_nosmt(char *s) | |
94 | { | |
95 | smp_max_threads = 1; | |
96 | return 0; | |
97 | } | |
98 | early_param("nosmt", early_nosmt); | |
99 | ||
100 | static int __init early_smt(char *s) | |
101 | { | |
102 | get_option(&s, &smp_max_threads); | |
103 | return 0; | |
104 | } | |
105 | early_param("smt", early_smt); | |
106 | ||
50ab9a9a HC |
107 | /* |
108 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
109 | * member of a pcpu data structure within the pcpu_devices arreay. | |
110 | */ | |
dbd70fb4 | 111 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 112 | |
8b646bd7 MS |
113 | /* |
114 | * Signal processor helper functions. | |
115 | */ | |
1a36a39e | 116 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) |
5c0b912e | 117 | { |
8b646bd7 | 118 | int cc; |
5c0b912e | 119 | |
8b646bd7 | 120 | while (1) { |
c5e3acd6 | 121 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 122 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
123 | return cc; |
124 | cpu_relax(); | |
5c0b912e | 125 | } |
5c0b912e HC |
126 | } |
127 | ||
8b646bd7 | 128 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 129 | { |
8b646bd7 MS |
130 | int cc, retry; |
131 | ||
132 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 133 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 134 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
135 | break; |
136 | if (retry >= 3) | |
137 | udelay(10); | |
138 | } | |
139 | return cc; | |
140 | } | |
141 | ||
142 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
143 | { | |
41459d36 | 144 | u32 uninitialized_var(status); |
c5e3acd6 | 145 | |
a9ae32c3 | 146 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 147 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 148 | return 0; |
c5e3acd6 | 149 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
150 | } |
151 | ||
152 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 153 | { |
a9ae32c3 | 154 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 155 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 156 | return 1; |
524b24ad HC |
157 | /* Status stored condition code is equivalent to cpu not running. */ |
158 | return 0; | |
a93b8ec1 HC |
159 | } |
160 | ||
1943f53c | 161 | /* |
8b646bd7 | 162 | * Find struct pcpu by cpu address. |
1943f53c | 163 | */ |
10ad34bc | 164 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) |
1943f53c MH |
165 | { |
166 | int cpu; | |
167 | ||
8b646bd7 MS |
168 | for_each_cpu(cpu, mask) |
169 | if (pcpu_devices[cpu].address == address) | |
170 | return pcpu_devices + cpu; | |
171 | return NULL; | |
172 | } | |
173 | ||
174 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
175 | { | |
176 | int order; | |
177 | ||
dea24190 HC |
178 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
179 | return; | |
180 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
3dbc78d3 | 181 | pcpu->ec_clk = get_tod_clock_fast(); |
8b646bd7 MS |
182 | pcpu_sigp_retry(pcpu, order, 0); |
183 | } | |
184 | ||
2f859d0d HC |
185 | #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) |
186 | #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) | |
187 | ||
e2741f17 | 188 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 | 189 | { |
2f859d0d | 190 | unsigned long async_stack, panic_stack; |
c667aeac | 191 | struct lowcore *lc; |
8b646bd7 MS |
192 | |
193 | if (pcpu != &pcpu_devices[0]) { | |
c667aeac | 194 | pcpu->lowcore = (struct lowcore *) |
8b646bd7 | 195 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
2f859d0d HC |
196 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); |
197 | panic_stack = __get_free_page(GFP_KERNEL); | |
198 | if (!pcpu->lowcore || !panic_stack || !async_stack) | |
8b646bd7 | 199 | goto out; |
2f859d0d HC |
200 | } else { |
201 | async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET; | |
202 | panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET; | |
1943f53c | 203 | } |
8b646bd7 MS |
204 | lc = pcpu->lowcore; |
205 | memcpy(lc, &S390_lowcore, 512); | |
206 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
2f859d0d HC |
207 | lc->async_stack = async_stack + ASYNC_FRAME_OFFSET; |
208 | lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET; | |
8b646bd7 | 209 | lc->cpu_nr = cpu; |
6c8cd5bb | 210 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
80703617 MS |
211 | if (MACHINE_HAS_VX) |
212 | lc->vector_save_area_addr = | |
213 | (unsigned long) &lc->vector_save_area; | |
8b646bd7 MS |
214 | if (vdso_alloc_per_cpu(lc)) |
215 | goto out; | |
8b646bd7 | 216 | lowcore_ptr[cpu] = lc; |
a9ae32c3 | 217 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
218 | return 0; |
219 | out: | |
220 | if (pcpu != &pcpu_devices[0]) { | |
2f859d0d HC |
221 | free_page(panic_stack); |
222 | free_pages(async_stack, ASYNC_ORDER); | |
8b646bd7 MS |
223 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); |
224 | } | |
225 | return -ENOMEM; | |
1943f53c MH |
226 | } |
227 | ||
9d0f46af HC |
228 | #ifdef CONFIG_HOTPLUG_CPU |
229 | ||
8b646bd7 | 230 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 231 | { |
a9ae32c3 | 232 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 | 233 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
8b646bd7 | 234 | vdso_free_per_cpu(pcpu->lowcore); |
2f859d0d HC |
235 | if (pcpu == &pcpu_devices[0]) |
236 | return; | |
237 | free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET); | |
238 | free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER); | |
239 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
8b646bd7 MS |
240 | } |
241 | ||
9d0f46af HC |
242 | #endif /* CONFIG_HOTPLUG_CPU */ |
243 | ||
8b646bd7 MS |
244 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
245 | { | |
c667aeac | 246 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 247 | |
64f31d58 | 248 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1b948d6c | 249 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); |
8b646bd7 | 250 | lc->cpu_nr = cpu; |
6c8cd5bb | 251 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
8b646bd7 MS |
252 | lc->percpu_offset = __per_cpu_offset[cpu]; |
253 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
254 | lc->machine_flags = S390_lowcore.machine_flags; | |
8b646bd7 MS |
255 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; |
256 | __ctl_store(lc->cregs_save_area, 0, 15); | |
257 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
258 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
259 | MAX_FACILITY_BIT/8); | |
260 | } | |
261 | ||
262 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
263 | { | |
c667aeac | 264 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 265 | |
dc7ee00d MS |
266 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
267 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 | 268 | lc->current_task = (unsigned long) tsk; |
e22cf8ca CB |
269 | lc->lpp = LPP_MAGIC; |
270 | lc->current_pid = tsk->pid; | |
90c53e65 MS |
271 | lc->user_timer = tsk->thread.user_timer; |
272 | lc->system_timer = tsk->thread.system_timer; | |
8b646bd7 MS |
273 | lc->steal_timer = 0; |
274 | } | |
275 | ||
276 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
277 | { | |
c667aeac | 278 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 MS |
279 | |
280 | lc->restart_stack = lc->kernel_stack; | |
281 | lc->restart_fn = (unsigned long) func; | |
282 | lc->restart_data = (unsigned long) data; | |
283 | lc->restart_source = -1UL; | |
a9ae32c3 | 284 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
285 | } |
286 | ||
287 | /* | |
288 | * Call function via PSW restart on pcpu and stop the current cpu. | |
289 | */ | |
290 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
291 | void *data, unsigned long stack) | |
292 | { | |
c667aeac | 293 | struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 294 | unsigned long source_cpu = stap(); |
8b646bd7 | 295 | |
e258d719 | 296 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 297 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
298 | func(data); /* should not return */ |
299 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 300 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 301 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
302 | mem_assign_absolute(lc->restart_stack, stack); |
303 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
304 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
305 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 306 | asm volatile( |
eb546195 | 307 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 308 | " brc 2,0b # busy, try again\n" |
eb546195 | 309 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 310 | " brc 2,1b # busy, try again\n" |
fbe76568 | 311 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
312 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
313 | : "0", "1", "cc"); | |
8b646bd7 MS |
314 | for (;;) ; |
315 | } | |
316 | ||
10ad34bc MS |
317 | /* |
318 | * Enable additional logical cpus for multi-threading. | |
319 | */ | |
320 | static int pcpu_set_smt(unsigned int mtid) | |
321 | { | |
10ad34bc MS |
322 | int cc; |
323 | ||
324 | if (smp_cpu_mtid == mtid) | |
325 | return 0; | |
80a60f6e | 326 | cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); |
10ad34bc MS |
327 | if (cc == 0) { |
328 | smp_cpu_mtid = mtid; | |
329 | smp_cpu_mt_shift = 0; | |
330 | while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) | |
331 | smp_cpu_mt_shift++; | |
332 | pcpu_devices[0].address = stap(); | |
333 | } | |
334 | return cc; | |
335 | } | |
336 | ||
8b646bd7 MS |
337 | /* |
338 | * Call function on an online CPU. | |
339 | */ | |
340 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
341 | { | |
342 | struct pcpu *pcpu; | |
343 | ||
344 | /* Use the current cpu if it is online. */ | |
345 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
346 | if (!pcpu) | |
347 | /* Use the first online cpu. */ | |
348 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
349 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
350 | } | |
351 | ||
352 | /* | |
353 | * Call function on the ipl CPU. | |
354 | */ | |
355 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
356 | { | |
c6da39f2 | 357 | pcpu_delegate(&pcpu_devices[0], func, data, |
2f859d0d HC |
358 | pcpu_devices->lowcore->panic_stack - |
359 | PANIC_FRAME_OFFSET + PAGE_SIZE); | |
8b646bd7 MS |
360 | } |
361 | ||
362 | int smp_find_processor_id(u16 address) | |
363 | { | |
364 | int cpu; | |
365 | ||
366 | for_each_present_cpu(cpu) | |
367 | if (pcpu_devices[cpu].address == address) | |
368 | return cpu; | |
369 | return -1; | |
2c2df118 HC |
370 | } |
371 | ||
760928c0 | 372 | bool arch_vcpu_is_preempted(int cpu) |
85ac7ca5 | 373 | { |
760928c0 CB |
374 | if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) |
375 | return false; | |
376 | if (pcpu_running(pcpu_devices + cpu)) | |
377 | return false; | |
378 | return true; | |
8b646bd7 | 379 | } |
760928c0 | 380 | EXPORT_SYMBOL(arch_vcpu_is_preempted); |
8b646bd7 | 381 | |
8b646bd7 | 382 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 383 | { |
1ec2772e | 384 | if (MACHINE_HAS_DIAG9C) { |
b5a6b71b | 385 | diag_stat_inc_norecursion(DIAG_STAT_X09C); |
8b646bd7 MS |
386 | asm volatile("diag %0,0,0x9c" |
387 | : : "d" (pcpu_devices[cpu].address)); | |
1ec2772e | 388 | } else if (MACHINE_HAS_DIAG44) { |
b5a6b71b | 389 | diag_stat_inc_norecursion(DIAG_STAT_X044); |
8b646bd7 | 390 | asm volatile("diag 0,0,0x44"); |
1ec2772e | 391 | } |
8b646bd7 MS |
392 | } |
393 | ||
394 | /* | |
395 | * Send cpus emergency shutdown signal. This gives the cpus the | |
396 | * opportunity to complete outstanding interrupts. | |
397 | */ | |
63df41d6 | 398 | static void smp_emergency_stop(cpumask_t *cpumask) |
8b646bd7 MS |
399 | { |
400 | u64 end; | |
401 | int cpu; | |
402 | ||
1aae0560 | 403 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
404 | for_each_cpu(cpu, cpumask) { |
405 | struct pcpu *pcpu = pcpu_devices + cpu; | |
406 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
407 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
408 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 409 | get_tod_clock() < end) |
8b646bd7 MS |
410 | cpu_relax(); |
411 | } | |
1aae0560 | 412 | while (get_tod_clock() < end) { |
8b646bd7 MS |
413 | for_each_cpu(cpu, cpumask) |
414 | if (pcpu_stopped(pcpu_devices + cpu)) | |
415 | cpumask_clear_cpu(cpu, cpumask); | |
416 | if (cpumask_empty(cpumask)) | |
417 | break; | |
85ac7ca5 | 418 | cpu_relax(); |
8b646bd7 | 419 | } |
85ac7ca5 MS |
420 | } |
421 | ||
8b646bd7 MS |
422 | /* |
423 | * Stop all cpus but the current one. | |
424 | */ | |
677d7623 | 425 | void smp_send_stop(void) |
1da177e4 | 426 | { |
85ac7ca5 MS |
427 | cpumask_t cpumask; |
428 | int cpu; | |
1da177e4 | 429 | |
677d7623 | 430 | /* Disable all interrupts/machine checks */ |
e258d719 | 431 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 432 | trace_hardirqs_off(); |
1da177e4 | 433 | |
3ab121ab | 434 | debug_set_critical(); |
85ac7ca5 MS |
435 | cpumask_copy(&cpumask, cpu_online_mask); |
436 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
437 | ||
8b646bd7 MS |
438 | if (oops_in_progress) |
439 | smp_emergency_stop(&cpumask); | |
1da177e4 | 440 | |
85ac7ca5 MS |
441 | /* stop all processors */ |
442 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 443 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 444 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 445 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
446 | cpu_relax(); |
447 | } | |
448 | } | |
449 | ||
1da177e4 LT |
450 | /* |
451 | * This is the main routine where commands issued by other | |
452 | * cpus are handled. | |
453 | */ | |
9acf73b7 | 454 | static void smp_handle_ext_call(void) |
1da177e4 | 455 | { |
39ce010d | 456 | unsigned long bits; |
1da177e4 | 457 | |
9acf73b7 HC |
458 | /* handle bit signal external calls */ |
459 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
460 | if (test_bit(ec_stop_cpu, &bits)) |
461 | smp_stop_cpu(); | |
184748cc PZ |
462 | if (test_bit(ec_schedule, &bits)) |
463 | scheduler_ipi(); | |
ca9fc75a HC |
464 | if (test_bit(ec_call_function_single, &bits)) |
465 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 466 | } |
85ac7ca5 | 467 | |
9acf73b7 HC |
468 | static void do_ext_call_interrupt(struct ext_code ext_code, |
469 | unsigned int param32, unsigned long param64) | |
470 | { | |
471 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
472 | smp_handle_ext_call(); | |
1da177e4 LT |
473 | } |
474 | ||
630cd046 | 475 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
476 | { |
477 | int cpu; | |
478 | ||
630cd046 | 479 | for_each_cpu(cpu, mask) |
b6ed49e0 | 480 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
481 | } |
482 | ||
483 | void arch_send_call_function_single_ipi(int cpu) | |
484 | { | |
8b646bd7 | 485 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
486 | } |
487 | ||
1da177e4 LT |
488 | /* |
489 | * this function sends a 'reschedule' IPI to another CPU. | |
490 | * it goes straight through and wastes no time serializing | |
491 | * anything. Worst case is that we lose a reschedule ... | |
492 | */ | |
493 | void smp_send_reschedule(int cpu) | |
494 | { | |
8b646bd7 | 495 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
496 | } |
497 | ||
498 | /* | |
499 | * parameter area for the set/clear control bit callbacks | |
500 | */ | |
94c12cc7 | 501 | struct ec_creg_mask_parms { |
8b646bd7 MS |
502 | unsigned long orval; |
503 | unsigned long andval; | |
504 | int cr; | |
94c12cc7 | 505 | }; |
1da177e4 LT |
506 | |
507 | /* | |
508 | * callback for setting/clearing control bits | |
509 | */ | |
39ce010d HC |
510 | static void smp_ctl_bit_callback(void *info) |
511 | { | |
94c12cc7 | 512 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 513 | unsigned long cregs[16]; |
39ce010d | 514 | |
94c12cc7 | 515 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 516 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 517 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
518 | } |
519 | ||
520 | /* | |
521 | * Set a bit in a control register of all cpus | |
522 | */ | |
94c12cc7 MS |
523 | void smp_ctl_set_bit(int cr, int bit) |
524 | { | |
8b646bd7 | 525 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 526 | |
15c8b6c1 | 527 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 528 | } |
39ce010d | 529 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
530 | |
531 | /* | |
532 | * Clear a bit in a control register of all cpus | |
533 | */ | |
94c12cc7 MS |
534 | void smp_ctl_clear_bit(int cr, int bit) |
535 | { | |
8b646bd7 | 536 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 537 | |
15c8b6c1 | 538 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 539 | } |
39ce010d | 540 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 541 | |
bf28a597 | 542 | #ifdef CONFIG_CRASH_DUMP |
411ed322 | 543 | |
1af135a1 HC |
544 | int smp_store_status(int cpu) |
545 | { | |
1a36a39e MS |
546 | struct pcpu *pcpu = pcpu_devices + cpu; |
547 | unsigned long pa; | |
1af135a1 | 548 | |
1a36a39e MS |
549 | pa = __pa(&pcpu->lowcore->floating_pt_save_area); |
550 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, | |
551 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
1af135a1 HC |
552 | return -EIO; |
553 | if (!MACHINE_HAS_VX) | |
554 | return 0; | |
1a36a39e MS |
555 | pa = __pa(pcpu->lowcore->vector_save_area_addr); |
556 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, | |
557 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
558 | return -EIO; | |
1af135a1 HC |
559 | return 0; |
560 | } | |
561 | ||
10ad34bc MS |
562 | /* |
563 | * Collect CPU state of the previous, crashed system. | |
564 | * There are four cases: | |
565 | * 1) standard zfcp dump | |
566 | * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
567 | * The state for all CPUs except the boot CPU needs to be collected | |
568 | * with sigp stop-and-store-status. The boot CPU state is located in | |
569 | * the absolute lowcore of the memory stored in the HSA. The zcore code | |
1a36a39e | 570 | * will copy the boot CPU state from the HSA. |
10ad34bc MS |
571 | * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory) |
572 | * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
573 | * The state for all CPUs except the boot CPU needs to be collected | |
574 | * with sigp stop-and-store-status. The firmware or the boot-loader | |
575 | * stored the registers of the boot CPU in the absolute lowcore in the | |
576 | * memory of the old system. | |
577 | * 3) kdump and the old kernel did not store the CPU state, | |
578 | * or stand-alone kdump for DASD | |
579 | * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() | |
580 | * The state for all CPUs except the boot CPU needs to be collected | |
581 | * with sigp stop-and-store-status. The kexec code or the boot-loader | |
582 | * stored the registers of the boot CPU in the memory of the old system. | |
583 | * 4) kdump and the old kernel stored the CPU state | |
584 | * condition: OLDMEM_BASE != NULL && is_kdump_kernel() | |
8a07dd02 MS |
585 | * This case does not exist for s390 anymore, setup_arch explicitly |
586 | * deactivates the elfcorehdr= kernel parameter | |
10ad34bc | 587 | */ |
1a2c5840 | 588 | static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, |
1a36a39e MS |
589 | bool is_boot_cpu, unsigned long page) |
590 | { | |
591 | __vector128 *vxrs = (__vector128 *) page; | |
592 | ||
593 | if (is_boot_cpu) | |
594 | vxrs = boot_cpu_vector_save_area; | |
595 | else | |
596 | __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); | |
1a2c5840 | 597 | save_area_add_vxrs(sa, vxrs); |
1a36a39e MS |
598 | } |
599 | ||
1a2c5840 | 600 | static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, |
1a36a39e MS |
601 | bool is_boot_cpu, unsigned long page) |
602 | { | |
603 | void *regs = (void *) page; | |
604 | ||
605 | if (is_boot_cpu) | |
606 | copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); | |
607 | else | |
608 | __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); | |
1a2c5840 | 609 | save_area_add_regs(sa, regs); |
1a36a39e MS |
610 | } |
611 | ||
1592a8e4 | 612 | void __init smp_save_dump_cpus(void) |
10ad34bc | 613 | { |
1a2c5840 MS |
614 | int addr, boot_cpu_addr, max_cpu_addr; |
615 | struct save_area *sa; | |
1a36a39e | 616 | unsigned long page; |
1592a8e4 | 617 | bool is_boot_cpu; |
10ad34bc | 618 | |
10ad34bc MS |
619 | if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP)) |
620 | /* No previous system present, normal boot. */ | |
621 | return; | |
1a36a39e MS |
622 | /* Allocate a page as dumping area for the store status sigps */ |
623 | page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31); | |
10ad34bc | 624 | /* Set multi-threading state to the previous system. */ |
37c5f6c8 | 625 | pcpu_set_smt(sclp.mtid_prev); |
1592a8e4 | 626 | boot_cpu_addr = stap(); |
1a2c5840 MS |
627 | max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; |
628 | for (addr = 0; addr <= max_cpu_addr; addr++) { | |
1a36a39e | 629 | if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == |
1592a8e4 MH |
630 | SIGP_CC_NOT_OPERATIONAL) |
631 | continue; | |
1592a8e4 | 632 | is_boot_cpu = (addr == boot_cpu_addr); |
1a2c5840 MS |
633 | /* Allocate save area */ |
634 | sa = save_area_alloc(is_boot_cpu); | |
635 | if (!sa) | |
636 | panic("could not allocate memory for save area\n"); | |
1a36a39e MS |
637 | if (MACHINE_HAS_VX) |
638 | /* Get the vector registers */ | |
1a2c5840 | 639 | smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page); |
1a36a39e MS |
640 | /* |
641 | * For a zfcp dump OLDMEM_BASE == NULL and the registers | |
642 | * of the boot CPU are stored in the HSA. To retrieve | |
643 | * these registers an SCLP request is required which is | |
644 | * done by drivers/s390/char/zcore.c:init_cpu_info() | |
645 | */ | |
646 | if (!is_boot_cpu || OLDMEM_BASE) | |
647 | /* Get the CPU registers */ | |
1a2c5840 | 648 | smp_save_cpu_regs(sa, addr, is_boot_cpu, page); |
10ad34bc | 649 | } |
1a36a39e | 650 | memblock_free(page, PAGE_SIZE); |
1592a8e4 MH |
651 | diag308_reset(); |
652 | pcpu_set_smt(0); | |
1af135a1 | 653 | } |
1a36a39e | 654 | #endif /* CONFIG_CRASH_DUMP */ |
08d07968 | 655 | |
50ab9a9a HC |
656 | void smp_cpu_set_polarization(int cpu, int val) |
657 | { | |
658 | pcpu_devices[cpu].polarization = val; | |
659 | } | |
660 | ||
661 | int smp_cpu_get_polarization(int cpu) | |
662 | { | |
663 | return pcpu_devices[cpu].polarization; | |
664 | } | |
665 | ||
af51160e | 666 | static void __ref smp_get_core_info(struct sclp_core_info *info, int early) |
08d07968 | 667 | { |
8b646bd7 | 668 | static int use_sigp_detection; |
8b646bd7 MS |
669 | int address; |
670 | ||
af51160e | 671 | if (use_sigp_detection || sclp_get_core_info(info, early)) { |
8b646bd7 | 672 | use_sigp_detection = 1; |
e7086eb1 | 673 | for (address = 0; |
d08d9430 | 674 | address < (SCLP_MAX_CORES << smp_cpu_mt_shift); |
10ad34bc | 675 | address += (1U << smp_cpu_mt_shift)) { |
1a36a39e | 676 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == |
a9ae32c3 | 677 | SIGP_CC_NOT_OPERATIONAL) |
8b646bd7 | 678 | continue; |
d08d9430 | 679 | info->core[info->configured].core_id = |
10ad34bc | 680 | address >> smp_cpu_mt_shift; |
8b646bd7 MS |
681 | info->configured++; |
682 | } | |
683 | info->combined = info->configured; | |
08d07968 | 684 | } |
08d07968 HC |
685 | } |
686 | ||
e2741f17 | 687 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 688 | |
d08d9430 | 689 | static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add) |
08d07968 | 690 | { |
8b646bd7 | 691 | struct pcpu *pcpu; |
08d07968 | 692 | cpumask_t avail; |
10ad34bc MS |
693 | int cpu, nr, i, j; |
694 | u16 address; | |
08d07968 | 695 | |
8b646bd7 | 696 | nr = 0; |
0f1959f5 | 697 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
698 | cpu = cpumask_first(&avail); |
699 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
d08d9430 | 700 | if (sclp.has_core_type && info->core[i].type != boot_core_type) |
8b646bd7 | 701 | continue; |
d08d9430 | 702 | address = info->core[i].core_id << smp_cpu_mt_shift; |
10ad34bc MS |
703 | for (j = 0; j <= smp_cpu_mtid; j++) { |
704 | if (pcpu_find_address(cpu_present_mask, address + j)) | |
705 | continue; | |
706 | pcpu = pcpu_devices + cpu; | |
707 | pcpu->address = address + j; | |
708 | pcpu->state = | |
709 | (cpu >= info->configured*(smp_cpu_mtid + 1)) ? | |
710 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; | |
711 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
712 | set_cpu_present(cpu, true); | |
713 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
714 | set_cpu_present(cpu, false); | |
715 | else | |
716 | nr++; | |
717 | cpu = cpumask_next(cpu, &avail); | |
718 | if (cpu >= nr_cpu_ids) | |
719 | break; | |
720 | } | |
8b646bd7 MS |
721 | } |
722 | return nr; | |
1da177e4 LT |
723 | } |
724 | ||
af51160e | 725 | void __init smp_detect_cpus(void) |
48483b32 | 726 | { |
10ad34bc | 727 | unsigned int cpu, mtid, c_cpus, s_cpus; |
d08d9430 | 728 | struct sclp_core_info *info; |
10ad34bc | 729 | u16 address; |
48483b32 | 730 | |
10ad34bc | 731 | /* Get CPU information */ |
af51160e HC |
732 | info = memblock_virt_alloc(sizeof(*info), 8); |
733 | smp_get_core_info(info, 1); | |
10ad34bc | 734 | /* Find boot CPU type */ |
d08d9430 | 735 | if (sclp.has_core_type) { |
10ad34bc MS |
736 | address = stap(); |
737 | for (cpu = 0; cpu < info->combined; cpu++) | |
d08d9430 | 738 | if (info->core[cpu].core_id == address) { |
10ad34bc | 739 | /* The boot cpu dictates the cpu type. */ |
d08d9430 | 740 | boot_core_type = info->core[cpu].type; |
10ad34bc MS |
741 | break; |
742 | } | |
743 | if (cpu >= info->combined) | |
744 | panic("Could not find boot CPU type"); | |
48483b32 | 745 | } |
10ad34bc | 746 | |
10ad34bc | 747 | /* Set multi-threading state for the current system */ |
d08d9430 | 748 | mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; |
10ad34bc MS |
749 | mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; |
750 | pcpu_set_smt(mtid); | |
751 | ||
752 | /* Print number of CPUs */ | |
8b646bd7 | 753 | c_cpus = s_cpus = 0; |
48483b32 | 754 | for (cpu = 0; cpu < info->combined; cpu++) { |
d08d9430 MS |
755 | if (sclp.has_core_type && |
756 | info->core[cpu].type != boot_core_type) | |
48483b32 | 757 | continue; |
10ad34bc MS |
758 | if (cpu < info->configured) |
759 | c_cpus += smp_cpu_mtid + 1; | |
760 | else | |
761 | s_cpus += smp_cpu_mtid + 1; | |
48483b32 | 762 | } |
395d31d4 | 763 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
10ad34bc MS |
764 | |
765 | /* Add CPUs present at boot */ | |
9d40d2e3 | 766 | get_online_cpus(); |
8b646bd7 | 767 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 768 | put_online_cpus(); |
af51160e | 769 | memblock_free_early((unsigned long)info, sizeof(*info)); |
48483b32 HC |
770 | } |
771 | ||
1da177e4 | 772 | /* |
39ce010d | 773 | * Activate a secondary processor. |
1da177e4 | 774 | */ |
e2741f17 | 775 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 776 | { |
1aae0560 | 777 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
778 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
779 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
780 | S390_lowcore.restart_data = 0; | |
781 | S390_lowcore.restart_source = -1UL; | |
782 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
783 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 784 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 785 | cpu_init(); |
5bfb5d69 | 786 | preempt_disable(); |
39ce010d | 787 | init_cpu_timer(); |
b5f87f15 | 788 | vtime_init(); |
29b08d2b | 789 | pfault_init(); |
e545a614 | 790 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 791 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 792 | inc_irq_stat(CPU_RST); |
1da177e4 | 793 | local_irq_enable(); |
fc6d73d6 | 794 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
795 | } |
796 | ||
1da177e4 | 797 | /* Upping and downing of CPUs */ |
e2741f17 | 798 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 799 | { |
8b646bd7 | 800 | struct pcpu *pcpu; |
10ad34bc | 801 | int base, i, rc; |
1da177e4 | 802 | |
8b646bd7 MS |
803 | pcpu = pcpu_devices + cpu; |
804 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 805 | return -EIO; |
5423145f | 806 | base = smp_get_base_cpu(cpu); |
10ad34bc MS |
807 | for (i = 0; i <= smp_cpu_mtid; i++) { |
808 | if (base + i < nr_cpu_ids) | |
809 | if (cpu_online(base + i)) | |
810 | break; | |
811 | } | |
812 | /* | |
813 | * If this is the first CPU of the core to get online | |
814 | * do an initial CPU reset. | |
815 | */ | |
816 | if (i > smp_cpu_mtid && | |
817 | pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) != | |
a9ae32c3 | 818 | SIGP_CC_ORDER_CODE_ACCEPTED) |
08d07968 | 819 | return -EIO; |
e80e7813 | 820 | |
8b646bd7 MS |
821 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
822 | if (rc) | |
823 | return rc; | |
824 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 825 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 826 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
a1307bba | 827 | /* Wait until cpu puts itself in the online & active maps */ |
e9d867a6 | 828 | while (!cpu_online(cpu)) |
1da177e4 LT |
829 | cpu_relax(); |
830 | return 0; | |
831 | } | |
832 | ||
d80512f8 | 833 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 834 | |
d80512f8 HC |
835 | static int __init _setup_possible_cpus(char *s) |
836 | { | |
837 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
838 | return 0; |
839 | } | |
d80512f8 | 840 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 841 | |
48483b32 HC |
842 | #ifdef CONFIG_HOTPLUG_CPU |
843 | ||
39ce010d | 844 | int __cpu_disable(void) |
1da177e4 | 845 | { |
8b646bd7 | 846 | unsigned long cregs[16]; |
1da177e4 | 847 | |
9acf73b7 HC |
848 | /* Handle possible pending IPIs */ |
849 | smp_handle_ext_call(); | |
8b646bd7 MS |
850 | set_cpu_online(smp_processor_id(), false); |
851 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 852 | pfault_fini(); |
8b646bd7 MS |
853 | /* Disable interrupt sources via control register. */ |
854 | __ctl_store(cregs, 0, 15); | |
855 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
856 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
857 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
858 | __ctl_load(cregs, 0, 15); | |
fe0f4976 | 859 | clear_cpu_flag(CIF_NOHZ_DELAY); |
1da177e4 LT |
860 | return 0; |
861 | } | |
862 | ||
39ce010d | 863 | void __cpu_die(unsigned int cpu) |
1da177e4 | 864 | { |
8b646bd7 MS |
865 | struct pcpu *pcpu; |
866 | ||
1da177e4 | 867 | /* Wait until target cpu is down */ |
8b646bd7 MS |
868 | pcpu = pcpu_devices + cpu; |
869 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 870 | cpu_relax(); |
8b646bd7 | 871 | pcpu_free_lowcore(pcpu); |
1b948d6c | 872 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
64f31d58 | 873 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1da177e4 LT |
874 | } |
875 | ||
b456d94a | 876 | void __noreturn cpu_die(void) |
1da177e4 LT |
877 | { |
878 | idle_task_exit(); | |
a9ae32c3 | 879 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 880 | for (;;) ; |
1da177e4 LT |
881 | } |
882 | ||
255acee7 HC |
883 | #endif /* CONFIG_HOTPLUG_CPU */ |
884 | ||
d80512f8 HC |
885 | void __init smp_fill_possible_mask(void) |
886 | { | |
9747bc47 | 887 | unsigned int possible, sclp_max, cpu; |
d80512f8 | 888 | |
3a9f3fe6 DH |
889 | sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; |
890 | sclp_max = min(smp_max_threads, sclp_max); | |
61282aff | 891 | sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; |
cf813db0 | 892 | possible = setup_possible_cpus ?: nr_cpu_ids; |
9747bc47 | 893 | possible = min(possible, sclp_max); |
d80512f8 HC |
894 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
895 | set_cpu_possible(cpu, true); | |
896 | } | |
897 | ||
1da177e4 LT |
898 | void __init smp_prepare_cpus(unsigned int max_cpus) |
899 | { | |
39ce010d | 900 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 901 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 902 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 903 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 904 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 905 | panic("Couldn't request external interrupt 0x1202"); |
1da177e4 LT |
906 | } |
907 | ||
ea1f4eec | 908 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 909 | { |
8b646bd7 MS |
910 | struct pcpu *pcpu = pcpu_devices; |
911 | ||
8b646bd7 | 912 | pcpu->state = CPU_STATE_CONFIGURED; |
10ad34bc | 913 | pcpu->address = stap(); |
c667aeac | 914 | pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix(); |
1da177e4 | 915 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 916 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
917 | set_cpu_present(0, true); |
918 | set_cpu_online(0, true); | |
1da177e4 LT |
919 | } |
920 | ||
ea1f4eec | 921 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 922 | { |
1da177e4 LT |
923 | } |
924 | ||
02beaccc HC |
925 | void __init smp_setup_processor_id(void) |
926 | { | |
927 | S390_lowcore.cpu_nr = 0; | |
6c8cd5bb | 928 | S390_lowcore.spinlock_lockval = arch_spin_lockval(0); |
02beaccc HC |
929 | } |
930 | ||
1da177e4 LT |
931 | /* |
932 | * the frequency of the profiling timer can be changed | |
933 | * by writing a multiplier value into /proc/profile. | |
934 | * | |
935 | * usually you want to run this on all CPUs ;) | |
936 | */ | |
937 | int setup_profiling_timer(unsigned int multiplier) | |
938 | { | |
39ce010d | 939 | return 0; |
1da177e4 LT |
940 | } |
941 | ||
08d07968 | 942 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 943 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 944 | struct device_attribute *attr, char *buf) |
08d07968 HC |
945 | { |
946 | ssize_t count; | |
947 | ||
948 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 949 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
950 | mutex_unlock(&smp_cpu_state_mutex); |
951 | return count; | |
952 | } | |
953 | ||
8a25a2fd | 954 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
955 | struct device_attribute *attr, |
956 | const char *buf, size_t count) | |
08d07968 | 957 | { |
8b646bd7 | 958 | struct pcpu *pcpu; |
10ad34bc | 959 | int cpu, val, rc, i; |
08d07968 HC |
960 | char delim; |
961 | ||
962 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
963 | return -EINVAL; | |
964 | if (val != 0 && val != 1) | |
965 | return -EINVAL; | |
9d40d2e3 | 966 | get_online_cpus(); |
0b18d318 | 967 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 968 | rc = -EBUSY; |
2c2df118 | 969 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 970 | cpu = dev->id; |
5423145f | 971 | cpu = smp_get_base_cpu(cpu); |
10ad34bc | 972 | if (cpu == 0) |
08d07968 | 973 | goto out; |
10ad34bc MS |
974 | for (i = 0; i <= smp_cpu_mtid; i++) |
975 | if (cpu_online(cpu + i)) | |
976 | goto out; | |
8b646bd7 | 977 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
978 | rc = 0; |
979 | switch (val) { | |
980 | case 0: | |
8b646bd7 MS |
981 | if (pcpu->state != CPU_STATE_CONFIGURED) |
982 | break; | |
d08d9430 | 983 | rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
984 | if (rc) |
985 | break; | |
10ad34bc MS |
986 | for (i = 0; i <= smp_cpu_mtid; i++) { |
987 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
988 | continue; | |
989 | pcpu[i].state = CPU_STATE_STANDBY; | |
990 | smp_cpu_set_polarization(cpu + i, | |
991 | POLARIZATION_UNKNOWN); | |
992 | } | |
8b646bd7 | 993 | topology_expect_change(); |
08d07968 HC |
994 | break; |
995 | case 1: | |
8b646bd7 MS |
996 | if (pcpu->state != CPU_STATE_STANDBY) |
997 | break; | |
d08d9430 | 998 | rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
999 | if (rc) |
1000 | break; | |
10ad34bc MS |
1001 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1002 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1003 | continue; | |
1004 | pcpu[i].state = CPU_STATE_CONFIGURED; | |
1005 | smp_cpu_set_polarization(cpu + i, | |
1006 | POLARIZATION_UNKNOWN); | |
1007 | } | |
8b646bd7 | 1008 | topology_expect_change(); |
08d07968 HC |
1009 | break; |
1010 | default: | |
1011 | break; | |
1012 | } | |
1013 | out: | |
08d07968 | 1014 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1015 | put_online_cpus(); |
08d07968 HC |
1016 | return rc ? rc : count; |
1017 | } | |
8a25a2fd | 1018 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
1019 | #endif /* CONFIG_HOTPLUG_CPU */ |
1020 | ||
8a25a2fd KS |
1021 | static ssize_t show_cpu_address(struct device *dev, |
1022 | struct device_attribute *attr, char *buf) | |
08d07968 | 1023 | { |
8b646bd7 | 1024 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 1025 | } |
8a25a2fd | 1026 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 1027 | |
08d07968 HC |
1028 | static struct attribute *cpu_common_attrs[] = { |
1029 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 1030 | &dev_attr_configure.attr, |
08d07968 | 1031 | #endif |
8a25a2fd | 1032 | &dev_attr_address.attr, |
08d07968 HC |
1033 | NULL, |
1034 | }; | |
1035 | ||
1036 | static struct attribute_group cpu_common_attr_group = { | |
1037 | .attrs = cpu_common_attrs, | |
1038 | }; | |
1da177e4 | 1039 | |
08d07968 | 1040 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1041 | &dev_attr_idle_count.attr, |
1042 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1043 | NULL, |
1044 | }; | |
1045 | ||
08d07968 HC |
1046 | static struct attribute_group cpu_online_attr_group = { |
1047 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1048 | }; |
1049 | ||
dfbbd86a | 1050 | static int smp_cpu_online(unsigned int cpu) |
2fc2d1e9 | 1051 | { |
2f859d0d | 1052 | struct device *s = &per_cpu(cpu_device, cpu)->dev; |
2fc2d1e9 | 1053 | |
dfbbd86a SAS |
1054 | return sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
1055 | } | |
1056 | static int smp_cpu_pre_down(unsigned int cpu) | |
1057 | { | |
1058 | struct device *s = &per_cpu(cpu_device, cpu)->dev; | |
1059 | ||
1060 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1061 | return 0; | |
2fc2d1e9 HC |
1062 | } |
1063 | ||
e2741f17 | 1064 | static int smp_add_present_cpu(int cpu) |
08d07968 | 1065 | { |
96619fc1 HC |
1066 | struct device *s; |
1067 | struct cpu *c; | |
08d07968 HC |
1068 | int rc; |
1069 | ||
96619fc1 HC |
1070 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
1071 | if (!c) | |
1072 | return -ENOMEM; | |
2f859d0d | 1073 | per_cpu(cpu_device, cpu) = c; |
96619fc1 | 1074 | s = &c->dev; |
08d07968 HC |
1075 | c->hotpluggable = 1; |
1076 | rc = register_cpu(c, cpu); | |
1077 | if (rc) | |
1078 | goto out; | |
1079 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1080 | if (rc) | |
1081 | goto out_cpu; | |
83a24e32 HC |
1082 | rc = topology_cpu_init(c); |
1083 | if (rc) | |
1084 | goto out_topology; | |
1085 | return 0; | |
1086 | ||
1087 | out_topology: | |
08d07968 HC |
1088 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1089 | out_cpu: | |
1090 | #ifdef CONFIG_HOTPLUG_CPU | |
1091 | unregister_cpu(c); | |
1092 | #endif | |
1093 | out: | |
1094 | return rc; | |
1095 | } | |
1096 | ||
1097 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1098 | |
67060d9c | 1099 | int __ref smp_rescan_cpus(void) |
08d07968 | 1100 | { |
d08d9430 | 1101 | struct sclp_core_info *info; |
8b646bd7 | 1102 | int nr; |
08d07968 | 1103 | |
af51160e | 1104 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
8b646bd7 MS |
1105 | if (!info) |
1106 | return -ENOMEM; | |
af51160e | 1107 | smp_get_core_info(info, 0); |
9d40d2e3 | 1108 | get_online_cpus(); |
0b18d318 | 1109 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1110 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1111 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1112 | put_online_cpus(); |
8b646bd7 MS |
1113 | kfree(info); |
1114 | if (nr) | |
c10fde0d | 1115 | topology_schedule_update(); |
8b646bd7 | 1116 | return 0; |
1e489518 HC |
1117 | } |
1118 | ||
8a25a2fd KS |
1119 | static ssize_t __ref rescan_store(struct device *dev, |
1120 | struct device_attribute *attr, | |
c9be0a36 | 1121 | const char *buf, |
1e489518 HC |
1122 | size_t count) |
1123 | { | |
1124 | int rc; | |
1125 | ||
1126 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1127 | return rc ? rc : count; |
1128 | } | |
8a25a2fd | 1129 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1130 | #endif /* CONFIG_HOTPLUG_CPU */ |
1131 | ||
83a24e32 | 1132 | static int __init s390_smp_init(void) |
1da177e4 | 1133 | { |
f4edbcd5 | 1134 | int cpu, rc = 0; |
2fc2d1e9 | 1135 | |
08d07968 | 1136 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1137 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1138 | if (rc) |
1139 | return rc; | |
1140 | #endif | |
1141 | for_each_present_cpu(cpu) { | |
1142 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1143 | if (rc) |
f4edbcd5 | 1144 | goto out; |
1da177e4 | 1145 | } |
f4edbcd5 | 1146 | |
dfbbd86a SAS |
1147 | rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", |
1148 | smp_cpu_online, smp_cpu_pre_down); | |
f4edbcd5 | 1149 | out: |
f4edbcd5 | 1150 | return rc; |
1da177e4 | 1151 | } |
83a24e32 | 1152 | subsys_initcall(s390_smp_init); |