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Commit | Line | Data |
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1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
8b646bd7 MS |
4 | * Copyright IBM Corp. 1999,2012 |
5 | * Author(s): Denis Joseph Barrow, | |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
46b05d26 | 35 | #include <asm/ipl.h> |
2b67fc46 | 36 | #include <asm/setup.h> |
1da177e4 | 37 | #include <asm/irq.h> |
1da177e4 | 38 | #include <asm/tlbflush.h> |
2b67fc46 | 39 | #include <asm/timer.h> |
411ed322 | 40 | #include <asm/lowcore.h> |
08d07968 | 41 | #include <asm/sclp.h> |
c742b31c | 42 | #include <asm/vdso.h> |
a806170e | 43 | #include "entry.h" |
1da177e4 | 44 | |
8b646bd7 MS |
45 | enum { |
46 | sigp_sense = 1, | |
47 | sigp_external_call = 2, | |
48 | sigp_emergency_signal = 3, | |
49 | sigp_start = 4, | |
50 | sigp_stop = 5, | |
51 | sigp_restart = 6, | |
52 | sigp_stop_and_store_status = 9, | |
53 | sigp_initial_cpu_reset = 11, | |
54 | sigp_cpu_reset = 12, | |
55 | sigp_set_prefix = 13, | |
56 | sigp_store_status_at_address = 14, | |
57 | sigp_store_extended_status_at_address = 15, | |
58 | sigp_set_architecture = 18, | |
59 | sigp_conditional_emergency_signal = 19, | |
60 | sigp_sense_running = 21, | |
61 | }; | |
fb380aad | 62 | |
8b646bd7 MS |
63 | enum { |
64 | sigp_order_code_accepted = 0, | |
65 | sigp_status_stored = 1, | |
66 | sigp_busy = 2, | |
67 | sigp_not_operational = 3, | |
68 | }; | |
1da177e4 | 69 | |
8b646bd7 MS |
70 | enum { |
71 | ec_schedule = 0, | |
72 | ec_call_function, | |
73 | ec_call_function_single, | |
74 | ec_stop_cpu, | |
75 | }; | |
08d07968 | 76 | |
8b646bd7 | 77 | enum { |
08d07968 HC |
78 | CPU_STATE_STANDBY, |
79 | CPU_STATE_CONFIGURED, | |
80 | }; | |
81 | ||
8b646bd7 MS |
82 | struct pcpu { |
83 | struct cpu cpu; | |
84 | struct task_struct *idle; /* idle process for the cpu */ | |
85 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ | |
86 | unsigned long async_stack; /* async stack for the cpu */ | |
87 | unsigned long panic_stack; /* panic stack for the cpu */ | |
88 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
89 | int state; /* physical cpu state */ | |
90 | u32 status; /* last status received via sigp */ | |
91 | u16 address; /* physical cpu address */ | |
92 | }; | |
93 | ||
94 | static u8 boot_cpu_type; | |
95 | static u16 boot_cpu_address; | |
96 | static struct pcpu pcpu_devices[NR_CPUS]; | |
97 | ||
dbd70fb4 | 98 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 99 | |
8b646bd7 MS |
100 | /* |
101 | * Signal processor helper functions. | |
102 | */ | |
103 | static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status) | |
104 | { | |
105 | register unsigned int reg1 asm ("1") = parm; | |
106 | int cc; | |
08d07968 | 107 | |
8b646bd7 MS |
108 | asm volatile( |
109 | " sigp %1,%2,0(%3)\n" | |
110 | " ipm %0\n" | |
111 | " srl %0,28\n" | |
112 | : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); | |
113 | if (status && cc == 1) | |
114 | *status = reg1; | |
115 | return cc; | |
116 | } | |
1da177e4 | 117 | |
8b646bd7 | 118 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 119 | { |
8b646bd7 | 120 | int cc; |
5c0b912e | 121 | |
8b646bd7 MS |
122 | while (1) { |
123 | cc = __pcpu_sigp(addr, order, parm, status); | |
124 | if (cc != sigp_busy) | |
125 | return cc; | |
126 | cpu_relax(); | |
5c0b912e | 127 | } |
5c0b912e HC |
128 | } |
129 | ||
8b646bd7 | 130 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 131 | { |
8b646bd7 MS |
132 | int cc, retry; |
133 | ||
134 | for (retry = 0; ; retry++) { | |
135 | cc = __pcpu_sigp(pcpu->address, order, parm, &pcpu->status); | |
136 | if (cc != sigp_busy) | |
137 | break; | |
138 | if (retry >= 3) | |
139 | udelay(10); | |
140 | } | |
141 | return cc; | |
142 | } | |
143 | ||
144 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
145 | { | |
146 | if (__pcpu_sigp(pcpu->address, sigp_sense, | |
147 | 0, &pcpu->status) != sigp_status_stored) | |
148 | return 0; | |
149 | /* Check for stopped and check stop state */ | |
150 | return !!(pcpu->status & 0x50); | |
151 | } | |
152 | ||
153 | static inline int pcpu_running(struct pcpu *pcpu) | |
154 | { | |
155 | if (__pcpu_sigp(pcpu->address, sigp_sense_running, | |
156 | 0, &pcpu->status) != sigp_status_stored) | |
157 | return 1; | |
158 | /* Check for running status */ | |
159 | return !(pcpu->status & 0x400); | |
a93b8ec1 HC |
160 | } |
161 | ||
1943f53c | 162 | /* |
8b646bd7 | 163 | * Find struct pcpu by cpu address. |
1943f53c | 164 | */ |
8b646bd7 | 165 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
166 | { |
167 | int cpu; | |
168 | ||
8b646bd7 MS |
169 | for_each_cpu(cpu, mask) |
170 | if (pcpu_devices[cpu].address == address) | |
171 | return pcpu_devices + cpu; | |
172 | return NULL; | |
173 | } | |
174 | ||
175 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
176 | { | |
177 | int order; | |
178 | ||
179 | set_bit(ec_bit, &pcpu->ec_mask); | |
180 | order = pcpu_running(pcpu) ? | |
181 | sigp_external_call : sigp_emergency_signal; | |
182 | pcpu_sigp_retry(pcpu, order, 0); | |
183 | } | |
184 | ||
185 | static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) | |
186 | { | |
187 | struct _lowcore *lc; | |
188 | ||
189 | if (pcpu != &pcpu_devices[0]) { | |
190 | pcpu->lowcore = (struct _lowcore *) | |
191 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
192 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
193 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
194 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
195 | goto out; | |
1943f53c | 196 | } |
8b646bd7 MS |
197 | lc = pcpu->lowcore; |
198 | memcpy(lc, &S390_lowcore, 512); | |
199 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
200 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE; | |
201 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE; | |
202 | lc->cpu_nr = cpu; | |
203 | #ifndef CONFIG_64BIT | |
204 | if (MACHINE_HAS_IEEE) { | |
205 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
206 | if (!lc->extended_save_area_addr) | |
207 | goto out; | |
208 | } | |
209 | #else | |
210 | if (vdso_alloc_per_cpu(lc)) | |
211 | goto out; | |
212 | #endif | |
213 | lowcore_ptr[cpu] = lc; | |
214 | pcpu_sigp_retry(pcpu, sigp_set_prefix, (u32)(unsigned long) lc); | |
215 | return 0; | |
216 | out: | |
217 | if (pcpu != &pcpu_devices[0]) { | |
218 | free_page(pcpu->panic_stack); | |
219 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
220 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
221 | } | |
222 | return -ENOMEM; | |
1943f53c MH |
223 | } |
224 | ||
8b646bd7 | 225 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 226 | { |
8b646bd7 MS |
227 | pcpu_sigp_retry(pcpu, sigp_set_prefix, 0); |
228 | lowcore_ptr[pcpu - pcpu_devices] = NULL; | |
229 | #ifndef CONFIG_64BIT | |
230 | if (MACHINE_HAS_IEEE) { | |
231 | struct _lowcore *lc = pcpu->lowcore; | |
232 | ||
233 | free_page((unsigned long) lc->extended_save_area_addr); | |
234 | lc->extended_save_area_addr = 0; | |
235 | } | |
236 | #else | |
237 | vdso_free_per_cpu(pcpu->lowcore); | |
238 | #endif | |
239 | if (pcpu != &pcpu_devices[0]) { | |
240 | free_page(pcpu->panic_stack); | |
241 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
242 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
243 | } | |
244 | } | |
245 | ||
246 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) | |
247 | { | |
248 | struct _lowcore *lc = pcpu->lowcore; | |
249 | ||
250 | atomic_inc(&init_mm.context.attach_count); | |
251 | lc->cpu_nr = cpu; | |
252 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
253 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
254 | lc->machine_flags = S390_lowcore.machine_flags; | |
255 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
256 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
257 | __ctl_store(lc->cregs_save_area, 0, 15); | |
258 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
259 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
260 | MAX_FACILITY_BIT/8); | |
261 | } | |
262 | ||
263 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
264 | { | |
265 | struct _lowcore *lc = pcpu->lowcore; | |
266 | struct thread_info *ti = task_thread_info(tsk); | |
267 | ||
268 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) + THREAD_SIZE; | |
269 | lc->thread_info = (unsigned long) task_thread_info(tsk); | |
270 | lc->current_task = (unsigned long) tsk; | |
271 | lc->user_timer = ti->user_timer; | |
272 | lc->system_timer = ti->system_timer; | |
273 | lc->steal_timer = 0; | |
274 | } | |
275 | ||
276 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
277 | { | |
278 | struct _lowcore *lc = pcpu->lowcore; | |
279 | ||
280 | lc->restart_stack = lc->kernel_stack; | |
281 | lc->restart_fn = (unsigned long) func; | |
282 | lc->restart_data = (unsigned long) data; | |
283 | lc->restart_source = -1UL; | |
284 | pcpu_sigp_retry(pcpu, sigp_restart, 0); | |
285 | } | |
286 | ||
287 | /* | |
288 | * Call function via PSW restart on pcpu and stop the current cpu. | |
289 | */ | |
290 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
291 | void *data, unsigned long stack) | |
292 | { | |
293 | struct _lowcore *lc = pcpu->lowcore; | |
294 | unsigned short this_cpu; | |
295 | ||
296 | __load_psw_mask(psw_kernel_bits); | |
297 | this_cpu = stap(); | |
298 | if (pcpu->address == this_cpu) | |
299 | func(data); /* should not return */ | |
300 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
301 | pcpu_sigp_retry(pcpu, sigp_stop, 0); | |
302 | /* Restart func on the target cpu and stop the current cpu. */ | |
303 | lc->restart_stack = stack; | |
304 | lc->restart_fn = (unsigned long) func; | |
305 | lc->restart_data = (unsigned long) data; | |
306 | lc->restart_source = (unsigned long) this_cpu; | |
307 | asm volatile( | |
308 | "0: sigp 0,%0,6 # sigp restart to target cpu\n" | |
309 | " brc 2,0b # busy, try again\n" | |
310 | "1: sigp 0,%1,5 # sigp stop to current cpu\n" | |
311 | " brc 2,1b # busy, try again\n" | |
312 | : : "d" (pcpu->address), "d" (this_cpu) : "0", "1", "cc"); | |
313 | for (;;) ; | |
314 | } | |
315 | ||
316 | /* | |
317 | * Call function on an online CPU. | |
318 | */ | |
319 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
320 | { | |
321 | struct pcpu *pcpu; | |
322 | ||
323 | /* Use the current cpu if it is online. */ | |
324 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
325 | if (!pcpu) | |
326 | /* Use the first online cpu. */ | |
327 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
328 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
329 | } | |
330 | ||
331 | /* | |
332 | * Call function on the ipl CPU. | |
333 | */ | |
334 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
335 | { | |
336 | pcpu_delegate(&pcpu_devices[0], func, data, pcpu_devices->panic_stack); | |
337 | } | |
338 | ||
339 | int smp_find_processor_id(u16 address) | |
340 | { | |
341 | int cpu; | |
342 | ||
343 | for_each_present_cpu(cpu) | |
344 | if (pcpu_devices[cpu].address == address) | |
345 | return cpu; | |
346 | return -1; | |
2c2df118 HC |
347 | } |
348 | ||
8b646bd7 | 349 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 350 | { |
8b646bd7 MS |
351 | return pcpu_running(pcpu_devices + cpu); |
352 | } | |
353 | ||
354 | void smp_yield(void) | |
355 | { | |
356 | if (MACHINE_HAS_DIAG44) | |
357 | asm volatile("diag 0,0,0x44"); | |
358 | } | |
359 | ||
360 | void smp_yield_cpu(int cpu) | |
361 | { | |
362 | if (MACHINE_HAS_DIAG9C) | |
363 | asm volatile("diag %0,0,0x9c" | |
364 | : : "d" (pcpu_devices[cpu].address)); | |
365 | else if (MACHINE_HAS_DIAG44) | |
366 | asm volatile("diag 0,0,0x44"); | |
367 | } | |
368 | ||
369 | /* | |
370 | * Send cpus emergency shutdown signal. This gives the cpus the | |
371 | * opportunity to complete outstanding interrupts. | |
372 | */ | |
373 | void smp_emergency_stop(cpumask_t *cpumask) | |
374 | { | |
375 | u64 end; | |
376 | int cpu; | |
377 | ||
378 | end = get_clock() + (1000000UL << 12); | |
379 | for_each_cpu(cpu, cpumask) { | |
380 | struct pcpu *pcpu = pcpu_devices + cpu; | |
381 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
382 | while (__pcpu_sigp(pcpu->address, sigp_emergency_signal, | |
383 | 0, NULL) == sigp_busy && | |
384 | get_clock() < end) | |
385 | cpu_relax(); | |
386 | } | |
387 | while (get_clock() < end) { | |
388 | for_each_cpu(cpu, cpumask) | |
389 | if (pcpu_stopped(pcpu_devices + cpu)) | |
390 | cpumask_clear_cpu(cpu, cpumask); | |
391 | if (cpumask_empty(cpumask)) | |
392 | break; | |
85ac7ca5 | 393 | cpu_relax(); |
8b646bd7 | 394 | } |
85ac7ca5 MS |
395 | } |
396 | ||
8b646bd7 MS |
397 | /* |
398 | * Stop all cpus but the current one. | |
399 | */ | |
677d7623 | 400 | void smp_send_stop(void) |
1da177e4 | 401 | { |
85ac7ca5 MS |
402 | cpumask_t cpumask; |
403 | int cpu; | |
1da177e4 | 404 | |
677d7623 | 405 | /* Disable all interrupts/machine checks */ |
b50511e4 | 406 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 407 | trace_hardirqs_off(); |
1da177e4 | 408 | |
85ac7ca5 MS |
409 | cpumask_copy(&cpumask, cpu_online_mask); |
410 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
411 | ||
8b646bd7 MS |
412 | if (oops_in_progress) |
413 | smp_emergency_stop(&cpumask); | |
1da177e4 | 414 | |
85ac7ca5 MS |
415 | /* stop all processors */ |
416 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 MS |
417 | struct pcpu *pcpu = pcpu_devices + cpu; |
418 | pcpu_sigp_retry(pcpu, sigp_stop, 0); | |
419 | while (!pcpu_stopped(pcpu)) | |
c6b5b847 HC |
420 | cpu_relax(); |
421 | } | |
422 | } | |
423 | ||
8b646bd7 MS |
424 | /* |
425 | * Stop the current cpu. | |
426 | */ | |
427 | void smp_stop_cpu(void) | |
428 | { | |
429 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0); | |
430 | for (;;) ; | |
431 | } | |
432 | ||
1da177e4 LT |
433 | /* |
434 | * This is the main routine where commands issued by other | |
435 | * cpus are handled. | |
436 | */ | |
f6649a7e MS |
437 | static void do_ext_call_interrupt(unsigned int ext_int_code, |
438 | unsigned int param32, unsigned long param64) | |
1da177e4 | 439 | { |
39ce010d | 440 | unsigned long bits; |
8b646bd7 | 441 | int cpu; |
1da177e4 | 442 | |
8b646bd7 | 443 | cpu = smp_processor_id(); |
272f01bf | 444 | if ((ext_int_code & 0xffff) == 0x1202) |
8b646bd7 | 445 | kstat_cpu(cpu).irqs[EXTINT_EXC]++; |
2a3a2d66 | 446 | else |
8b646bd7 | 447 | kstat_cpu(cpu).irqs[EXTINT_EMS]++; |
39ce010d HC |
448 | /* |
449 | * handle bit signal external calls | |
39ce010d | 450 | */ |
8b646bd7 | 451 | bits = xchg(&pcpu_devices[cpu].ec_mask, 0); |
1da177e4 | 452 | |
85ac7ca5 MS |
453 | if (test_bit(ec_stop_cpu, &bits)) |
454 | smp_stop_cpu(); | |
455 | ||
184748cc PZ |
456 | if (test_bit(ec_schedule, &bits)) |
457 | scheduler_ipi(); | |
458 | ||
39ce010d | 459 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
460 | generic_smp_call_function_interrupt(); |
461 | ||
462 | if (test_bit(ec_call_function_single, &bits)) | |
463 | generic_smp_call_function_single_interrupt(); | |
85ac7ca5 | 464 | |
1da177e4 LT |
465 | } |
466 | ||
630cd046 | 467 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
468 | { |
469 | int cpu; | |
470 | ||
630cd046 | 471 | for_each_cpu(cpu, mask) |
8b646bd7 | 472 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function); |
ca9fc75a HC |
473 | } |
474 | ||
475 | void arch_send_call_function_single_ipi(int cpu) | |
476 | { | |
8b646bd7 | 477 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
478 | } |
479 | ||
347a8dc3 | 480 | #ifndef CONFIG_64BIT |
1da177e4 LT |
481 | /* |
482 | * this function sends a 'purge tlb' signal to another CPU. | |
483 | */ | |
a806170e | 484 | static void smp_ptlb_callback(void *info) |
1da177e4 | 485 | { |
ba8a9229 | 486 | __tlb_flush_local(); |
1da177e4 LT |
487 | } |
488 | ||
489 | void smp_ptlb_all(void) | |
490 | { | |
15c8b6c1 | 491 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
492 | } |
493 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 494 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
495 | |
496 | /* | |
497 | * this function sends a 'reschedule' IPI to another CPU. | |
498 | * it goes straight through and wastes no time serializing | |
499 | * anything. Worst case is that we lose a reschedule ... | |
500 | */ | |
501 | void smp_send_reschedule(int cpu) | |
502 | { | |
8b646bd7 | 503 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
504 | } |
505 | ||
506 | /* | |
507 | * parameter area for the set/clear control bit callbacks | |
508 | */ | |
94c12cc7 | 509 | struct ec_creg_mask_parms { |
8b646bd7 MS |
510 | unsigned long orval; |
511 | unsigned long andval; | |
512 | int cr; | |
94c12cc7 | 513 | }; |
1da177e4 LT |
514 | |
515 | /* | |
516 | * callback for setting/clearing control bits | |
517 | */ | |
39ce010d HC |
518 | static void smp_ctl_bit_callback(void *info) |
519 | { | |
94c12cc7 | 520 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 521 | unsigned long cregs[16]; |
39ce010d | 522 | |
94c12cc7 | 523 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 524 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 525 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
526 | } |
527 | ||
528 | /* | |
529 | * Set a bit in a control register of all cpus | |
530 | */ | |
94c12cc7 MS |
531 | void smp_ctl_set_bit(int cr, int bit) |
532 | { | |
8b646bd7 | 533 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 534 | |
15c8b6c1 | 535 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 536 | } |
39ce010d | 537 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
538 | |
539 | /* | |
540 | * Clear a bit in a control register of all cpus | |
541 | */ | |
94c12cc7 MS |
542 | void smp_ctl_clear_bit(int cr, int bit) |
543 | { | |
8b646bd7 | 544 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 545 | |
15c8b6c1 | 546 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 547 | } |
39ce010d | 548 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 549 | |
60a0c68d | 550 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 551 | |
8b646bd7 MS |
552 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
553 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
554 | ||
555 | static void __init smp_get_save_area(int cpu, u16 address) | |
411ed322 | 556 | { |
8b646bd7 MS |
557 | void *lc = pcpu_devices[0].lowcore; |
558 | struct save_area *save_area; | |
559 | ||
60a0c68d | 560 | if (is_kdump_kernel()) |
411ed322 | 561 | return; |
8b646bd7 MS |
562 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
563 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
564 | return; | |
285f6722 | 565 | if (cpu >= NR_CPUS) { |
8b646bd7 MS |
566 | pr_warning("CPU %i exceeds the maximum %i and is excluded " |
567 | "from the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 568 | return; |
411ed322 | 569 | } |
8b646bd7 MS |
570 | save_area = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
571 | if (!save_area) | |
572 | panic("could not allocate memory for save area\n"); | |
573 | zfcpdump_save_areas[cpu] = save_area; | |
574 | #ifdef CONFIG_CRASH_DUMP | |
575 | if (address == boot_cpu_address) { | |
576 | /* Copy the registers of the boot cpu. */ | |
577 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
578 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
579 | return; | |
580 | } | |
581 | #endif | |
582 | /* Get the registers of a non-boot cpu. */ | |
583 | __pcpu_sigp_relax(address, sigp_stop_and_store_status, 0, NULL); | |
584 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); | |
411ed322 MH |
585 | } |
586 | ||
8b646bd7 | 587 | int smp_store_status(int cpu) |
08d07968 | 588 | { |
8b646bd7 | 589 | struct pcpu *pcpu; |
08d07968 | 590 | |
8b646bd7 MS |
591 | pcpu = pcpu_devices + cpu; |
592 | if (__pcpu_sigp_relax(pcpu->address, sigp_stop_and_store_status, | |
593 | 0, NULL) != sigp_order_code_accepted) | |
594 | return -EIO; | |
08d07968 HC |
595 | return 0; |
596 | } | |
597 | ||
8b646bd7 | 598 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 599 | |
8b646bd7 MS |
600 | static inline void smp_get_save_area(int cpu, u16 address) { } |
601 | ||
602 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ | |
08d07968 | 603 | |
8b646bd7 | 604 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 605 | { |
8b646bd7 | 606 | static int use_sigp_detection; |
08d07968 | 607 | struct sclp_cpu_info *info; |
8b646bd7 MS |
608 | int address; |
609 | ||
610 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
611 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
612 | use_sigp_detection = 1; | |
613 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
614 | if (__pcpu_sigp_relax(address, sigp_sense, 0, NULL) == | |
615 | sigp_not_operational) | |
616 | continue; | |
617 | info->cpu[info->configured].address = address; | |
618 | info->configured++; | |
619 | } | |
620 | info->combined = info->configured; | |
08d07968 | 621 | } |
8b646bd7 | 622 | return info; |
08d07968 HC |
623 | } |
624 | ||
8b646bd7 MS |
625 | static int __devinit smp_add_present_cpu(int cpu); |
626 | ||
627 | static int __devinit __smp_rescan_cpus(struct sclp_cpu_info *info, | |
628 | int sysfs_add) | |
08d07968 | 629 | { |
8b646bd7 | 630 | struct pcpu *pcpu; |
08d07968 | 631 | cpumask_t avail; |
8b646bd7 | 632 | int cpu, nr, i; |
08d07968 | 633 | |
8b646bd7 | 634 | nr = 0; |
0f1959f5 | 635 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
636 | cpu = cpumask_first(&avail); |
637 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
638 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
639 | continue; | |
640 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
641 | continue; | |
642 | pcpu = pcpu_devices + cpu; | |
643 | pcpu->address = info->cpu[i].address; | |
644 | pcpu->state = (cpu >= info->configured) ? | |
645 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; | |
646 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
647 | set_cpu_present(cpu, true); | |
648 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
649 | set_cpu_present(cpu, false); | |
650 | else | |
651 | nr++; | |
652 | cpu = cpumask_next(cpu, &avail); | |
653 | } | |
654 | return nr; | |
1da177e4 LT |
655 | } |
656 | ||
48483b32 HC |
657 | static void __init smp_detect_cpus(void) |
658 | { | |
659 | unsigned int cpu, c_cpus, s_cpus; | |
660 | struct sclp_cpu_info *info; | |
48483b32 | 661 | |
8b646bd7 | 662 | info = smp_get_cpu_info(); |
48483b32 HC |
663 | if (!info) |
664 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
665 | if (info->has_cpu_type) { |
666 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
667 | if (info->cpu[cpu].address != boot_cpu_address) |
668 | continue; | |
669 | /* The boot cpu dictates the cpu type. */ | |
670 | boot_cpu_type = info->cpu[cpu].type; | |
671 | break; | |
48483b32 HC |
672 | } |
673 | } | |
8b646bd7 | 674 | c_cpus = s_cpus = 0; |
48483b32 | 675 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 676 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 677 | continue; |
8b646bd7 MS |
678 | if (cpu < info->configured) { |
679 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
680 | c_cpus++; | |
681 | } else | |
48483b32 | 682 | s_cpus++; |
48483b32 | 683 | } |
395d31d4 | 684 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 685 | get_online_cpus(); |
8b646bd7 | 686 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 687 | put_online_cpus(); |
8b646bd7 | 688 | kfree(info); |
48483b32 HC |
689 | } |
690 | ||
1da177e4 | 691 | /* |
39ce010d | 692 | * Activate a secondary processor. |
1da177e4 | 693 | */ |
8b646bd7 | 694 | static void __cpuinit smp_start_secondary(void *cpuvoid) |
1da177e4 | 695 | { |
8b646bd7 MS |
696 | S390_lowcore.last_update_clock = get_clock(); |
697 | S390_lowcore.restart_stack = (unsigned long) restart_stack; | |
698 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
699 | S390_lowcore.restart_data = 0; | |
700 | S390_lowcore.restart_source = -1UL; | |
701 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
702 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
703 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); | |
39ce010d | 704 | cpu_init(); |
5bfb5d69 | 705 | preempt_disable(); |
39ce010d | 706 | init_cpu_timer(); |
39ce010d | 707 | init_cpu_vtimer(); |
29b08d2b | 708 | pfault_init(); |
e545a614 | 709 | notify_cpu_starting(smp_processor_id()); |
ca9fc75a | 710 | ipi_call_lock(); |
0f1959f5 | 711 | set_cpu_online(smp_processor_id(), true); |
ca9fc75a | 712 | ipi_call_unlock(); |
cc34321d HC |
713 | /* |
714 | * Wait until the cpu which brought this one up marked it | |
715 | * active before enabling interrupts. | |
716 | */ | |
717 | while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask)) | |
718 | cpu_relax(); | |
1da177e4 | 719 | local_irq_enable(); |
39ce010d HC |
720 | /* cpu_idle will call schedule for us */ |
721 | cpu_idle(); | |
1da177e4 LT |
722 | } |
723 | ||
f230886b HC |
724 | struct create_idle { |
725 | struct work_struct work; | |
726 | struct task_struct *idle; | |
727 | struct completion done; | |
728 | int cpu; | |
729 | }; | |
730 | ||
731 | static void __cpuinit smp_fork_idle(struct work_struct *work) | |
1da177e4 | 732 | { |
f230886b | 733 | struct create_idle *c_idle; |
1da177e4 | 734 | |
f230886b HC |
735 | c_idle = container_of(work, struct create_idle, work); |
736 | c_idle->idle = fork_idle(c_idle->cpu); | |
737 | complete(&c_idle->done); | |
1da177e4 LT |
738 | } |
739 | ||
1da177e4 | 740 | /* Upping and downing of CPUs */ |
1cb6bb4b | 741 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 | 742 | { |
f230886b | 743 | struct create_idle c_idle; |
8b646bd7 MS |
744 | struct pcpu *pcpu; |
745 | int rc; | |
1da177e4 | 746 | |
8b646bd7 MS |
747 | pcpu = pcpu_devices + cpu; |
748 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 749 | return -EIO; |
8b646bd7 MS |
750 | if (pcpu_sigp_retry(pcpu, sigp_initial_cpu_reset, 0) != |
751 | sigp_order_code_accepted) | |
752 | return -EIO; | |
753 | if (!pcpu->idle) { | |
f230886b HC |
754 | c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done); |
755 | INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle); | |
756 | c_idle.cpu = cpu; | |
757 | schedule_work(&c_idle.work); | |
758 | wait_for_completion(&c_idle.done); | |
759 | if (IS_ERR(c_idle.idle)) | |
760 | return PTR_ERR(c_idle.idle); | |
8b646bd7 | 761 | pcpu->idle = c_idle.idle; |
f230886b | 762 | } |
8b646bd7 MS |
763 | init_idle(pcpu->idle, cpu); |
764 | rc = pcpu_alloc_lowcore(pcpu, cpu); | |
765 | if (rc) | |
766 | return rc; | |
767 | pcpu_prepare_secondary(pcpu, cpu); | |
768 | pcpu_attach_task(pcpu, pcpu->idle); | |
769 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); | |
1da177e4 LT |
770 | while (!cpu_online(cpu)) |
771 | cpu_relax(); | |
772 | return 0; | |
773 | } | |
774 | ||
48483b32 | 775 | static int __init setup_possible_cpus(char *s) |
255acee7 | 776 | { |
8b646bd7 | 777 | int max, cpu; |
255acee7 | 778 | |
8b646bd7 MS |
779 | if (kstrtoint(s, 0, &max) < 0) |
780 | return 0; | |
88e01285 | 781 | init_cpu_possible(cpumask_of(0)); |
8b646bd7 | 782 | for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++) |
def6cfb7 | 783 | set_cpu_possible(cpu, true); |
37a33026 HC |
784 | return 0; |
785 | } | |
786 | early_param("possible_cpus", setup_possible_cpus); | |
787 | ||
48483b32 HC |
788 | #ifdef CONFIG_HOTPLUG_CPU |
789 | ||
39ce010d | 790 | int __cpu_disable(void) |
1da177e4 | 791 | { |
8b646bd7 | 792 | unsigned long cregs[16]; |
1da177e4 | 793 | |
8b646bd7 MS |
794 | set_cpu_online(smp_processor_id(), false); |
795 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 796 | pfault_fini(); |
8b646bd7 MS |
797 | /* Disable interrupt sources via control register. */ |
798 | __ctl_store(cregs, 0, 15); | |
799 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
800 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
801 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
802 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
803 | return 0; |
804 | } | |
805 | ||
39ce010d | 806 | void __cpu_die(unsigned int cpu) |
1da177e4 | 807 | { |
8b646bd7 MS |
808 | struct pcpu *pcpu; |
809 | ||
1da177e4 | 810 | /* Wait until target cpu is down */ |
8b646bd7 MS |
811 | pcpu = pcpu_devices + cpu; |
812 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 813 | cpu_relax(); |
8b646bd7 | 814 | pcpu_free_lowcore(pcpu); |
050eef36 | 815 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
816 | } |
817 | ||
b456d94a | 818 | void __noreturn cpu_die(void) |
1da177e4 LT |
819 | { |
820 | idle_task_exit(); | |
8b646bd7 MS |
821 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0); |
822 | for (;;) ; | |
1da177e4 LT |
823 | } |
824 | ||
255acee7 HC |
825 | #endif /* CONFIG_HOTPLUG_CPU */ |
826 | ||
1da177e4 LT |
827 | void __init smp_prepare_cpus(unsigned int max_cpus) |
828 | { | |
39ce010d HC |
829 | /* request the 0x1201 emergency signal external interrupt */ |
830 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
831 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
832 | /* request the 0x1202 external call external interrupt */ |
833 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
834 | panic("Couldn't request external interrupt 0x1202"); | |
8b646bd7 | 835 | smp_detect_cpus(); |
1da177e4 LT |
836 | } |
837 | ||
ea1f4eec | 838 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 839 | { |
8b646bd7 MS |
840 | struct pcpu *pcpu = pcpu_devices; |
841 | ||
842 | boot_cpu_address = stap(); | |
843 | pcpu->idle = current; | |
844 | pcpu->state = CPU_STATE_CONFIGURED; | |
845 | pcpu->address = boot_cpu_address; | |
846 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
847 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE; | |
848 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE; | |
1da177e4 | 849 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
83a24e32 | 850 | cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
851 | set_cpu_present(0, true); |
852 | set_cpu_online(0, true); | |
1da177e4 LT |
853 | } |
854 | ||
ea1f4eec | 855 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 856 | { |
1da177e4 LT |
857 | } |
858 | ||
02beaccc HC |
859 | void __init smp_setup_processor_id(void) |
860 | { | |
861 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
862 | } |
863 | ||
1da177e4 LT |
864 | /* |
865 | * the frequency of the profiling timer can be changed | |
866 | * by writing a multiplier value into /proc/profile. | |
867 | * | |
868 | * usually you want to run this on all CPUs ;) | |
869 | */ | |
870 | int setup_profiling_timer(unsigned int multiplier) | |
871 | { | |
39ce010d | 872 | return 0; |
1da177e4 LT |
873 | } |
874 | ||
08d07968 | 875 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 876 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 877 | struct device_attribute *attr, char *buf) |
08d07968 HC |
878 | { |
879 | ssize_t count; | |
880 | ||
881 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 882 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
883 | mutex_unlock(&smp_cpu_state_mutex); |
884 | return count; | |
885 | } | |
886 | ||
8a25a2fd | 887 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
888 | struct device_attribute *attr, |
889 | const char *buf, size_t count) | |
08d07968 | 890 | { |
8b646bd7 MS |
891 | struct pcpu *pcpu; |
892 | int cpu, val, rc; | |
08d07968 HC |
893 | char delim; |
894 | ||
895 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
896 | return -EINVAL; | |
897 | if (val != 0 && val != 1) | |
898 | return -EINVAL; | |
9d40d2e3 | 899 | get_online_cpus(); |
0b18d318 | 900 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 901 | rc = -EBUSY; |
2c2df118 | 902 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 903 | cpu = dev->id; |
2c2df118 | 904 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 905 | goto out; |
8b646bd7 | 906 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
907 | rc = 0; |
908 | switch (val) { | |
909 | case 0: | |
8b646bd7 MS |
910 | if (pcpu->state != CPU_STATE_CONFIGURED) |
911 | break; | |
912 | rc = sclp_cpu_deconfigure(pcpu->address); | |
913 | if (rc) | |
914 | break; | |
915 | pcpu->state = CPU_STATE_STANDBY; | |
916 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
917 | topology_expect_change(); | |
08d07968 HC |
918 | break; |
919 | case 1: | |
8b646bd7 MS |
920 | if (pcpu->state != CPU_STATE_STANDBY) |
921 | break; | |
922 | rc = sclp_cpu_configure(pcpu->address); | |
923 | if (rc) | |
924 | break; | |
925 | pcpu->state = CPU_STATE_CONFIGURED; | |
926 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
927 | topology_expect_change(); | |
08d07968 HC |
928 | break; |
929 | default: | |
930 | break; | |
931 | } | |
932 | out: | |
08d07968 | 933 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 934 | put_online_cpus(); |
08d07968 HC |
935 | return rc ? rc : count; |
936 | } | |
8a25a2fd | 937 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
938 | #endif /* CONFIG_HOTPLUG_CPU */ |
939 | ||
8a25a2fd KS |
940 | static ssize_t show_cpu_address(struct device *dev, |
941 | struct device_attribute *attr, char *buf) | |
08d07968 | 942 | { |
8b646bd7 | 943 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 944 | } |
8a25a2fd | 945 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 946 | |
08d07968 HC |
947 | static struct attribute *cpu_common_attrs[] = { |
948 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 949 | &dev_attr_configure.attr, |
08d07968 | 950 | #endif |
8a25a2fd | 951 | &dev_attr_address.attr, |
08d07968 HC |
952 | NULL, |
953 | }; | |
954 | ||
955 | static struct attribute_group cpu_common_attr_group = { | |
956 | .attrs = cpu_common_attrs, | |
957 | }; | |
1da177e4 | 958 | |
8a25a2fd KS |
959 | static ssize_t show_capability(struct device *dev, |
960 | struct device_attribute *attr, char *buf) | |
2fc2d1e9 HC |
961 | { |
962 | unsigned int capability; | |
963 | int rc; | |
964 | ||
965 | rc = get_cpu_capability(&capability); | |
966 | if (rc) | |
967 | return rc; | |
968 | return sprintf(buf, "%u\n", capability); | |
969 | } | |
8a25a2fd | 970 | static DEVICE_ATTR(capability, 0444, show_capability, NULL); |
2fc2d1e9 | 971 | |
8a25a2fd KS |
972 | static ssize_t show_idle_count(struct device *dev, |
973 | struct device_attribute *attr, char *buf) | |
fae8b22d HC |
974 | { |
975 | struct s390_idle_data *idle; | |
976 | unsigned long long idle_count; | |
e98bbaaf | 977 | unsigned int sequence; |
fae8b22d HC |
978 | |
979 | idle = &per_cpu(s390_idle, dev->id); | |
e98bbaaf MS |
980 | repeat: |
981 | sequence = idle->sequence; | |
982 | smp_rmb(); | |
983 | if (sequence & 1) | |
984 | goto repeat; | |
fae8b22d | 985 | idle_count = idle->idle_count; |
6f430924 MS |
986 | if (idle->idle_enter) |
987 | idle_count++; | |
e98bbaaf MS |
988 | smp_rmb(); |
989 | if (idle->sequence != sequence) | |
990 | goto repeat; | |
fae8b22d HC |
991 | return sprintf(buf, "%llu\n", idle_count); |
992 | } | |
8a25a2fd | 993 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 994 | |
8a25a2fd KS |
995 | static ssize_t show_idle_time(struct device *dev, |
996 | struct device_attribute *attr, char *buf) | |
fae8b22d HC |
997 | { |
998 | struct s390_idle_data *idle; | |
6f430924 | 999 | unsigned long long now, idle_time, idle_enter; |
e98bbaaf | 1000 | unsigned int sequence; |
fae8b22d HC |
1001 | |
1002 | idle = &per_cpu(s390_idle, dev->id); | |
6f430924 | 1003 | now = get_clock(); |
e98bbaaf MS |
1004 | repeat: |
1005 | sequence = idle->sequence; | |
1006 | smp_rmb(); | |
1007 | if (sequence & 1) | |
1008 | goto repeat; | |
6f430924 MS |
1009 | idle_time = idle->idle_time; |
1010 | idle_enter = idle->idle_enter; | |
1011 | if (idle_enter != 0ULL && idle_enter < now) | |
1012 | idle_time += now - idle_enter; | |
e98bbaaf MS |
1013 | smp_rmb(); |
1014 | if (idle->sequence != sequence) | |
1015 | goto repeat; | |
6f430924 | 1016 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 1017 | } |
8a25a2fd | 1018 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 1019 | |
08d07968 | 1020 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1021 | &dev_attr_capability.attr, |
1022 | &dev_attr_idle_count.attr, | |
1023 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1024 | NULL, |
1025 | }; | |
1026 | ||
08d07968 HC |
1027 | static struct attribute_group cpu_online_attr_group = { |
1028 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1029 | }; |
1030 | ||
2fc2d1e9 HC |
1031 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
1032 | unsigned long action, void *hcpu) | |
1033 | { | |
1034 | unsigned int cpu = (unsigned int)(long)hcpu; | |
8b646bd7 | 1035 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 1036 | struct device *s = &c->dev; |
fae8b22d | 1037 | struct s390_idle_data *idle; |
d882ba69 | 1038 | int err = 0; |
2fc2d1e9 HC |
1039 | |
1040 | switch (action) { | |
1041 | case CPU_ONLINE: | |
8bb78442 | 1042 | case CPU_ONLINE_FROZEN: |
fae8b22d | 1043 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 1044 | memset(idle, 0, sizeof(struct s390_idle_data)); |
d882ba69 | 1045 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1046 | break; |
1047 | case CPU_DEAD: | |
8bb78442 | 1048 | case CPU_DEAD_FROZEN: |
08d07968 | 1049 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1050 | break; |
1051 | } | |
d882ba69 | 1052 | return notifier_from_errno(err); |
2fc2d1e9 HC |
1053 | } |
1054 | ||
1055 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 1056 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
1057 | }; |
1058 | ||
2bc89b5e | 1059 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 | 1060 | { |
8b646bd7 | 1061 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 1062 | struct device *s = &c->dev; |
08d07968 HC |
1063 | int rc; |
1064 | ||
1065 | c->hotpluggable = 1; | |
1066 | rc = register_cpu(c, cpu); | |
1067 | if (rc) | |
1068 | goto out; | |
1069 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1070 | if (rc) | |
1071 | goto out_cpu; | |
83a24e32 HC |
1072 | if (cpu_online(cpu)) { |
1073 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1074 | if (rc) | |
1075 | goto out_online; | |
1076 | } | |
1077 | rc = topology_cpu_init(c); | |
1078 | if (rc) | |
1079 | goto out_topology; | |
1080 | return 0; | |
1081 | ||
1082 | out_topology: | |
1083 | if (cpu_online(cpu)) | |
1084 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1085 | out_online: | |
08d07968 HC |
1086 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1087 | out_cpu: | |
1088 | #ifdef CONFIG_HOTPLUG_CPU | |
1089 | unregister_cpu(c); | |
1090 | #endif | |
1091 | out: | |
1092 | return rc; | |
1093 | } | |
1094 | ||
1095 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1096 | |
67060d9c | 1097 | int __ref smp_rescan_cpus(void) |
08d07968 | 1098 | { |
8b646bd7 MS |
1099 | struct sclp_cpu_info *info; |
1100 | int nr; | |
08d07968 | 1101 | |
8b646bd7 MS |
1102 | info = smp_get_cpu_info(); |
1103 | if (!info) | |
1104 | return -ENOMEM; | |
9d40d2e3 | 1105 | get_online_cpus(); |
0b18d318 | 1106 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1107 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1108 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1109 | put_online_cpus(); |
8b646bd7 MS |
1110 | kfree(info); |
1111 | if (nr) | |
c10fde0d | 1112 | topology_schedule_update(); |
8b646bd7 | 1113 | return 0; |
1e489518 HC |
1114 | } |
1115 | ||
8a25a2fd KS |
1116 | static ssize_t __ref rescan_store(struct device *dev, |
1117 | struct device_attribute *attr, | |
c9be0a36 | 1118 | const char *buf, |
1e489518 HC |
1119 | size_t count) |
1120 | { | |
1121 | int rc; | |
1122 | ||
1123 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1124 | return rc ? rc : count; |
1125 | } | |
8a25a2fd | 1126 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1127 | #endif /* CONFIG_HOTPLUG_CPU */ |
1128 | ||
83a24e32 | 1129 | static int __init s390_smp_init(void) |
1da177e4 | 1130 | { |
83a24e32 | 1131 | int cpu, rc; |
2fc2d1e9 HC |
1132 | |
1133 | register_cpu_notifier(&smp_cpu_nb); | |
08d07968 | 1134 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1135 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1136 | if (rc) |
1137 | return rc; | |
1138 | #endif | |
1139 | for_each_present_cpu(cpu) { | |
1140 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1141 | if (rc) |
1142 | return rc; | |
1da177e4 LT |
1143 | } |
1144 | return 0; | |
1145 | } | |
83a24e32 | 1146 | subsys_initcall(s390_smp_init); |