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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
8b646bd7 3 * SMP related functions
1da177e4 4 *
a53c8fab 5 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
6 * Author(s): Denis Joseph Barrow,
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
8 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 9 *
39ce010d 10 * based on other smp stuff by
1da177e4
LT
11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
12 * (c) 1998 Ingo Molnar
13 *
8b646bd7
MS
14 * The code outside of smp.c uses logical cpu numbers, only smp.c does
15 * the translation of logical to physical cpu ids. All new code that
16 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
17 */
18
395d31d4
MS
19#define KMSG_COMPONENT "cpu"
20#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
f230886b 22#include <linux/workqueue.h>
af51160e 23#include <linux/bootmem.h>
3994a52b 24#include <linux/export.h>
1da177e4 25#include <linux/init.h>
1da177e4 26#include <linux/mm.h>
4e950f6f 27#include <linux/err.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/kernel_stat.h>
9cf8edb7 30#include <linux/kmemleak.h>
1da177e4 31#include <linux/delay.h>
1da177e4 32#include <linux/interrupt.h>
3324e60a 33#include <linux/irqflags.h>
1da177e4 34#include <linux/cpu.h>
5a0e3ad6 35#include <linux/slab.h>
ef8bd77f 36#include <linux/sched/hotplug.h>
68db0cf1 37#include <linux/sched/task_stack.h>
60a0c68d 38#include <linux/crash_dump.h>
1592a8e4 39#include <linux/memblock.h>
cbb870c8 40#include <asm/asm-offsets.h>
1ec2772e 41#include <asm/diag.h>
1e3cab2f
HC
42#include <asm/switch_to.h>
43#include <asm/facility.h>
46b05d26 44#include <asm/ipl.h>
2b67fc46 45#include <asm/setup.h>
1da177e4 46#include <asm/irq.h>
1da177e4 47#include <asm/tlbflush.h>
27f6b416 48#include <asm/vtimer.h>
411ed322 49#include <asm/lowcore.h>
08d07968 50#include <asm/sclp.h>
c742b31c 51#include <asm/vdso.h>
3ab121ab 52#include <asm/debug.h>
4857d4bb 53#include <asm/os_info.h>
a9ae32c3 54#include <asm/sigp.h>
b5f87f15 55#include <asm/idle.h>
916cda1a 56#include <asm/nmi.h>
a806170e 57#include "entry.h"
1da177e4 58
8b646bd7
MS
59enum {
60 ec_schedule = 0,
8b646bd7
MS
61 ec_call_function_single,
62 ec_stop_cpu,
63};
08d07968 64
8b646bd7 65enum {
08d07968
HC
66 CPU_STATE_STANDBY,
67 CPU_STATE_CONFIGURED,
68};
69
2f859d0d
HC
70static DEFINE_PER_CPU(struct cpu *, cpu_device);
71
8b646bd7 72struct pcpu {
c667aeac 73 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 74 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 75 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
76 signed char state; /* physical cpu state */
77 signed char polarization; /* physical polarization */
8b646bd7
MS
78 u16 address; /* physical cpu address */
79};
80
d08d9430 81static u8 boot_core_type;
8b646bd7
MS
82static struct pcpu pcpu_devices[NR_CPUS];
83
916cda1a
MS
84static struct kmem_cache *pcpu_mcesa_cache;
85
10ad34bc
MS
86unsigned int smp_cpu_mt_shift;
87EXPORT_SYMBOL(smp_cpu_mt_shift);
88
89unsigned int smp_cpu_mtid;
90EXPORT_SYMBOL(smp_cpu_mtid);
91
1a36a39e
MS
92#ifdef CONFIG_CRASH_DUMP
93__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
94#endif
95
10ad34bc
MS
96static unsigned int smp_max_threads __initdata = -1U;
97
98static int __init early_nosmt(char *s)
99{
100 smp_max_threads = 1;
101 return 0;
102}
103early_param("nosmt", early_nosmt);
104
105static int __init early_smt(char *s)
106{
107 get_option(&s, &smp_max_threads);
108 return 0;
109}
110early_param("smt", early_smt);
111
50ab9a9a
HC
112/*
113 * The smp_cpu_state_mutex must be held when changing the state or polarization
114 * member of a pcpu data structure within the pcpu_devices arreay.
115 */
dbd70fb4 116DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 117
8b646bd7
MS
118/*
119 * Signal processor helper functions.
120 */
1a36a39e 121static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 122{
8b646bd7 123 int cc;
5c0b912e 124
8b646bd7 125 while (1) {
c5e3acd6 126 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 127 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
128 return cc;
129 cpu_relax();
5c0b912e 130 }
5c0b912e
HC
131}
132
8b646bd7 133static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 134{
8b646bd7
MS
135 int cc, retry;
136
137 for (retry = 0; ; retry++) {
c5e3acd6 138 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 139 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
140 break;
141 if (retry >= 3)
142 udelay(10);
143 }
144 return cc;
145}
146
147static inline int pcpu_stopped(struct pcpu *pcpu)
148{
41459d36 149 u32 uninitialized_var(status);
c5e3acd6 150
a9ae32c3 151 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 152 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 153 return 0;
c5e3acd6 154 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
155}
156
157static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 158{
a9ae32c3 159 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 160 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 161 return 1;
524b24ad
HC
162 /* Status stored condition code is equivalent to cpu not running. */
163 return 0;
a93b8ec1
HC
164}
165
1943f53c 166/*
8b646bd7 167 * Find struct pcpu by cpu address.
1943f53c 168 */
10ad34bc 169static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
170{
171 int cpu;
172
8b646bd7
MS
173 for_each_cpu(cpu, mask)
174 if (pcpu_devices[cpu].address == address)
175 return pcpu_devices + cpu;
176 return NULL;
177}
178
179static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
180{
181 int order;
182
dea24190
HC
183 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
184 return;
185 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 186 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
187 pcpu_sigp_retry(pcpu, order, 0);
188}
189
2f859d0d
HC
190#define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
191#define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
192
e2741f17 193static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 194{
2f859d0d 195 unsigned long async_stack, panic_stack;
916cda1a 196 unsigned long mcesa_origin, mcesa_bits;
c667aeac 197 struct lowcore *lc;
8b646bd7 198
916cda1a 199 mcesa_origin = mcesa_bits = 0;
8b646bd7 200 if (pcpu != &pcpu_devices[0]) {
c667aeac 201 pcpu->lowcore = (struct lowcore *)
8b646bd7 202 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
2f859d0d
HC
203 async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
204 panic_stack = __get_free_page(GFP_KERNEL);
205 if (!pcpu->lowcore || !panic_stack || !async_stack)
8b646bd7 206 goto out;
916cda1a
MS
207 if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
208 mcesa_origin = (unsigned long)
209 kmem_cache_alloc(pcpu_mcesa_cache, GFP_KERNEL);
210 if (!mcesa_origin)
211 goto out;
9cf8edb7
CB
212 /* The pointer is stored with mcesa_bits ORed in */
213 kmemleak_not_leak((void *) mcesa_origin);
916cda1a
MS
214 mcesa_bits = MACHINE_HAS_GS ? 11 : 0;
215 }
2f859d0d
HC
216 } else {
217 async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
218 panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
916cda1a
MS
219 mcesa_origin = pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK;
220 mcesa_bits = pcpu->lowcore->mcesad & MCESA_LC_MASK;
1943f53c 221 }
8b646bd7
MS
222 lc = pcpu->lowcore;
223 memcpy(lc, &S390_lowcore, 512);
224 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
2f859d0d
HC
225 lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
226 lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
916cda1a 227 lc->mcesad = mcesa_origin | mcesa_bits;
8b646bd7 228 lc->cpu_nr = cpu;
6c8cd5bb 229 lc->spinlock_lockval = arch_spin_lockval(cpu);
8b646bd7
MS
230 if (vdso_alloc_per_cpu(lc))
231 goto out;
8b646bd7 232 lowcore_ptr[cpu] = lc;
a9ae32c3 233 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7
MS
234 return 0;
235out:
236 if (pcpu != &pcpu_devices[0]) {
916cda1a
MS
237 if (mcesa_origin)
238 kmem_cache_free(pcpu_mcesa_cache,
239 (void *) mcesa_origin);
2f859d0d
HC
240 free_page(panic_stack);
241 free_pages(async_stack, ASYNC_ORDER);
8b646bd7
MS
242 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
243 }
244 return -ENOMEM;
1943f53c
MH
245}
246
9d0f46af
HC
247#ifdef CONFIG_HOTPLUG_CPU
248
8b646bd7 249static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 250{
916cda1a
MS
251 unsigned long mcesa_origin;
252
a9ae32c3 253 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 254 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 255 vdso_free_per_cpu(pcpu->lowcore);
2f859d0d
HC
256 if (pcpu == &pcpu_devices[0])
257 return;
916cda1a
MS
258 if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
259 mcesa_origin = pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK;
260 kmem_cache_free(pcpu_mcesa_cache, (void *) mcesa_origin);
261 }
2f859d0d
HC
262 free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
263 free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
264 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
8b646bd7
MS
265}
266
9d0f46af
HC
267#endif /* CONFIG_HOTPLUG_CPU */
268
8b646bd7
MS
269static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
270{
c667aeac 271 struct lowcore *lc = pcpu->lowcore;
8b646bd7 272
64f31d58 273 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 274 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 275 lc->cpu_nr = cpu;
6c8cd5bb 276 lc->spinlock_lockval = arch_spin_lockval(cpu);
8b646bd7
MS
277 lc->percpu_offset = __per_cpu_offset[cpu];
278 lc->kernel_asce = S390_lowcore.kernel_asce;
279 lc->machine_flags = S390_lowcore.machine_flags;
8b646bd7
MS
280 lc->user_timer = lc->system_timer = lc->steal_timer = 0;
281 __ctl_store(lc->cregs_save_area, 0, 15);
282 save_access_regs((unsigned int *) lc->access_regs_save_area);
283 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
284 MAX_FACILITY_BIT/8);
285}
286
287static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
288{
c667aeac 289 struct lowcore *lc = pcpu->lowcore;
8b646bd7 290
dc7ee00d
MS
291 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
292 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 293 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
294 lc->lpp = LPP_MAGIC;
295 lc->current_pid = tsk->pid;
90c53e65 296 lc->user_timer = tsk->thread.user_timer;
b7662eef 297 lc->guest_timer = tsk->thread.guest_timer;
90c53e65 298 lc->system_timer = tsk->thread.system_timer;
b7662eef
CB
299 lc->hardirq_timer = tsk->thread.hardirq_timer;
300 lc->softirq_timer = tsk->thread.softirq_timer;
8b646bd7
MS
301 lc->steal_timer = 0;
302}
303
304static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
305{
c667aeac 306 struct lowcore *lc = pcpu->lowcore;
8b646bd7
MS
307
308 lc->restart_stack = lc->kernel_stack;
309 lc->restart_fn = (unsigned long) func;
310 lc->restart_data = (unsigned long) data;
311 lc->restart_source = -1UL;
a9ae32c3 312 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
313}
314
315/*
316 * Call function via PSW restart on pcpu and stop the current cpu.
317 */
318static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
319 void *data, unsigned long stack)
320{
c667aeac 321 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 322 unsigned long source_cpu = stap();
8b646bd7 323
e258d719 324 __load_psw_mask(PSW_KERNEL_BITS);
fbe76568 325 if (pcpu->address == source_cpu)
8b646bd7
MS
326 func(data); /* should not return */
327 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 328 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 329 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
330 mem_assign_absolute(lc->restart_stack, stack);
331 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
332 mem_assign_absolute(lc->restart_data, (unsigned long) data);
333 mem_assign_absolute(lc->restart_source, source_cpu);
8b646bd7 334 asm volatile(
eb546195 335 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 336 " brc 2,0b # busy, try again\n"
eb546195 337 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 338 " brc 2,1b # busy, try again\n"
fbe76568 339 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
340 "K" (SIGP_RESTART), "K" (SIGP_STOP)
341 : "0", "1", "cc");
8b646bd7
MS
342 for (;;) ;
343}
344
10ad34bc
MS
345/*
346 * Enable additional logical cpus for multi-threading.
347 */
348static int pcpu_set_smt(unsigned int mtid)
349{
10ad34bc
MS
350 int cc;
351
352 if (smp_cpu_mtid == mtid)
353 return 0;
80a60f6e 354 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
355 if (cc == 0) {
356 smp_cpu_mtid = mtid;
357 smp_cpu_mt_shift = 0;
358 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
359 smp_cpu_mt_shift++;
360 pcpu_devices[0].address = stap();
361 }
362 return cc;
363}
364
8b646bd7
MS
365/*
366 * Call function on an online CPU.
367 */
368void smp_call_online_cpu(void (*func)(void *), void *data)
369{
370 struct pcpu *pcpu;
371
372 /* Use the current cpu if it is online. */
373 pcpu = pcpu_find_address(cpu_online_mask, stap());
374 if (!pcpu)
375 /* Use the first online cpu. */
376 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
377 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
378}
379
380/*
381 * Call function on the ipl CPU.
382 */
383void smp_call_ipl_cpu(void (*func)(void *), void *data)
384{
c6da39f2 385 pcpu_delegate(&pcpu_devices[0], func, data,
2f859d0d
HC
386 pcpu_devices->lowcore->panic_stack -
387 PANIC_FRAME_OFFSET + PAGE_SIZE);
8b646bd7
MS
388}
389
390int smp_find_processor_id(u16 address)
391{
392 int cpu;
393
394 for_each_present_cpu(cpu)
395 if (pcpu_devices[cpu].address == address)
396 return cpu;
397 return -1;
2c2df118
HC
398}
399
760928c0 400bool arch_vcpu_is_preempted(int cpu)
85ac7ca5 401{
760928c0
CB
402 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
403 return false;
404 if (pcpu_running(pcpu_devices + cpu))
405 return false;
406 return true;
8b646bd7 407}
760928c0 408EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 409
8b646bd7 410void smp_yield_cpu(int cpu)
85ac7ca5 411{
1ec2772e 412 if (MACHINE_HAS_DIAG9C) {
b5a6b71b 413 diag_stat_inc_norecursion(DIAG_STAT_X09C);
8b646bd7
MS
414 asm volatile("diag %0,0,0x9c"
415 : : "d" (pcpu_devices[cpu].address));
1ec2772e 416 } else if (MACHINE_HAS_DIAG44) {
b5a6b71b 417 diag_stat_inc_norecursion(DIAG_STAT_X044);
8b646bd7 418 asm volatile("diag 0,0,0x44");
1ec2772e 419 }
8b646bd7
MS
420}
421
422/*
423 * Send cpus emergency shutdown signal. This gives the cpus the
424 * opportunity to complete outstanding interrupts.
425 */
63df41d6 426static void smp_emergency_stop(cpumask_t *cpumask)
8b646bd7
MS
427{
428 u64 end;
429 int cpu;
430
1aae0560 431 end = get_tod_clock() + (1000000UL << 12);
8b646bd7
MS
432 for_each_cpu(cpu, cpumask) {
433 struct pcpu *pcpu = pcpu_devices + cpu;
434 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
435 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
436 0, NULL) == SIGP_CC_BUSY &&
1aae0560 437 get_tod_clock() < end)
8b646bd7
MS
438 cpu_relax();
439 }
1aae0560 440 while (get_tod_clock() < end) {
8b646bd7
MS
441 for_each_cpu(cpu, cpumask)
442 if (pcpu_stopped(pcpu_devices + cpu))
443 cpumask_clear_cpu(cpu, cpumask);
444 if (cpumask_empty(cpumask))
445 break;
85ac7ca5 446 cpu_relax();
8b646bd7 447 }
85ac7ca5
MS
448}
449
8b646bd7
MS
450/*
451 * Stop all cpus but the current one.
452 */
677d7623 453void smp_send_stop(void)
1da177e4 454{
85ac7ca5
MS
455 cpumask_t cpumask;
456 int cpu;
1da177e4 457
677d7623 458 /* Disable all interrupts/machine checks */
e258d719 459 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 460 trace_hardirqs_off();
1da177e4 461
3ab121ab 462 debug_set_critical();
85ac7ca5
MS
463 cpumask_copy(&cpumask, cpu_online_mask);
464 cpumask_clear_cpu(smp_processor_id(), &cpumask);
465
8b646bd7
MS
466 if (oops_in_progress)
467 smp_emergency_stop(&cpumask);
1da177e4 468
85ac7ca5
MS
469 /* stop all processors */
470 for_each_cpu(cpu, &cpumask) {
8b646bd7 471 struct pcpu *pcpu = pcpu_devices + cpu;
a9ae32c3 472 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 473 while (!pcpu_stopped(pcpu))
c6b5b847
HC
474 cpu_relax();
475 }
476}
477
1da177e4
LT
478/*
479 * This is the main routine where commands issued by other
480 * cpus are handled.
481 */
9acf73b7 482static void smp_handle_ext_call(void)
1da177e4 483{
39ce010d 484 unsigned long bits;
1da177e4 485
9acf73b7
HC
486 /* handle bit signal external calls */
487 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
488 if (test_bit(ec_stop_cpu, &bits))
489 smp_stop_cpu();
184748cc
PZ
490 if (test_bit(ec_schedule, &bits))
491 scheduler_ipi();
ca9fc75a
HC
492 if (test_bit(ec_call_function_single, &bits))
493 generic_smp_call_function_single_interrupt();
9acf73b7 494}
85ac7ca5 495
9acf73b7
HC
496static void do_ext_call_interrupt(struct ext_code ext_code,
497 unsigned int param32, unsigned long param64)
498{
499 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
500 smp_handle_ext_call();
1da177e4
LT
501}
502
630cd046 503void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
504{
505 int cpu;
506
630cd046 507 for_each_cpu(cpu, mask)
b6ed49e0 508 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
509}
510
511void arch_send_call_function_single_ipi(int cpu)
512{
8b646bd7 513 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
514}
515
1da177e4
LT
516/*
517 * this function sends a 'reschedule' IPI to another CPU.
518 * it goes straight through and wastes no time serializing
519 * anything. Worst case is that we lose a reschedule ...
520 */
521void smp_send_reschedule(int cpu)
522{
8b646bd7 523 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
524}
525
526/*
527 * parameter area for the set/clear control bit callbacks
528 */
94c12cc7 529struct ec_creg_mask_parms {
8b646bd7
MS
530 unsigned long orval;
531 unsigned long andval;
532 int cr;
94c12cc7 533};
1da177e4
LT
534
535/*
536 * callback for setting/clearing control bits
537 */
39ce010d
HC
538static void smp_ctl_bit_callback(void *info)
539{
94c12cc7 540 struct ec_creg_mask_parms *pp = info;
1da177e4 541 unsigned long cregs[16];
39ce010d 542
94c12cc7 543 __ctl_store(cregs, 0, 15);
8b646bd7 544 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 545 __ctl_load(cregs, 0, 15);
1da177e4
LT
546}
547
548/*
549 * Set a bit in a control register of all cpus
550 */
94c12cc7
MS
551void smp_ctl_set_bit(int cr, int bit)
552{
8b646bd7 553 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 554
15c8b6c1 555 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 556}
39ce010d 557EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
558
559/*
560 * Clear a bit in a control register of all cpus
561 */
94c12cc7
MS
562void smp_ctl_clear_bit(int cr, int bit)
563{
8b646bd7 564 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 565
15c8b6c1 566 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 567}
39ce010d 568EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 569
bf28a597 570#ifdef CONFIG_CRASH_DUMP
411ed322 571
1af135a1
HC
572int smp_store_status(int cpu)
573{
1a36a39e
MS
574 struct pcpu *pcpu = pcpu_devices + cpu;
575 unsigned long pa;
1af135a1 576
1a36a39e
MS
577 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
578 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
579 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1 580 return -EIO;
916cda1a 581 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
1af135a1 582 return 0;
916cda1a
MS
583 pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
584 if (MACHINE_HAS_GS)
585 pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
1a36a39e
MS
586 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
587 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
588 return -EIO;
1af135a1
HC
589 return 0;
590}
591
10ad34bc
MS
592/*
593 * Collect CPU state of the previous, crashed system.
594 * There are four cases:
595 * 1) standard zfcp dump
596 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
597 * The state for all CPUs except the boot CPU needs to be collected
598 * with sigp stop-and-store-status. The boot CPU state is located in
599 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 600 * will copy the boot CPU state from the HSA.
10ad34bc
MS
601 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
602 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
603 * The state for all CPUs except the boot CPU needs to be collected
604 * with sigp stop-and-store-status. The firmware or the boot-loader
605 * stored the registers of the boot CPU in the absolute lowcore in the
606 * memory of the old system.
607 * 3) kdump and the old kernel did not store the CPU state,
608 * or stand-alone kdump for DASD
609 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
610 * The state for all CPUs except the boot CPU needs to be collected
611 * with sigp stop-and-store-status. The kexec code or the boot-loader
612 * stored the registers of the boot CPU in the memory of the old system.
613 * 4) kdump and the old kernel stored the CPU state
614 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
615 * This case does not exist for s390 anymore, setup_arch explicitly
616 * deactivates the elfcorehdr= kernel parameter
10ad34bc 617 */
1a2c5840 618static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
619 bool is_boot_cpu, unsigned long page)
620{
621 __vector128 *vxrs = (__vector128 *) page;
622
623 if (is_boot_cpu)
624 vxrs = boot_cpu_vector_save_area;
625 else
626 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 627 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
628}
629
1a2c5840 630static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
631 bool is_boot_cpu, unsigned long page)
632{
633 void *regs = (void *) page;
634
635 if (is_boot_cpu)
636 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
637 else
638 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 639 save_area_add_regs(sa, regs);
1a36a39e
MS
640}
641
1592a8e4 642void __init smp_save_dump_cpus(void)
10ad34bc 643{
1a2c5840
MS
644 int addr, boot_cpu_addr, max_cpu_addr;
645 struct save_area *sa;
1a36a39e 646 unsigned long page;
1592a8e4 647 bool is_boot_cpu;
10ad34bc 648
10ad34bc
MS
649 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
650 /* No previous system present, normal boot. */
651 return;
1a36a39e
MS
652 /* Allocate a page as dumping area for the store status sigps */
653 page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
10ad34bc 654 /* Set multi-threading state to the previous system. */
37c5f6c8 655 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 656 boot_cpu_addr = stap();
1a2c5840
MS
657 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
658 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 659 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
660 SIGP_CC_NOT_OPERATIONAL)
661 continue;
1592a8e4 662 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
663 /* Allocate save area */
664 sa = save_area_alloc(is_boot_cpu);
665 if (!sa)
666 panic("could not allocate memory for save area\n");
1a36a39e
MS
667 if (MACHINE_HAS_VX)
668 /* Get the vector registers */
1a2c5840 669 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
670 /*
671 * For a zfcp dump OLDMEM_BASE == NULL and the registers
672 * of the boot CPU are stored in the HSA. To retrieve
673 * these registers an SCLP request is required which is
674 * done by drivers/s390/char/zcore.c:init_cpu_info()
675 */
676 if (!is_boot_cpu || OLDMEM_BASE)
677 /* Get the CPU registers */
1a2c5840 678 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 679 }
1a36a39e 680 memblock_free(page, PAGE_SIZE);
1592a8e4
MH
681 diag308_reset();
682 pcpu_set_smt(0);
1af135a1 683}
1a36a39e 684#endif /* CONFIG_CRASH_DUMP */
08d07968 685
50ab9a9a
HC
686void smp_cpu_set_polarization(int cpu, int val)
687{
688 pcpu_devices[cpu].polarization = val;
689}
690
691int smp_cpu_get_polarization(int cpu)
692{
693 return pcpu_devices[cpu].polarization;
694}
695
af51160e 696static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 697{
8b646bd7 698 static int use_sigp_detection;
8b646bd7
MS
699 int address;
700
af51160e 701 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 702 use_sigp_detection = 1;
e7086eb1 703 for (address = 0;
d08d9430 704 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 705 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 706 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 707 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 708 continue;
d08d9430 709 info->core[info->configured].core_id =
10ad34bc 710 address >> smp_cpu_mt_shift;
8b646bd7
MS
711 info->configured++;
712 }
713 info->combined = info->configured;
08d07968 714 }
08d07968
HC
715}
716
e2741f17 717static int smp_add_present_cpu(int cpu);
8b646bd7 718
d08d9430 719static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 720{
8b646bd7 721 struct pcpu *pcpu;
08d07968 722 cpumask_t avail;
10ad34bc
MS
723 int cpu, nr, i, j;
724 u16 address;
08d07968 725
8b646bd7 726 nr = 0;
0f1959f5 727 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
728 cpu = cpumask_first(&avail);
729 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 730 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 731 continue;
d08d9430 732 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
733 for (j = 0; j <= smp_cpu_mtid; j++) {
734 if (pcpu_find_address(cpu_present_mask, address + j))
735 continue;
736 pcpu = pcpu_devices + cpu;
737 pcpu->address = address + j;
738 pcpu->state =
739 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
740 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
741 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
742 set_cpu_present(cpu, true);
743 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
744 set_cpu_present(cpu, false);
745 else
746 nr++;
747 cpu = cpumask_next(cpu, &avail);
748 if (cpu >= nr_cpu_ids)
749 break;
750 }
8b646bd7
MS
751 }
752 return nr;
1da177e4
LT
753}
754
af51160e 755void __init smp_detect_cpus(void)
48483b32 756{
10ad34bc 757 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 758 struct sclp_core_info *info;
10ad34bc 759 u16 address;
48483b32 760
10ad34bc 761 /* Get CPU information */
af51160e
HC
762 info = memblock_virt_alloc(sizeof(*info), 8);
763 smp_get_core_info(info, 1);
10ad34bc 764 /* Find boot CPU type */
d08d9430 765 if (sclp.has_core_type) {
10ad34bc
MS
766 address = stap();
767 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 768 if (info->core[cpu].core_id == address) {
10ad34bc 769 /* The boot cpu dictates the cpu type. */
d08d9430 770 boot_core_type = info->core[cpu].type;
10ad34bc
MS
771 break;
772 }
773 if (cpu >= info->combined)
774 panic("Could not find boot CPU type");
48483b32 775 }
10ad34bc 776
10ad34bc 777 /* Set multi-threading state for the current system */
d08d9430 778 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
779 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
780 pcpu_set_smt(mtid);
781
782 /* Print number of CPUs */
8b646bd7 783 c_cpus = s_cpus = 0;
48483b32 784 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
785 if (sclp.has_core_type &&
786 info->core[cpu].type != boot_core_type)
48483b32 787 continue;
10ad34bc
MS
788 if (cpu < info->configured)
789 c_cpus += smp_cpu_mtid + 1;
790 else
791 s_cpus += smp_cpu_mtid + 1;
48483b32 792 }
395d31d4 793 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
794
795 /* Add CPUs present at boot */
9d40d2e3 796 get_online_cpus();
8b646bd7 797 __smp_rescan_cpus(info, 0);
9d40d2e3 798 put_online_cpus();
af51160e 799 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
800}
801
1da177e4 802/*
39ce010d 803 * Activate a secondary processor.
1da177e4 804 */
e2741f17 805static void smp_start_secondary(void *cpuvoid)
1da177e4 806{
1aae0560 807 S390_lowcore.last_update_clock = get_tod_clock();
8b646bd7
MS
808 S390_lowcore.restart_stack = (unsigned long) restart_stack;
809 S390_lowcore.restart_fn = (unsigned long) do_restart;
810 S390_lowcore.restart_data = 0;
811 S390_lowcore.restart_source = -1UL;
812 restore_access_regs(S390_lowcore.access_regs_save_area);
813 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
e258d719 814 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
39ce010d 815 cpu_init();
5bfb5d69 816 preempt_disable();
39ce010d 817 init_cpu_timer();
b5f87f15 818 vtime_init();
29b08d2b 819 pfault_init();
e545a614 820 notify_cpu_starting(smp_processor_id());
0f1959f5 821 set_cpu_online(smp_processor_id(), true);
93f3b2ee 822 inc_irq_stat(CPU_RST);
1da177e4 823 local_irq_enable();
fc6d73d6 824 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
825}
826
1da177e4 827/* Upping and downing of CPUs */
e2741f17 828int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 829{
8b646bd7 830 struct pcpu *pcpu;
10ad34bc 831 int base, i, rc;
1da177e4 832
8b646bd7
MS
833 pcpu = pcpu_devices + cpu;
834 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 835 return -EIO;
5423145f 836 base = smp_get_base_cpu(cpu);
10ad34bc
MS
837 for (i = 0; i <= smp_cpu_mtid; i++) {
838 if (base + i < nr_cpu_ids)
839 if (cpu_online(base + i))
840 break;
841 }
842 /*
843 * If this is the first CPU of the core to get online
844 * do an initial CPU reset.
845 */
846 if (i > smp_cpu_mtid &&
847 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 848 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 849 return -EIO;
e80e7813 850
8b646bd7
MS
851 rc = pcpu_alloc_lowcore(pcpu, cpu);
852 if (rc)
853 return rc;
854 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 855 pcpu_attach_task(pcpu, tidle);
8b646bd7 856 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 857 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 858 while (!cpu_online(cpu))
1da177e4
LT
859 cpu_relax();
860 return 0;
861}
862
d80512f8 863static unsigned int setup_possible_cpus __initdata;
255acee7 864
d80512f8
HC
865static int __init _setup_possible_cpus(char *s)
866{
867 get_option(&s, &setup_possible_cpus);
37a33026
HC
868 return 0;
869}
d80512f8 870early_param("possible_cpus", _setup_possible_cpus);
37a33026 871
48483b32
HC
872#ifdef CONFIG_HOTPLUG_CPU
873
39ce010d 874int __cpu_disable(void)
1da177e4 875{
8b646bd7 876 unsigned long cregs[16];
1da177e4 877
9acf73b7
HC
878 /* Handle possible pending IPIs */
879 smp_handle_ext_call();
8b646bd7
MS
880 set_cpu_online(smp_processor_id(), false);
881 /* Disable pseudo page faults on this cpu. */
29b08d2b 882 pfault_fini();
8b646bd7
MS
883 /* Disable interrupt sources via control register. */
884 __ctl_store(cregs, 0, 15);
885 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
886 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
887 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
888 __ctl_load(cregs, 0, 15);
fe0f4976 889 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
890 return 0;
891}
892
39ce010d 893void __cpu_die(unsigned int cpu)
1da177e4 894{
8b646bd7
MS
895 struct pcpu *pcpu;
896
1da177e4 897 /* Wait until target cpu is down */
8b646bd7
MS
898 pcpu = pcpu_devices + cpu;
899 while (!pcpu_stopped(pcpu))
1da177e4 900 cpu_relax();
8b646bd7 901 pcpu_free_lowcore(pcpu);
1b948d6c 902 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 903 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
904}
905
b456d94a 906void __noreturn cpu_die(void)
1da177e4
LT
907{
908 idle_task_exit();
a9ae32c3 909 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 910 for (;;) ;
1da177e4
LT
911}
912
255acee7
HC
913#endif /* CONFIG_HOTPLUG_CPU */
914
d80512f8
HC
915void __init smp_fill_possible_mask(void)
916{
9747bc47 917 unsigned int possible, sclp_max, cpu;
d80512f8 918
3a9f3fe6
DH
919 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
920 sclp_max = min(smp_max_threads, sclp_max);
61282aff 921 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 922 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 923 possible = min(possible, sclp_max);
d80512f8
HC
924 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
925 set_cpu_possible(cpu, true);
926}
927
1da177e4
LT
928void __init smp_prepare_cpus(unsigned int max_cpus)
929{
916cda1a
MS
930 unsigned long size;
931
39ce010d 932 /* request the 0x1201 emergency signal external interrupt */
1dad093b 933 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 934 panic("Couldn't request external interrupt 0x1201");
d98e19cc 935 /* request the 0x1202 external call external interrupt */
1dad093b 936 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 937 panic("Couldn't request external interrupt 0x1202");
916cda1a
MS
938 /* create slab cache for the machine-check-extended-save-areas */
939 if (MACHINE_HAS_VX || MACHINE_HAS_GS) {
940 size = 1UL << (MACHINE_HAS_GS ? 11 : 10);
941 pcpu_mcesa_cache = kmem_cache_create("nmi_save_areas",
942 size, size, 0, NULL);
943 if (!pcpu_mcesa_cache)
944 panic("Couldn't create nmi save area cache");
945 }
1da177e4
LT
946}
947
ea1f4eec 948void __init smp_prepare_boot_cpu(void)
1da177e4 949{
8b646bd7
MS
950 struct pcpu *pcpu = pcpu_devices;
951
0861b5a7 952 WARN_ON(!cpu_present(0) || !cpu_online(0));
8b646bd7 953 pcpu->state = CPU_STATE_CONFIGURED;
c667aeac 954 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 955 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 956 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1da177e4
LT
957}
958
ea1f4eec 959void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 960{
1da177e4
LT
961}
962
02beaccc
HC
963void __init smp_setup_processor_id(void)
964{
0861b5a7 965 pcpu_devices[0].address = stap();
02beaccc 966 S390_lowcore.cpu_nr = 0;
6c8cd5bb 967 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
02beaccc
HC
968}
969
1da177e4
LT
970/*
971 * the frequency of the profiling timer can be changed
972 * by writing a multiplier value into /proc/profile.
973 *
974 * usually you want to run this on all CPUs ;)
975 */
976int setup_profiling_timer(unsigned int multiplier)
977{
39ce010d 978 return 0;
1da177e4
LT
979}
980
08d07968 981#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 982static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 983 struct device_attribute *attr, char *buf)
08d07968
HC
984{
985 ssize_t count;
986
987 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 988 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
989 mutex_unlock(&smp_cpu_state_mutex);
990 return count;
991}
992
8a25a2fd 993static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
994 struct device_attribute *attr,
995 const char *buf, size_t count)
08d07968 996{
8b646bd7 997 struct pcpu *pcpu;
10ad34bc 998 int cpu, val, rc, i;
08d07968
HC
999 char delim;
1000
1001 if (sscanf(buf, "%d %c", &val, &delim) != 1)
1002 return -EINVAL;
1003 if (val != 0 && val != 1)
1004 return -EINVAL;
9d40d2e3 1005 get_online_cpus();
0b18d318 1006 mutex_lock(&smp_cpu_state_mutex);
08d07968 1007 rc = -EBUSY;
2c2df118 1008 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 1009 cpu = dev->id;
5423145f 1010 cpu = smp_get_base_cpu(cpu);
10ad34bc 1011 if (cpu == 0)
08d07968 1012 goto out;
10ad34bc
MS
1013 for (i = 0; i <= smp_cpu_mtid; i++)
1014 if (cpu_online(cpu + i))
1015 goto out;
8b646bd7 1016 pcpu = pcpu_devices + cpu;
08d07968
HC
1017 rc = 0;
1018 switch (val) {
1019 case 0:
8b646bd7
MS
1020 if (pcpu->state != CPU_STATE_CONFIGURED)
1021 break;
d08d9430 1022 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1023 if (rc)
1024 break;
10ad34bc
MS
1025 for (i = 0; i <= smp_cpu_mtid; i++) {
1026 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1027 continue;
1028 pcpu[i].state = CPU_STATE_STANDBY;
1029 smp_cpu_set_polarization(cpu + i,
1030 POLARIZATION_UNKNOWN);
1031 }
8b646bd7 1032 topology_expect_change();
08d07968
HC
1033 break;
1034 case 1:
8b646bd7
MS
1035 if (pcpu->state != CPU_STATE_STANDBY)
1036 break;
d08d9430 1037 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1038 if (rc)
1039 break;
10ad34bc
MS
1040 for (i = 0; i <= smp_cpu_mtid; i++) {
1041 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1042 continue;
1043 pcpu[i].state = CPU_STATE_CONFIGURED;
1044 smp_cpu_set_polarization(cpu + i,
1045 POLARIZATION_UNKNOWN);
1046 }
8b646bd7 1047 topology_expect_change();
08d07968
HC
1048 break;
1049 default:
1050 break;
1051 }
1052out:
08d07968 1053 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1054 put_online_cpus();
08d07968
HC
1055 return rc ? rc : count;
1056}
8a25a2fd 1057static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968
HC
1058#endif /* CONFIG_HOTPLUG_CPU */
1059
8a25a2fd
KS
1060static ssize_t show_cpu_address(struct device *dev,
1061 struct device_attribute *attr, char *buf)
08d07968 1062{
8b646bd7 1063 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1064}
8a25a2fd 1065static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1066
08d07968
HC
1067static struct attribute *cpu_common_attrs[] = {
1068#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1069 &dev_attr_configure.attr,
08d07968 1070#endif
8a25a2fd 1071 &dev_attr_address.attr,
08d07968
HC
1072 NULL,
1073};
1074
1075static struct attribute_group cpu_common_attr_group = {
1076 .attrs = cpu_common_attrs,
1077};
1da177e4 1078
08d07968 1079static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1080 &dev_attr_idle_count.attr,
1081 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1082 NULL,
1083};
1084
08d07968
HC
1085static struct attribute_group cpu_online_attr_group = {
1086 .attrs = cpu_online_attrs,
fae8b22d
HC
1087};
1088
dfbbd86a 1089static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1090{
2f859d0d 1091 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1092
dfbbd86a
SAS
1093 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1094}
1095static int smp_cpu_pre_down(unsigned int cpu)
1096{
1097 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1098
1099 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1100 return 0;
2fc2d1e9
HC
1101}
1102
e2741f17 1103static int smp_add_present_cpu(int cpu)
08d07968 1104{
96619fc1
HC
1105 struct device *s;
1106 struct cpu *c;
08d07968
HC
1107 int rc;
1108
96619fc1
HC
1109 c = kzalloc(sizeof(*c), GFP_KERNEL);
1110 if (!c)
1111 return -ENOMEM;
2f859d0d 1112 per_cpu(cpu_device, cpu) = c;
96619fc1 1113 s = &c->dev;
08d07968
HC
1114 c->hotpluggable = 1;
1115 rc = register_cpu(c, cpu);
1116 if (rc)
1117 goto out;
1118 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1119 if (rc)
1120 goto out_cpu;
83a24e32
HC
1121 rc = topology_cpu_init(c);
1122 if (rc)
1123 goto out_topology;
1124 return 0;
1125
1126out_topology:
08d07968
HC
1127 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1128out_cpu:
1129#ifdef CONFIG_HOTPLUG_CPU
1130 unregister_cpu(c);
1131#endif
1132out:
1133 return rc;
1134}
1135
1136#ifdef CONFIG_HOTPLUG_CPU
1e489518 1137
67060d9c 1138int __ref smp_rescan_cpus(void)
08d07968 1139{
d08d9430 1140 struct sclp_core_info *info;
8b646bd7 1141 int nr;
08d07968 1142
af51160e 1143 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1144 if (!info)
1145 return -ENOMEM;
af51160e 1146 smp_get_core_info(info, 0);
9d40d2e3 1147 get_online_cpus();
0b18d318 1148 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1149 nr = __smp_rescan_cpus(info, 1);
08d07968 1150 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1151 put_online_cpus();
8b646bd7
MS
1152 kfree(info);
1153 if (nr)
c10fde0d 1154 topology_schedule_update();
8b646bd7 1155 return 0;
1e489518
HC
1156}
1157
8a25a2fd
KS
1158static ssize_t __ref rescan_store(struct device *dev,
1159 struct device_attribute *attr,
c9be0a36 1160 const char *buf,
1e489518
HC
1161 size_t count)
1162{
1163 int rc;
1164
1165 rc = smp_rescan_cpus();
08d07968
HC
1166 return rc ? rc : count;
1167}
8a25a2fd 1168static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
08d07968
HC
1169#endif /* CONFIG_HOTPLUG_CPU */
1170
83a24e32 1171static int __init s390_smp_init(void)
1da177e4 1172{
f4edbcd5 1173 int cpu, rc = 0;
2fc2d1e9 1174
08d07968 1175#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1176 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1177 if (rc)
1178 return rc;
1179#endif
1180 for_each_present_cpu(cpu) {
1181 rc = smp_add_present_cpu(cpu);
fae8b22d 1182 if (rc)
f4edbcd5 1183 goto out;
1da177e4 1184 }
f4edbcd5 1185
dfbbd86a
SAS
1186 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1187 smp_cpu_online, smp_cpu_pre_down);
e1108e8f 1188 rc = rc <= 0 ? rc : 0;
f4edbcd5 1189out:
f4edbcd5 1190 return rc;
1da177e4 1191}
83a24e32 1192subsys_initcall(s390_smp_init);