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CommitLineData
1da177e4 1/*
8b646bd7 2 * SMP related functions
1da177e4 3 *
a53c8fab 4 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
5 * Author(s): Denis Joseph Barrow,
6 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
7 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 8 *
39ce010d 9 * based on other smp stuff by
1da177e4
LT
10 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
11 * (c) 1998 Ingo Molnar
12 *
8b646bd7
MS
13 * The code outside of smp.c uses logical cpu numbers, only smp.c does
14 * the translation of logical to physical cpu ids. All new code that
15 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
16 */
17
395d31d4
MS
18#define KMSG_COMPONENT "cpu"
19#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
f230886b 21#include <linux/workqueue.h>
1da177e4
LT
22#include <linux/module.h>
23#include <linux/init.h>
1da177e4 24#include <linux/mm.h>
4e950f6f 25#include <linux/err.h>
1da177e4
LT
26#include <linux/spinlock.h>
27#include <linux/kernel_stat.h>
1da177e4 28#include <linux/delay.h>
1da177e4 29#include <linux/interrupt.h>
3324e60a 30#include <linux/irqflags.h>
1da177e4 31#include <linux/cpu.h>
5a0e3ad6 32#include <linux/slab.h>
60a0c68d 33#include <linux/crash_dump.h>
1592a8e4 34#include <linux/memblock.h>
cbb870c8 35#include <asm/asm-offsets.h>
1e3cab2f
HC
36#include <asm/switch_to.h>
37#include <asm/facility.h>
46b05d26 38#include <asm/ipl.h>
2b67fc46 39#include <asm/setup.h>
1da177e4 40#include <asm/irq.h>
1da177e4 41#include <asm/tlbflush.h>
27f6b416 42#include <asm/vtimer.h>
411ed322 43#include <asm/lowcore.h>
08d07968 44#include <asm/sclp.h>
c742b31c 45#include <asm/vdso.h>
3ab121ab 46#include <asm/debug.h>
4857d4bb 47#include <asm/os_info.h>
a9ae32c3 48#include <asm/sigp.h>
b5f87f15 49#include <asm/idle.h>
a806170e 50#include "entry.h"
1da177e4 51
8b646bd7
MS
52enum {
53 ec_schedule = 0,
8b646bd7
MS
54 ec_call_function_single,
55 ec_stop_cpu,
56};
08d07968 57
8b646bd7 58enum {
08d07968
HC
59 CPU_STATE_STANDBY,
60 CPU_STATE_CONFIGURED,
61};
62
2f859d0d
HC
63static DEFINE_PER_CPU(struct cpu *, cpu_device);
64
8b646bd7 65struct pcpu {
8b646bd7 66 struct _lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 67 unsigned long ec_mask; /* bit mask for ec_xxx functions */
2f859d0d
HC
68 signed char state; /* physical cpu state */
69 signed char polarization; /* physical polarization */
8b646bd7
MS
70 u16 address; /* physical cpu address */
71};
72
d08d9430 73static u8 boot_core_type;
8b646bd7
MS
74static struct pcpu pcpu_devices[NR_CPUS];
75
10ad34bc
MS
76unsigned int smp_cpu_mt_shift;
77EXPORT_SYMBOL(smp_cpu_mt_shift);
78
79unsigned int smp_cpu_mtid;
80EXPORT_SYMBOL(smp_cpu_mtid);
81
82static unsigned int smp_max_threads __initdata = -1U;
83
84static int __init early_nosmt(char *s)
85{
86 smp_max_threads = 1;
87 return 0;
88}
89early_param("nosmt", early_nosmt);
90
91static int __init early_smt(char *s)
92{
93 get_option(&s, &smp_max_threads);
94 return 0;
95}
96early_param("smt", early_smt);
97
50ab9a9a
HC
98/*
99 * The smp_cpu_state_mutex must be held when changing the state or polarization
100 * member of a pcpu data structure within the pcpu_devices arreay.
101 */
dbd70fb4 102DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 103
8b646bd7
MS
104/*
105 * Signal processor helper functions.
106 */
a62bc073
MH
107static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm,
108 u32 *status)
5c0b912e 109{
8b646bd7 110 int cc;
5c0b912e 111
8b646bd7 112 while (1) {
c5e3acd6 113 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 114 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
115 return cc;
116 cpu_relax();
5c0b912e 117 }
5c0b912e
HC
118}
119
8b646bd7 120static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 121{
8b646bd7
MS
122 int cc, retry;
123
124 for (retry = 0; ; retry++) {
c5e3acd6 125 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 126 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
127 break;
128 if (retry >= 3)
129 udelay(10);
130 }
131 return cc;
132}
133
134static inline int pcpu_stopped(struct pcpu *pcpu)
135{
41459d36 136 u32 uninitialized_var(status);
c5e3acd6 137
a9ae32c3 138 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 139 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 140 return 0;
c5e3acd6 141 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
142}
143
144static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 145{
a9ae32c3 146 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 147 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 148 return 1;
524b24ad
HC
149 /* Status stored condition code is equivalent to cpu not running. */
150 return 0;
a93b8ec1
HC
151}
152
1943f53c 153/*
8b646bd7 154 * Find struct pcpu by cpu address.
1943f53c 155 */
10ad34bc 156static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
157{
158 int cpu;
159
8b646bd7
MS
160 for_each_cpu(cpu, mask)
161 if (pcpu_devices[cpu].address == address)
162 return pcpu_devices + cpu;
163 return NULL;
164}
165
166static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
167{
168 int order;
169
dea24190
HC
170 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
171 return;
172 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
8b646bd7
MS
173 pcpu_sigp_retry(pcpu, order, 0);
174}
175
2f859d0d
HC
176#define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
177#define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
178
e2741f17 179static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 180{
2f859d0d 181 unsigned long async_stack, panic_stack;
8b646bd7
MS
182 struct _lowcore *lc;
183
184 if (pcpu != &pcpu_devices[0]) {
185 pcpu->lowcore = (struct _lowcore *)
186 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
2f859d0d
HC
187 async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
188 panic_stack = __get_free_page(GFP_KERNEL);
189 if (!pcpu->lowcore || !panic_stack || !async_stack)
8b646bd7 190 goto out;
2f859d0d
HC
191 } else {
192 async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
193 panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
1943f53c 194 }
8b646bd7
MS
195 lc = pcpu->lowcore;
196 memcpy(lc, &S390_lowcore, 512);
197 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
2f859d0d
HC
198 lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
199 lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
8b646bd7 200 lc->cpu_nr = cpu;
6c8cd5bb 201 lc->spinlock_lockval = arch_spin_lockval(cpu);
80703617
MS
202 if (MACHINE_HAS_VX)
203 lc->vector_save_area_addr =
204 (unsigned long) &lc->vector_save_area;
8b646bd7
MS
205 if (vdso_alloc_per_cpu(lc))
206 goto out;
8b646bd7 207 lowcore_ptr[cpu] = lc;
a9ae32c3 208 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7
MS
209 return 0;
210out:
211 if (pcpu != &pcpu_devices[0]) {
2f859d0d
HC
212 free_page(panic_stack);
213 free_pages(async_stack, ASYNC_ORDER);
8b646bd7
MS
214 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
215 }
216 return -ENOMEM;
1943f53c
MH
217}
218
9d0f46af
HC
219#ifdef CONFIG_HOTPLUG_CPU
220
8b646bd7 221static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 222{
a9ae32c3 223 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 224 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 225 vdso_free_per_cpu(pcpu->lowcore);
2f859d0d
HC
226 if (pcpu == &pcpu_devices[0])
227 return;
228 free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
229 free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
230 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
8b646bd7
MS
231}
232
9d0f46af
HC
233#endif /* CONFIG_HOTPLUG_CPU */
234
8b646bd7
MS
235static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
236{
237 struct _lowcore *lc = pcpu->lowcore;
238
1b948d6c
MS
239 if (MACHINE_HAS_TLB_LC)
240 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
241 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7
MS
242 atomic_inc(&init_mm.context.attach_count);
243 lc->cpu_nr = cpu;
6c8cd5bb 244 lc->spinlock_lockval = arch_spin_lockval(cpu);
8b646bd7
MS
245 lc->percpu_offset = __per_cpu_offset[cpu];
246 lc->kernel_asce = S390_lowcore.kernel_asce;
247 lc->machine_flags = S390_lowcore.machine_flags;
8b646bd7
MS
248 lc->user_timer = lc->system_timer = lc->steal_timer = 0;
249 __ctl_store(lc->cregs_save_area, 0, 15);
250 save_access_regs((unsigned int *) lc->access_regs_save_area);
251 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
252 MAX_FACILITY_BIT/8);
253}
254
255static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
256{
257 struct _lowcore *lc = pcpu->lowcore;
258 struct thread_info *ti = task_thread_info(tsk);
259
dc7ee00d
MS
260 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
261 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7
MS
262 lc->thread_info = (unsigned long) task_thread_info(tsk);
263 lc->current_task = (unsigned long) tsk;
264 lc->user_timer = ti->user_timer;
265 lc->system_timer = ti->system_timer;
266 lc->steal_timer = 0;
267}
268
269static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
270{
271 struct _lowcore *lc = pcpu->lowcore;
272
273 lc->restart_stack = lc->kernel_stack;
274 lc->restart_fn = (unsigned long) func;
275 lc->restart_data = (unsigned long) data;
276 lc->restart_source = -1UL;
a9ae32c3 277 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
278}
279
280/*
281 * Call function via PSW restart on pcpu and stop the current cpu.
282 */
283static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
284 void *data, unsigned long stack)
285{
061da3df 286 struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 287 unsigned long source_cpu = stap();
8b646bd7 288
e258d719 289 __load_psw_mask(PSW_KERNEL_BITS);
fbe76568 290 if (pcpu->address == source_cpu)
8b646bd7
MS
291 func(data); /* should not return */
292 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 293 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 294 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
295 mem_assign_absolute(lc->restart_stack, stack);
296 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
297 mem_assign_absolute(lc->restart_data, (unsigned long) data);
298 mem_assign_absolute(lc->restart_source, source_cpu);
8b646bd7 299 asm volatile(
eb546195 300 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 301 " brc 2,0b # busy, try again\n"
eb546195 302 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 303 " brc 2,1b # busy, try again\n"
fbe76568 304 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
305 "K" (SIGP_RESTART), "K" (SIGP_STOP)
306 : "0", "1", "cc");
8b646bd7
MS
307 for (;;) ;
308}
309
10ad34bc
MS
310/*
311 * Enable additional logical cpus for multi-threading.
312 */
313static int pcpu_set_smt(unsigned int mtid)
314{
315 register unsigned long reg1 asm ("1") = (unsigned long) mtid;
316 int cc;
317
318 if (smp_cpu_mtid == mtid)
319 return 0;
320 asm volatile(
321 " sigp %1,0,%2 # sigp set multi-threading\n"
322 " ipm %0\n"
323 " srl %0,28\n"
324 : "=d" (cc) : "d" (reg1), "K" (SIGP_SET_MULTI_THREADING)
325 : "cc");
326 if (cc == 0) {
327 smp_cpu_mtid = mtid;
328 smp_cpu_mt_shift = 0;
329 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
330 smp_cpu_mt_shift++;
331 pcpu_devices[0].address = stap();
332 }
333 return cc;
334}
335
8b646bd7
MS
336/*
337 * Call function on an online CPU.
338 */
339void smp_call_online_cpu(void (*func)(void *), void *data)
340{
341 struct pcpu *pcpu;
342
343 /* Use the current cpu if it is online. */
344 pcpu = pcpu_find_address(cpu_online_mask, stap());
345 if (!pcpu)
346 /* Use the first online cpu. */
347 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
348 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
349}
350
351/*
352 * Call function on the ipl CPU.
353 */
354void smp_call_ipl_cpu(void (*func)(void *), void *data)
355{
c6da39f2 356 pcpu_delegate(&pcpu_devices[0], func, data,
2f859d0d
HC
357 pcpu_devices->lowcore->panic_stack -
358 PANIC_FRAME_OFFSET + PAGE_SIZE);
8b646bd7
MS
359}
360
361int smp_find_processor_id(u16 address)
362{
363 int cpu;
364
365 for_each_present_cpu(cpu)
366 if (pcpu_devices[cpu].address == address)
367 return cpu;
368 return -1;
2c2df118
HC
369}
370
8b646bd7 371int smp_vcpu_scheduled(int cpu)
85ac7ca5 372{
8b646bd7
MS
373 return pcpu_running(pcpu_devices + cpu);
374}
375
8b646bd7 376void smp_yield_cpu(int cpu)
85ac7ca5 377{
8b646bd7
MS
378 if (MACHINE_HAS_DIAG9C)
379 asm volatile("diag %0,0,0x9c"
380 : : "d" (pcpu_devices[cpu].address));
381 else if (MACHINE_HAS_DIAG44)
382 asm volatile("diag 0,0,0x44");
383}
384
385/*
386 * Send cpus emergency shutdown signal. This gives the cpus the
387 * opportunity to complete outstanding interrupts.
388 */
63df41d6 389static void smp_emergency_stop(cpumask_t *cpumask)
8b646bd7
MS
390{
391 u64 end;
392 int cpu;
393
1aae0560 394 end = get_tod_clock() + (1000000UL << 12);
8b646bd7
MS
395 for_each_cpu(cpu, cpumask) {
396 struct pcpu *pcpu = pcpu_devices + cpu;
397 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
398 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
399 0, NULL) == SIGP_CC_BUSY &&
1aae0560 400 get_tod_clock() < end)
8b646bd7
MS
401 cpu_relax();
402 }
1aae0560 403 while (get_tod_clock() < end) {
8b646bd7
MS
404 for_each_cpu(cpu, cpumask)
405 if (pcpu_stopped(pcpu_devices + cpu))
406 cpumask_clear_cpu(cpu, cpumask);
407 if (cpumask_empty(cpumask))
408 break;
85ac7ca5 409 cpu_relax();
8b646bd7 410 }
85ac7ca5
MS
411}
412
8b646bd7
MS
413/*
414 * Stop all cpus but the current one.
415 */
677d7623 416void smp_send_stop(void)
1da177e4 417{
85ac7ca5
MS
418 cpumask_t cpumask;
419 int cpu;
1da177e4 420
677d7623 421 /* Disable all interrupts/machine checks */
e258d719 422 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 423 trace_hardirqs_off();
1da177e4 424
3ab121ab 425 debug_set_critical();
85ac7ca5
MS
426 cpumask_copy(&cpumask, cpu_online_mask);
427 cpumask_clear_cpu(smp_processor_id(), &cpumask);
428
8b646bd7
MS
429 if (oops_in_progress)
430 smp_emergency_stop(&cpumask);
1da177e4 431
85ac7ca5
MS
432 /* stop all processors */
433 for_each_cpu(cpu, &cpumask) {
8b646bd7 434 struct pcpu *pcpu = pcpu_devices + cpu;
a9ae32c3 435 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 436 while (!pcpu_stopped(pcpu))
c6b5b847
HC
437 cpu_relax();
438 }
439}
440
1da177e4
LT
441/*
442 * This is the main routine where commands issued by other
443 * cpus are handled.
444 */
9acf73b7 445static void smp_handle_ext_call(void)
1da177e4 446{
39ce010d 447 unsigned long bits;
1da177e4 448
9acf73b7
HC
449 /* handle bit signal external calls */
450 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
451 if (test_bit(ec_stop_cpu, &bits))
452 smp_stop_cpu();
184748cc
PZ
453 if (test_bit(ec_schedule, &bits))
454 scheduler_ipi();
ca9fc75a
HC
455 if (test_bit(ec_call_function_single, &bits))
456 generic_smp_call_function_single_interrupt();
9acf73b7 457}
85ac7ca5 458
9acf73b7
HC
459static void do_ext_call_interrupt(struct ext_code ext_code,
460 unsigned int param32, unsigned long param64)
461{
462 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
463 smp_handle_ext_call();
1da177e4
LT
464}
465
630cd046 466void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
467{
468 int cpu;
469
630cd046 470 for_each_cpu(cpu, mask)
b6ed49e0 471 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
472}
473
474void arch_send_call_function_single_ipi(int cpu)
475{
8b646bd7 476 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
477}
478
1da177e4
LT
479/*
480 * this function sends a 'reschedule' IPI to another CPU.
481 * it goes straight through and wastes no time serializing
482 * anything. Worst case is that we lose a reschedule ...
483 */
484void smp_send_reschedule(int cpu)
485{
8b646bd7 486 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
487}
488
489/*
490 * parameter area for the set/clear control bit callbacks
491 */
94c12cc7 492struct ec_creg_mask_parms {
8b646bd7
MS
493 unsigned long orval;
494 unsigned long andval;
495 int cr;
94c12cc7 496};
1da177e4
LT
497
498/*
499 * callback for setting/clearing control bits
500 */
39ce010d
HC
501static void smp_ctl_bit_callback(void *info)
502{
94c12cc7 503 struct ec_creg_mask_parms *pp = info;
1da177e4 504 unsigned long cregs[16];
39ce010d 505
94c12cc7 506 __ctl_store(cregs, 0, 15);
8b646bd7 507 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 508 __ctl_load(cregs, 0, 15);
1da177e4
LT
509}
510
511/*
512 * Set a bit in a control register of all cpus
513 */
94c12cc7
MS
514void smp_ctl_set_bit(int cr, int bit)
515{
8b646bd7 516 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 517
15c8b6c1 518 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 519}
39ce010d 520EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
521
522/*
523 * Clear a bit in a control register of all cpus
524 */
94c12cc7
MS
525void smp_ctl_clear_bit(int cr, int bit)
526{
8b646bd7 527 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 528
15c8b6c1 529 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 530}
39ce010d 531EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 532
bf28a597 533#ifdef CONFIG_CRASH_DUMP
411ed322 534
e7f596de
HC
535static void __init __smp_store_cpu_state(struct save_area_ext *sa_ext,
536 u16 address, int is_boot_cpu)
411ed322 537{
1592a8e4 538 void *lc = (void *)(unsigned long) store_prefix();
a62bc073 539 unsigned long vx_sa;
8b646bd7 540
10ad34bc
MS
541 if (is_boot_cpu) {
542 /* Copy the registers of the boot CPU. */
a62bc073 543 copy_oldmem_page(1, (void *) &sa_ext->sa, sizeof(sa_ext->sa),
8b646bd7 544 SAVE_AREA_BASE - PAGE_SIZE, 0);
a62bc073
MH
545 if (MACHINE_HAS_VX)
546 save_vx_regs_safe(sa_ext->vx_regs);
8b646bd7
MS
547 return;
548 }
8b646bd7 549 /* Get the registers of a non-boot cpu. */
a9ae32c3 550 __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL);
a62bc073
MH
551 memcpy_real(&sa_ext->sa, lc + SAVE_AREA_BASE, sizeof(sa_ext->sa));
552 if (!MACHINE_HAS_VX)
553 return;
554 /* Get the VX registers */
1592a8e4 555 vx_sa = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
a62bc073
MH
556 if (!vx_sa)
557 panic("could not allocate memory for VX save area\n");
558 __pcpu_sigp_relax(address, SIGP_STORE_ADDITIONAL_STATUS, vx_sa, NULL);
559 memcpy(sa_ext->vx_regs, (void *) vx_sa, sizeof(sa_ext->vx_regs));
1592a8e4 560 memblock_free(vx_sa, PAGE_SIZE);
411ed322
MH
561}
562
1af135a1
HC
563int smp_store_status(int cpu)
564{
565 unsigned long vx_sa;
566 struct pcpu *pcpu;
567
568 pcpu = pcpu_devices + cpu;
569 if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS,
570 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED)
571 return -EIO;
572 if (!MACHINE_HAS_VX)
573 return 0;
574 vx_sa = __pa(pcpu->lowcore->vector_save_area_addr);
575 __pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
576 vx_sa, NULL);
577 return 0;
578}
579
580#endif /* CONFIG_CRASH_DUMP */
581
10ad34bc
MS
582/*
583 * Collect CPU state of the previous, crashed system.
584 * There are four cases:
585 * 1) standard zfcp dump
586 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
587 * The state for all CPUs except the boot CPU needs to be collected
588 * with sigp stop-and-store-status. The boot CPU state is located in
589 * the absolute lowcore of the memory stored in the HSA. The zcore code
590 * will allocate the save area and copy the boot CPU state from the HSA.
591 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
592 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
593 * The state for all CPUs except the boot CPU needs to be collected
594 * with sigp stop-and-store-status. The firmware or the boot-loader
595 * stored the registers of the boot CPU in the absolute lowcore in the
596 * memory of the old system.
597 * 3) kdump and the old kernel did not store the CPU state,
598 * or stand-alone kdump for DASD
599 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
600 * The state for all CPUs except the boot CPU needs to be collected
601 * with sigp stop-and-store-status. The kexec code or the boot-loader
602 * stored the registers of the boot CPU in the memory of the old system.
603 * 4) kdump and the old kernel stored the CPU state
604 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
605 * The state of all CPUs is stored in ELF sections in the memory of the
606 * old system. The ELF sections are picked up by the crash_dump code
607 * via elfcorehdr_addr.
608 */
1592a8e4 609void __init smp_save_dump_cpus(void)
10ad34bc 610{
1af135a1 611#ifdef CONFIG_CRASH_DUMP
1592a8e4
MH
612 int addr, cpu, boot_cpu_addr, max_cpu_addr;
613 struct save_area_ext *sa_ext;
614 bool is_boot_cpu;
10ad34bc
MS
615
616 if (is_kdump_kernel())
617 /* Previous system stored the CPU states. Nothing to do. */
618 return;
619 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
620 /* No previous system present, normal boot. */
621 return;
622 /* Set multi-threading state to the previous system. */
37c5f6c8 623 pcpu_set_smt(sclp.mtid_prev);
1592a8e4
MH
624 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
625 for (cpu = 0, addr = 0; addr <= max_cpu_addr; addr++) {
626 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0, NULL) ==
627 SIGP_CC_NOT_OPERATIONAL)
10ad34bc 628 continue;
1592a8e4
MH
629 cpu += 1;
630 }
631 dump_save_areas.areas = (void *)memblock_alloc(sizeof(void *) * cpu, 8);
632 dump_save_areas.count = cpu;
633 boot_cpu_addr = stap();
634 for (cpu = 0, addr = 0; addr <= max_cpu_addr; addr++) {
635 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0, NULL) ==
636 SIGP_CC_NOT_OPERATIONAL)
637 continue;
638 sa_ext = (void *) memblock_alloc(sizeof(*sa_ext), 8);
639 dump_save_areas.areas[cpu] = sa_ext;
640 if (!sa_ext)
641 panic("could not allocate memory for save area\n");
642 is_boot_cpu = (addr == boot_cpu_addr);
643 cpu += 1;
644 if (is_boot_cpu && !OLDMEM_BASE)
645 /* Skip boot CPU for standard zfcp dump. */
646 continue;
647 /* Get state for this CPU. */
648 __smp_store_cpu_state(sa_ext, addr, is_boot_cpu);
10ad34bc 649 }
1592a8e4
MH
650 diag308_reset();
651 pcpu_set_smt(0);
bf28a597 652#endif /* CONFIG_CRASH_DUMP */
1af135a1 653}
08d07968 654
50ab9a9a
HC
655void smp_cpu_set_polarization(int cpu, int val)
656{
657 pcpu_devices[cpu].polarization = val;
658}
659
660int smp_cpu_get_polarization(int cpu)
661{
662 return pcpu_devices[cpu].polarization;
663}
664
d08d9430 665static struct sclp_core_info *smp_get_core_info(void)
08d07968 666{
8b646bd7 667 static int use_sigp_detection;
d08d9430 668 struct sclp_core_info *info;
8b646bd7
MS
669 int address;
670
671 info = kzalloc(sizeof(*info), GFP_KERNEL);
d08d9430 672 if (info && (use_sigp_detection || sclp_get_core_info(info))) {
8b646bd7 673 use_sigp_detection = 1;
e7086eb1 674 for (address = 0;
d08d9430 675 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 676 address += (1U << smp_cpu_mt_shift)) {
a9ae32c3
HC
677 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) ==
678 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 679 continue;
d08d9430 680 info->core[info->configured].core_id =
10ad34bc 681 address >> smp_cpu_mt_shift;
8b646bd7
MS
682 info->configured++;
683 }
684 info->combined = info->configured;
08d07968 685 }
8b646bd7 686 return info;
08d07968
HC
687}
688
e2741f17 689static int smp_add_present_cpu(int cpu);
8b646bd7 690
d08d9430 691static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 692{
8b646bd7 693 struct pcpu *pcpu;
08d07968 694 cpumask_t avail;
10ad34bc
MS
695 int cpu, nr, i, j;
696 u16 address;
08d07968 697
8b646bd7 698 nr = 0;
0f1959f5 699 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
700 cpu = cpumask_first(&avail);
701 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 702 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 703 continue;
d08d9430 704 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
705 for (j = 0; j <= smp_cpu_mtid; j++) {
706 if (pcpu_find_address(cpu_present_mask, address + j))
707 continue;
708 pcpu = pcpu_devices + cpu;
709 pcpu->address = address + j;
710 pcpu->state =
711 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
712 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
713 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
714 set_cpu_present(cpu, true);
715 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
716 set_cpu_present(cpu, false);
717 else
718 nr++;
719 cpu = cpumask_next(cpu, &avail);
720 if (cpu >= nr_cpu_ids)
721 break;
722 }
8b646bd7
MS
723 }
724 return nr;
1da177e4
LT
725}
726
48483b32
HC
727static void __init smp_detect_cpus(void)
728{
10ad34bc 729 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 730 struct sclp_core_info *info;
10ad34bc 731 u16 address;
48483b32 732
10ad34bc 733 /* Get CPU information */
d08d9430 734 info = smp_get_core_info();
48483b32
HC
735 if (!info)
736 panic("smp_detect_cpus failed to allocate memory\n");
10ad34bc
MS
737
738 /* Find boot CPU type */
d08d9430 739 if (sclp.has_core_type) {
10ad34bc
MS
740 address = stap();
741 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 742 if (info->core[cpu].core_id == address) {
10ad34bc 743 /* The boot cpu dictates the cpu type. */
d08d9430 744 boot_core_type = info->core[cpu].type;
10ad34bc
MS
745 break;
746 }
747 if (cpu >= info->combined)
748 panic("Could not find boot CPU type");
48483b32 749 }
10ad34bc 750
10ad34bc 751 /* Set multi-threading state for the current system */
d08d9430 752 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
753 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
754 pcpu_set_smt(mtid);
755
756 /* Print number of CPUs */
8b646bd7 757 c_cpus = s_cpus = 0;
48483b32 758 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
759 if (sclp.has_core_type &&
760 info->core[cpu].type != boot_core_type)
48483b32 761 continue;
10ad34bc
MS
762 if (cpu < info->configured)
763 c_cpus += smp_cpu_mtid + 1;
764 else
765 s_cpus += smp_cpu_mtid + 1;
48483b32 766 }
395d31d4 767 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
768
769 /* Add CPUs present at boot */
9d40d2e3 770 get_online_cpus();
8b646bd7 771 __smp_rescan_cpus(info, 0);
9d40d2e3 772 put_online_cpus();
8b646bd7 773 kfree(info);
48483b32
HC
774}
775
1da177e4 776/*
39ce010d 777 * Activate a secondary processor.
1da177e4 778 */
e2741f17 779static void smp_start_secondary(void *cpuvoid)
1da177e4 780{
1aae0560 781 S390_lowcore.last_update_clock = get_tod_clock();
8b646bd7
MS
782 S390_lowcore.restart_stack = (unsigned long) restart_stack;
783 S390_lowcore.restart_fn = (unsigned long) do_restart;
784 S390_lowcore.restart_data = 0;
785 S390_lowcore.restart_source = -1UL;
786 restore_access_regs(S390_lowcore.access_regs_save_area);
787 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
e258d719 788 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
39ce010d 789 cpu_init();
5bfb5d69 790 preempt_disable();
39ce010d 791 init_cpu_timer();
b5f87f15 792 vtime_init();
29b08d2b 793 pfault_init();
e545a614 794 notify_cpu_starting(smp_processor_id());
0f1959f5 795 set_cpu_online(smp_processor_id(), true);
93f3b2ee 796 inc_irq_stat(CPU_RST);
1da177e4 797 local_irq_enable();
52c00659 798 cpu_startup_entry(CPUHP_ONLINE);
1da177e4
LT
799}
800
1da177e4 801/* Upping and downing of CPUs */
e2741f17 802int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 803{
8b646bd7 804 struct pcpu *pcpu;
10ad34bc 805 int base, i, rc;
1da177e4 806
8b646bd7
MS
807 pcpu = pcpu_devices + cpu;
808 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 809 return -EIO;
10ad34bc
MS
810 base = cpu - (cpu % (smp_cpu_mtid + 1));
811 for (i = 0; i <= smp_cpu_mtid; i++) {
812 if (base + i < nr_cpu_ids)
813 if (cpu_online(base + i))
814 break;
815 }
816 /*
817 * If this is the first CPU of the core to get online
818 * do an initial CPU reset.
819 */
820 if (i > smp_cpu_mtid &&
821 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 822 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 823 return -EIO;
e80e7813 824
8b646bd7
MS
825 rc = pcpu_alloc_lowcore(pcpu, cpu);
826 if (rc)
827 return rc;
828 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 829 pcpu_attach_task(pcpu, tidle);
8b646bd7 830 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba
HC
831 /* Wait until cpu puts itself in the online & active maps */
832 while (!cpu_online(cpu) || !cpu_active(cpu))
1da177e4
LT
833 cpu_relax();
834 return 0;
835}
836
d80512f8 837static unsigned int setup_possible_cpus __initdata;
255acee7 838
d80512f8
HC
839static int __init _setup_possible_cpus(char *s)
840{
841 get_option(&s, &setup_possible_cpus);
37a33026
HC
842 return 0;
843}
d80512f8 844early_param("possible_cpus", _setup_possible_cpus);
37a33026 845
48483b32
HC
846#ifdef CONFIG_HOTPLUG_CPU
847
39ce010d 848int __cpu_disable(void)
1da177e4 849{
8b646bd7 850 unsigned long cregs[16];
1da177e4 851
9acf73b7
HC
852 /* Handle possible pending IPIs */
853 smp_handle_ext_call();
8b646bd7
MS
854 set_cpu_online(smp_processor_id(), false);
855 /* Disable pseudo page faults on this cpu. */
29b08d2b 856 pfault_fini();
8b646bd7
MS
857 /* Disable interrupt sources via control register. */
858 __ctl_store(cregs, 0, 15);
859 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
860 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
861 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
862 __ctl_load(cregs, 0, 15);
fe0f4976 863 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
864 return 0;
865}
866
39ce010d 867void __cpu_die(unsigned int cpu)
1da177e4 868{
8b646bd7
MS
869 struct pcpu *pcpu;
870
1da177e4 871 /* Wait until target cpu is down */
8b646bd7
MS
872 pcpu = pcpu_devices + cpu;
873 while (!pcpu_stopped(pcpu))
1da177e4 874 cpu_relax();
8b646bd7 875 pcpu_free_lowcore(pcpu);
050eef36 876 atomic_dec(&init_mm.context.attach_count);
1b948d6c
MS
877 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
878 if (MACHINE_HAS_TLB_LC)
879 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
880}
881
b456d94a 882void __noreturn cpu_die(void)
1da177e4
LT
883{
884 idle_task_exit();
a9ae32c3 885 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 886 for (;;) ;
1da177e4
LT
887}
888
255acee7
HC
889#endif /* CONFIG_HOTPLUG_CPU */
890
d80512f8
HC
891void __init smp_fill_possible_mask(void)
892{
9747bc47 893 unsigned int possible, sclp_max, cpu;
d80512f8 894
3a9f3fe6
DH
895 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
896 sclp_max = min(smp_max_threads, sclp_max);
d08d9430 897 sclp_max = sclp.max_cores * sclp_max ?: nr_cpu_ids;
cf813db0 898 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 899 possible = min(possible, sclp_max);
d80512f8
HC
900 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
901 set_cpu_possible(cpu, true);
902}
903
1da177e4
LT
904void __init smp_prepare_cpus(unsigned int max_cpus)
905{
39ce010d 906 /* request the 0x1201 emergency signal external interrupt */
1dad093b 907 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 908 panic("Couldn't request external interrupt 0x1201");
d98e19cc 909 /* request the 0x1202 external call external interrupt */
1dad093b 910 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 911 panic("Couldn't request external interrupt 0x1202");
8b646bd7 912 smp_detect_cpus();
1da177e4
LT
913}
914
ea1f4eec 915void __init smp_prepare_boot_cpu(void)
1da177e4 916{
8b646bd7
MS
917 struct pcpu *pcpu = pcpu_devices;
918
8b646bd7 919 pcpu->state = CPU_STATE_CONFIGURED;
10ad34bc 920 pcpu->address = stap();
8b646bd7 921 pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix();
1da177e4 922 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 923 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
8b646bd7
MS
924 set_cpu_present(0, true);
925 set_cpu_online(0, true);
1da177e4
LT
926}
927
ea1f4eec 928void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 929{
1da177e4
LT
930}
931
02beaccc
HC
932void __init smp_setup_processor_id(void)
933{
934 S390_lowcore.cpu_nr = 0;
6c8cd5bb 935 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
02beaccc
HC
936}
937
1da177e4
LT
938/*
939 * the frequency of the profiling timer can be changed
940 * by writing a multiplier value into /proc/profile.
941 *
942 * usually you want to run this on all CPUs ;)
943 */
944int setup_profiling_timer(unsigned int multiplier)
945{
39ce010d 946 return 0;
1da177e4
LT
947}
948
08d07968 949#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 950static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 951 struct device_attribute *attr, char *buf)
08d07968
HC
952{
953 ssize_t count;
954
955 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 956 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
957 mutex_unlock(&smp_cpu_state_mutex);
958 return count;
959}
960
8a25a2fd 961static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
962 struct device_attribute *attr,
963 const char *buf, size_t count)
08d07968 964{
8b646bd7 965 struct pcpu *pcpu;
10ad34bc 966 int cpu, val, rc, i;
08d07968
HC
967 char delim;
968
969 if (sscanf(buf, "%d %c", &val, &delim) != 1)
970 return -EINVAL;
971 if (val != 0 && val != 1)
972 return -EINVAL;
9d40d2e3 973 get_online_cpus();
0b18d318 974 mutex_lock(&smp_cpu_state_mutex);
08d07968 975 rc = -EBUSY;
2c2df118 976 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 977 cpu = dev->id;
10ad34bc
MS
978 cpu -= cpu % (smp_cpu_mtid + 1);
979 if (cpu == 0)
08d07968 980 goto out;
10ad34bc
MS
981 for (i = 0; i <= smp_cpu_mtid; i++)
982 if (cpu_online(cpu + i))
983 goto out;
8b646bd7 984 pcpu = pcpu_devices + cpu;
08d07968
HC
985 rc = 0;
986 switch (val) {
987 case 0:
8b646bd7
MS
988 if (pcpu->state != CPU_STATE_CONFIGURED)
989 break;
d08d9430 990 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
991 if (rc)
992 break;
10ad34bc
MS
993 for (i = 0; i <= smp_cpu_mtid; i++) {
994 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
995 continue;
996 pcpu[i].state = CPU_STATE_STANDBY;
997 smp_cpu_set_polarization(cpu + i,
998 POLARIZATION_UNKNOWN);
999 }
8b646bd7 1000 topology_expect_change();
08d07968
HC
1001 break;
1002 case 1:
8b646bd7
MS
1003 if (pcpu->state != CPU_STATE_STANDBY)
1004 break;
d08d9430 1005 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1006 if (rc)
1007 break;
10ad34bc
MS
1008 for (i = 0; i <= smp_cpu_mtid; i++) {
1009 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1010 continue;
1011 pcpu[i].state = CPU_STATE_CONFIGURED;
1012 smp_cpu_set_polarization(cpu + i,
1013 POLARIZATION_UNKNOWN);
1014 }
8b646bd7 1015 topology_expect_change();
08d07968
HC
1016 break;
1017 default:
1018 break;
1019 }
1020out:
08d07968 1021 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1022 put_online_cpus();
08d07968
HC
1023 return rc ? rc : count;
1024}
8a25a2fd 1025static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968
HC
1026#endif /* CONFIG_HOTPLUG_CPU */
1027
8a25a2fd
KS
1028static ssize_t show_cpu_address(struct device *dev,
1029 struct device_attribute *attr, char *buf)
08d07968 1030{
8b646bd7 1031 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1032}
8a25a2fd 1033static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1034
08d07968
HC
1035static struct attribute *cpu_common_attrs[] = {
1036#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1037 &dev_attr_configure.attr,
08d07968 1038#endif
8a25a2fd 1039 &dev_attr_address.attr,
08d07968
HC
1040 NULL,
1041};
1042
1043static struct attribute_group cpu_common_attr_group = {
1044 .attrs = cpu_common_attrs,
1045};
1da177e4 1046
08d07968 1047static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1048 &dev_attr_idle_count.attr,
1049 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1050 NULL,
1051};
1052
08d07968
HC
1053static struct attribute_group cpu_online_attr_group = {
1054 .attrs = cpu_online_attrs,
fae8b22d
HC
1055};
1056
e2741f17
PG
1057static int smp_cpu_notify(struct notifier_block *self, unsigned long action,
1058 void *hcpu)
2fc2d1e9
HC
1059{
1060 unsigned int cpu = (unsigned int)(long)hcpu;
2f859d0d 1061 struct device *s = &per_cpu(cpu_device, cpu)->dev;
d882ba69 1062 int err = 0;
2fc2d1e9 1063
1c725922 1064 switch (action & ~CPU_TASKS_FROZEN) {
2fc2d1e9 1065 case CPU_ONLINE:
d882ba69 1066 err = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
2fc2d1e9
HC
1067 break;
1068 case CPU_DEAD:
08d07968 1069 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
2fc2d1e9
HC
1070 break;
1071 }
d882ba69 1072 return notifier_from_errno(err);
2fc2d1e9
HC
1073}
1074
e2741f17 1075static int smp_add_present_cpu(int cpu)
08d07968 1076{
96619fc1
HC
1077 struct device *s;
1078 struct cpu *c;
08d07968
HC
1079 int rc;
1080
96619fc1
HC
1081 c = kzalloc(sizeof(*c), GFP_KERNEL);
1082 if (!c)
1083 return -ENOMEM;
2f859d0d 1084 per_cpu(cpu_device, cpu) = c;
96619fc1 1085 s = &c->dev;
08d07968
HC
1086 c->hotpluggable = 1;
1087 rc = register_cpu(c, cpu);
1088 if (rc)
1089 goto out;
1090 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1091 if (rc)
1092 goto out_cpu;
83a24e32
HC
1093 if (cpu_online(cpu)) {
1094 rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1095 if (rc)
1096 goto out_online;
1097 }
1098 rc = topology_cpu_init(c);
1099 if (rc)
1100 goto out_topology;
1101 return 0;
1102
1103out_topology:
1104 if (cpu_online(cpu))
1105 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1106out_online:
08d07968
HC
1107 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1108out_cpu:
1109#ifdef CONFIG_HOTPLUG_CPU
1110 unregister_cpu(c);
1111#endif
1112out:
1113 return rc;
1114}
1115
1116#ifdef CONFIG_HOTPLUG_CPU
1e489518 1117
67060d9c 1118int __ref smp_rescan_cpus(void)
08d07968 1119{
d08d9430 1120 struct sclp_core_info *info;
8b646bd7 1121 int nr;
08d07968 1122
d08d9430 1123 info = smp_get_core_info();
8b646bd7
MS
1124 if (!info)
1125 return -ENOMEM;
9d40d2e3 1126 get_online_cpus();
0b18d318 1127 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1128 nr = __smp_rescan_cpus(info, 1);
08d07968 1129 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1130 put_online_cpus();
8b646bd7
MS
1131 kfree(info);
1132 if (nr)
c10fde0d 1133 topology_schedule_update();
8b646bd7 1134 return 0;
1e489518
HC
1135}
1136
8a25a2fd
KS
1137static ssize_t __ref rescan_store(struct device *dev,
1138 struct device_attribute *attr,
c9be0a36 1139 const char *buf,
1e489518
HC
1140 size_t count)
1141{
1142 int rc;
1143
1144 rc = smp_rescan_cpus();
08d07968
HC
1145 return rc ? rc : count;
1146}
8a25a2fd 1147static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
08d07968
HC
1148#endif /* CONFIG_HOTPLUG_CPU */
1149
83a24e32 1150static int __init s390_smp_init(void)
1da177e4 1151{
f4edbcd5 1152 int cpu, rc = 0;
2fc2d1e9 1153
08d07968 1154#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1155 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1156 if (rc)
1157 return rc;
1158#endif
f4edbcd5 1159 cpu_notifier_register_begin();
08d07968
HC
1160 for_each_present_cpu(cpu) {
1161 rc = smp_add_present_cpu(cpu);
fae8b22d 1162 if (rc)
f4edbcd5 1163 goto out;
1da177e4 1164 }
f4edbcd5
SB
1165
1166 __hotcpu_notifier(smp_cpu_notify, 0);
1167
1168out:
1169 cpu_notifier_register_done();
1170 return rc;
1da177e4 1171}
83a24e32 1172subsys_initcall(s390_smp_init);