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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
8b646bd7 3 * SMP related functions
1da177e4 4 *
a53c8fab 5 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
6 * Author(s): Denis Joseph Barrow,
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
8 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 9 *
39ce010d 10 * based on other smp stuff by
1da177e4
LT
11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
12 * (c) 1998 Ingo Molnar
13 *
8b646bd7
MS
14 * The code outside of smp.c uses logical cpu numbers, only smp.c does
15 * the translation of logical to physical cpu ids. All new code that
16 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
17 */
18
395d31d4
MS
19#define KMSG_COMPONENT "cpu"
20#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
f230886b 22#include <linux/workqueue.h>
af51160e 23#include <linux/bootmem.h>
3994a52b 24#include <linux/export.h>
1da177e4 25#include <linux/init.h>
1da177e4 26#include <linux/mm.h>
4e950f6f 27#include <linux/err.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/kernel_stat.h>
9cf8edb7 30#include <linux/kmemleak.h>
1da177e4 31#include <linux/delay.h>
1da177e4 32#include <linux/interrupt.h>
3324e60a 33#include <linux/irqflags.h>
1da177e4 34#include <linux/cpu.h>
5a0e3ad6 35#include <linux/slab.h>
ef8bd77f 36#include <linux/sched/hotplug.h>
68db0cf1 37#include <linux/sched/task_stack.h>
60a0c68d 38#include <linux/crash_dump.h>
1592a8e4 39#include <linux/memblock.h>
00a8f886 40#include <linux/kprobes.h>
cbb870c8 41#include <asm/asm-offsets.h>
1ec2772e 42#include <asm/diag.h>
1e3cab2f
HC
43#include <asm/switch_to.h>
44#include <asm/facility.h>
46b05d26 45#include <asm/ipl.h>
2b67fc46 46#include <asm/setup.h>
1da177e4 47#include <asm/irq.h>
1da177e4 48#include <asm/tlbflush.h>
27f6b416 49#include <asm/vtimer.h>
411ed322 50#include <asm/lowcore.h>
08d07968 51#include <asm/sclp.h>
c742b31c 52#include <asm/vdso.h>
3ab121ab 53#include <asm/debug.h>
4857d4bb 54#include <asm/os_info.h>
a9ae32c3 55#include <asm/sigp.h>
b5f87f15 56#include <asm/idle.h>
916cda1a 57#include <asm/nmi.h>
38389ec8 58#include <asm/topology.h>
a806170e 59#include "entry.h"
1da177e4 60
8b646bd7
MS
61enum {
62 ec_schedule = 0,
8b646bd7
MS
63 ec_call_function_single,
64 ec_stop_cpu,
65};
08d07968 66
8b646bd7 67enum {
08d07968
HC
68 CPU_STATE_STANDBY,
69 CPU_STATE_CONFIGURED,
70};
71
2f859d0d
HC
72static DEFINE_PER_CPU(struct cpu *, cpu_device);
73
8b646bd7 74struct pcpu {
c667aeac 75 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 76 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 77 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
78 signed char state; /* physical cpu state */
79 signed char polarization; /* physical polarization */
8b646bd7
MS
80 u16 address; /* physical cpu address */
81};
82
d08d9430 83static u8 boot_core_type;
8b646bd7
MS
84static struct pcpu pcpu_devices[NR_CPUS];
85
10ad34bc
MS
86unsigned int smp_cpu_mt_shift;
87EXPORT_SYMBOL(smp_cpu_mt_shift);
88
89unsigned int smp_cpu_mtid;
90EXPORT_SYMBOL(smp_cpu_mtid);
91
1a36a39e
MS
92#ifdef CONFIG_CRASH_DUMP
93__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
94#endif
95
10ad34bc
MS
96static unsigned int smp_max_threads __initdata = -1U;
97
98static int __init early_nosmt(char *s)
99{
100 smp_max_threads = 1;
101 return 0;
102}
103early_param("nosmt", early_nosmt);
104
105static int __init early_smt(char *s)
106{
107 get_option(&s, &smp_max_threads);
108 return 0;
109}
110early_param("smt", early_smt);
111
50ab9a9a
HC
112/*
113 * The smp_cpu_state_mutex must be held when changing the state or polarization
114 * member of a pcpu data structure within the pcpu_devices arreay.
115 */
dbd70fb4 116DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 117
8b646bd7
MS
118/*
119 * Signal processor helper functions.
120 */
1a36a39e 121static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 122{
8b646bd7 123 int cc;
5c0b912e 124
8b646bd7 125 while (1) {
c5e3acd6 126 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 127 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
128 return cc;
129 cpu_relax();
5c0b912e 130 }
5c0b912e
HC
131}
132
8b646bd7 133static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 134{
8b646bd7
MS
135 int cc, retry;
136
137 for (retry = 0; ; retry++) {
c5e3acd6 138 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 139 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
140 break;
141 if (retry >= 3)
142 udelay(10);
143 }
144 return cc;
145}
146
147static inline int pcpu_stopped(struct pcpu *pcpu)
148{
41459d36 149 u32 uninitialized_var(status);
c5e3acd6 150
a9ae32c3 151 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 152 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 153 return 0;
c5e3acd6 154 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
155}
156
157static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 158{
a9ae32c3 159 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 160 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 161 return 1;
524b24ad
HC
162 /* Status stored condition code is equivalent to cpu not running. */
163 return 0;
a93b8ec1
HC
164}
165
1943f53c 166/*
8b646bd7 167 * Find struct pcpu by cpu address.
1943f53c 168 */
10ad34bc 169static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
170{
171 int cpu;
172
8b646bd7
MS
173 for_each_cpu(cpu, mask)
174 if (pcpu_devices[cpu].address == address)
175 return pcpu_devices + cpu;
176 return NULL;
177}
178
179static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
180{
181 int order;
182
dea24190
HC
183 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
184 return;
185 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 186 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
187 pcpu_sigp_retry(pcpu, order, 0);
188}
189
2f859d0d
HC
190#define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
191#define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
192
e2741f17 193static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 194{
2f859d0d 195 unsigned long async_stack, panic_stack;
c667aeac 196 struct lowcore *lc;
8b646bd7
MS
197
198 if (pcpu != &pcpu_devices[0]) {
c667aeac 199 pcpu->lowcore = (struct lowcore *)
8b646bd7 200 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
2f859d0d
HC
201 async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
202 panic_stack = __get_free_page(GFP_KERNEL);
203 if (!pcpu->lowcore || !panic_stack || !async_stack)
8b646bd7 204 goto out;
2f859d0d
HC
205 } else {
206 async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
207 panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
1943f53c 208 }
8b646bd7
MS
209 lc = pcpu->lowcore;
210 memcpy(lc, &S390_lowcore, 512);
211 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
2f859d0d
HC
212 lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
213 lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
8b646bd7 214 lc->cpu_nr = cpu;
6c8cd5bb 215 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 216 lc->spinlock_index = 0;
6c81511c 217 if (nmi_alloc_per_cpu(lc))
8b646bd7 218 goto out;
6c81511c
MS
219 if (vdso_alloc_per_cpu(lc))
220 goto out_mcesa;
8b646bd7 221 lowcore_ptr[cpu] = lc;
a9ae32c3 222 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7 223 return 0;
6c81511c
MS
224
225out_mcesa:
226 nmi_free_per_cpu(lc);
8b646bd7
MS
227out:
228 if (pcpu != &pcpu_devices[0]) {
2f859d0d
HC
229 free_page(panic_stack);
230 free_pages(async_stack, ASYNC_ORDER);
8b646bd7
MS
231 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
232 }
233 return -ENOMEM;
1943f53c
MH
234}
235
9d0f46af
HC
236#ifdef CONFIG_HOTPLUG_CPU
237
8b646bd7 238static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 239{
a9ae32c3 240 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 241 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 242 vdso_free_per_cpu(pcpu->lowcore);
6c81511c 243 nmi_free_per_cpu(pcpu->lowcore);
2f859d0d
HC
244 if (pcpu == &pcpu_devices[0])
245 return;
246 free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
247 free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
248 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
8b646bd7
MS
249}
250
9d0f46af
HC
251#endif /* CONFIG_HOTPLUG_CPU */
252
8b646bd7
MS
253static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
254{
c667aeac 255 struct lowcore *lc = pcpu->lowcore;
8b646bd7 256
64f31d58 257 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 258 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 259 lc->cpu_nr = cpu;
6c8cd5bb 260 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 261 lc->spinlock_index = 0;
8b646bd7
MS
262 lc->percpu_offset = __per_cpu_offset[cpu];
263 lc->kernel_asce = S390_lowcore.kernel_asce;
264 lc->machine_flags = S390_lowcore.machine_flags;
8b646bd7
MS
265 lc->user_timer = lc->system_timer = lc->steal_timer = 0;
266 __ctl_store(lc->cregs_save_area, 0, 15);
267 save_access_regs((unsigned int *) lc->access_regs_save_area);
268 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
269 MAX_FACILITY_BIT/8);
b96f7d88 270 arch_spin_lock_setup(cpu);
8b646bd7
MS
271}
272
273static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
274{
c667aeac 275 struct lowcore *lc = pcpu->lowcore;
8b646bd7 276
dc7ee00d
MS
277 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
278 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 279 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
280 lc->lpp = LPP_MAGIC;
281 lc->current_pid = tsk->pid;
90c53e65 282 lc->user_timer = tsk->thread.user_timer;
b7662eef 283 lc->guest_timer = tsk->thread.guest_timer;
90c53e65 284 lc->system_timer = tsk->thread.system_timer;
b7662eef
CB
285 lc->hardirq_timer = tsk->thread.hardirq_timer;
286 lc->softirq_timer = tsk->thread.softirq_timer;
8b646bd7
MS
287 lc->steal_timer = 0;
288}
289
290static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
291{
c667aeac 292 struct lowcore *lc = pcpu->lowcore;
8b646bd7
MS
293
294 lc->restart_stack = lc->kernel_stack;
295 lc->restart_fn = (unsigned long) func;
296 lc->restart_data = (unsigned long) data;
297 lc->restart_source = -1UL;
a9ae32c3 298 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
299}
300
301/*
302 * Call function via PSW restart on pcpu and stop the current cpu.
303 */
304static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
305 void *data, unsigned long stack)
306{
c667aeac 307 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 308 unsigned long source_cpu = stap();
8b646bd7 309
e258d719 310 __load_psw_mask(PSW_KERNEL_BITS);
fbe76568 311 if (pcpu->address == source_cpu)
8b646bd7
MS
312 func(data); /* should not return */
313 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 314 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 315 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
316 mem_assign_absolute(lc->restart_stack, stack);
317 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
318 mem_assign_absolute(lc->restart_data, (unsigned long) data);
319 mem_assign_absolute(lc->restart_source, source_cpu);
8b646bd7 320 asm volatile(
eb546195 321 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 322 " brc 2,0b # busy, try again\n"
eb546195 323 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 324 " brc 2,1b # busy, try again\n"
fbe76568 325 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
326 "K" (SIGP_RESTART), "K" (SIGP_STOP)
327 : "0", "1", "cc");
8b646bd7
MS
328 for (;;) ;
329}
330
10ad34bc
MS
331/*
332 * Enable additional logical cpus for multi-threading.
333 */
334static int pcpu_set_smt(unsigned int mtid)
335{
10ad34bc
MS
336 int cc;
337
338 if (smp_cpu_mtid == mtid)
339 return 0;
80a60f6e 340 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
341 if (cc == 0) {
342 smp_cpu_mtid = mtid;
343 smp_cpu_mt_shift = 0;
344 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
345 smp_cpu_mt_shift++;
346 pcpu_devices[0].address = stap();
347 }
348 return cc;
349}
350
8b646bd7
MS
351/*
352 * Call function on an online CPU.
353 */
354void smp_call_online_cpu(void (*func)(void *), void *data)
355{
356 struct pcpu *pcpu;
357
358 /* Use the current cpu if it is online. */
359 pcpu = pcpu_find_address(cpu_online_mask, stap());
360 if (!pcpu)
361 /* Use the first online cpu. */
362 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
363 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
364}
365
366/*
367 * Call function on the ipl CPU.
368 */
369void smp_call_ipl_cpu(void (*func)(void *), void *data)
370{
c6da39f2 371 pcpu_delegate(&pcpu_devices[0], func, data,
2f859d0d
HC
372 pcpu_devices->lowcore->panic_stack -
373 PANIC_FRAME_OFFSET + PAGE_SIZE);
8b646bd7
MS
374}
375
376int smp_find_processor_id(u16 address)
377{
378 int cpu;
379
380 for_each_present_cpu(cpu)
381 if (pcpu_devices[cpu].address == address)
382 return cpu;
383 return -1;
2c2df118
HC
384}
385
760928c0 386bool arch_vcpu_is_preempted(int cpu)
85ac7ca5 387{
760928c0
CB
388 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
389 return false;
390 if (pcpu_running(pcpu_devices + cpu))
391 return false;
392 return true;
8b646bd7 393}
760928c0 394EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 395
8b646bd7 396void smp_yield_cpu(int cpu)
85ac7ca5 397{
1ec2772e 398 if (MACHINE_HAS_DIAG9C) {
b5a6b71b 399 diag_stat_inc_norecursion(DIAG_STAT_X09C);
8b646bd7
MS
400 asm volatile("diag %0,0,0x9c"
401 : : "d" (pcpu_devices[cpu].address));
1ec2772e 402 } else if (MACHINE_HAS_DIAG44) {
b5a6b71b 403 diag_stat_inc_norecursion(DIAG_STAT_X044);
8b646bd7 404 asm volatile("diag 0,0,0x44");
1ec2772e 405 }
8b646bd7
MS
406}
407
408/*
409 * Send cpus emergency shutdown signal. This gives the cpus the
410 * opportunity to complete outstanding interrupts.
411 */
00a8f886 412void notrace smp_emergency_stop(void)
8b646bd7 413{
00a8f886 414 cpumask_t cpumask;
8b646bd7
MS
415 u64 end;
416 int cpu;
417
00a8f886
MS
418 cpumask_copy(&cpumask, cpu_online_mask);
419 cpumask_clear_cpu(smp_processor_id(), &cpumask);
420
1aae0560 421 end = get_tod_clock() + (1000000UL << 12);
00a8f886 422 for_each_cpu(cpu, &cpumask) {
8b646bd7
MS
423 struct pcpu *pcpu = pcpu_devices + cpu;
424 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
425 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
426 0, NULL) == SIGP_CC_BUSY &&
1aae0560 427 get_tod_clock() < end)
8b646bd7
MS
428 cpu_relax();
429 }
1aae0560 430 while (get_tod_clock() < end) {
00a8f886 431 for_each_cpu(cpu, &cpumask)
8b646bd7 432 if (pcpu_stopped(pcpu_devices + cpu))
00a8f886
MS
433 cpumask_clear_cpu(cpu, &cpumask);
434 if (cpumask_empty(&cpumask))
8b646bd7 435 break;
85ac7ca5 436 cpu_relax();
8b646bd7 437 }
85ac7ca5 438}
00a8f886 439NOKPROBE_SYMBOL(smp_emergency_stop);
85ac7ca5 440
8b646bd7
MS
441/*
442 * Stop all cpus but the current one.
443 */
677d7623 444void smp_send_stop(void)
1da177e4 445{
85ac7ca5 446 int cpu;
1da177e4 447
677d7623 448 /* Disable all interrupts/machine checks */
e258d719 449 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 450 trace_hardirqs_off();
1da177e4 451
3ab121ab 452 debug_set_critical();
85ac7ca5 453
8b646bd7 454 if (oops_in_progress)
00a8f886 455 smp_emergency_stop();
1da177e4 456
85ac7ca5 457 /* stop all processors */
00a8f886
MS
458 for_each_online_cpu(cpu) {
459 if (cpu == smp_processor_id())
460 continue;
461 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
462 while (!pcpu_stopped(pcpu_devices + cpu))
c6b5b847
HC
463 cpu_relax();
464 }
465}
466
1da177e4
LT
467/*
468 * This is the main routine where commands issued by other
469 * cpus are handled.
470 */
9acf73b7 471static void smp_handle_ext_call(void)
1da177e4 472{
39ce010d 473 unsigned long bits;
1da177e4 474
9acf73b7
HC
475 /* handle bit signal external calls */
476 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
477 if (test_bit(ec_stop_cpu, &bits))
478 smp_stop_cpu();
184748cc
PZ
479 if (test_bit(ec_schedule, &bits))
480 scheduler_ipi();
ca9fc75a
HC
481 if (test_bit(ec_call_function_single, &bits))
482 generic_smp_call_function_single_interrupt();
9acf73b7 483}
85ac7ca5 484
9acf73b7
HC
485static void do_ext_call_interrupt(struct ext_code ext_code,
486 unsigned int param32, unsigned long param64)
487{
488 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
489 smp_handle_ext_call();
1da177e4
LT
490}
491
630cd046 492void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
493{
494 int cpu;
495
630cd046 496 for_each_cpu(cpu, mask)
b6ed49e0 497 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
498}
499
500void arch_send_call_function_single_ipi(int cpu)
501{
8b646bd7 502 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
503}
504
1da177e4
LT
505/*
506 * this function sends a 'reschedule' IPI to another CPU.
507 * it goes straight through and wastes no time serializing
508 * anything. Worst case is that we lose a reschedule ...
509 */
510void smp_send_reschedule(int cpu)
511{
8b646bd7 512 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
513}
514
515/*
516 * parameter area for the set/clear control bit callbacks
517 */
94c12cc7 518struct ec_creg_mask_parms {
8b646bd7
MS
519 unsigned long orval;
520 unsigned long andval;
521 int cr;
94c12cc7 522};
1da177e4
LT
523
524/*
525 * callback for setting/clearing control bits
526 */
39ce010d
HC
527static void smp_ctl_bit_callback(void *info)
528{
94c12cc7 529 struct ec_creg_mask_parms *pp = info;
1da177e4 530 unsigned long cregs[16];
39ce010d 531
94c12cc7 532 __ctl_store(cregs, 0, 15);
8b646bd7 533 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 534 __ctl_load(cregs, 0, 15);
1da177e4
LT
535}
536
537/*
538 * Set a bit in a control register of all cpus
539 */
94c12cc7
MS
540void smp_ctl_set_bit(int cr, int bit)
541{
8b646bd7 542 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 543
15c8b6c1 544 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 545}
39ce010d 546EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
547
548/*
549 * Clear a bit in a control register of all cpus
550 */
94c12cc7
MS
551void smp_ctl_clear_bit(int cr, int bit)
552{
8b646bd7 553 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 554
15c8b6c1 555 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 556}
39ce010d 557EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 558
bf28a597 559#ifdef CONFIG_CRASH_DUMP
411ed322 560
1af135a1
HC
561int smp_store_status(int cpu)
562{
1a36a39e
MS
563 struct pcpu *pcpu = pcpu_devices + cpu;
564 unsigned long pa;
1af135a1 565
1a36a39e
MS
566 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
567 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
568 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1 569 return -EIO;
916cda1a 570 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
1af135a1 571 return 0;
916cda1a
MS
572 pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
573 if (MACHINE_HAS_GS)
574 pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
1a36a39e
MS
575 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
576 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
577 return -EIO;
1af135a1
HC
578 return 0;
579}
580
10ad34bc
MS
581/*
582 * Collect CPU state of the previous, crashed system.
583 * There are four cases:
584 * 1) standard zfcp dump
585 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
586 * The state for all CPUs except the boot CPU needs to be collected
587 * with sigp stop-and-store-status. The boot CPU state is located in
588 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 589 * will copy the boot CPU state from the HSA.
10ad34bc
MS
590 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
591 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
592 * The state for all CPUs except the boot CPU needs to be collected
593 * with sigp stop-and-store-status. The firmware or the boot-loader
594 * stored the registers of the boot CPU in the absolute lowcore in the
595 * memory of the old system.
596 * 3) kdump and the old kernel did not store the CPU state,
597 * or stand-alone kdump for DASD
598 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
599 * The state for all CPUs except the boot CPU needs to be collected
600 * with sigp stop-and-store-status. The kexec code or the boot-loader
601 * stored the registers of the boot CPU in the memory of the old system.
602 * 4) kdump and the old kernel stored the CPU state
603 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
604 * This case does not exist for s390 anymore, setup_arch explicitly
605 * deactivates the elfcorehdr= kernel parameter
10ad34bc 606 */
1a2c5840 607static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
608 bool is_boot_cpu, unsigned long page)
609{
610 __vector128 *vxrs = (__vector128 *) page;
611
612 if (is_boot_cpu)
613 vxrs = boot_cpu_vector_save_area;
614 else
615 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 616 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
617}
618
1a2c5840 619static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
620 bool is_boot_cpu, unsigned long page)
621{
622 void *regs = (void *) page;
623
624 if (is_boot_cpu)
625 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
626 else
627 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 628 save_area_add_regs(sa, regs);
1a36a39e
MS
629}
630
1592a8e4 631void __init smp_save_dump_cpus(void)
10ad34bc 632{
1a2c5840
MS
633 int addr, boot_cpu_addr, max_cpu_addr;
634 struct save_area *sa;
1a36a39e 635 unsigned long page;
1592a8e4 636 bool is_boot_cpu;
10ad34bc 637
10ad34bc
MS
638 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
639 /* No previous system present, normal boot. */
640 return;
1a36a39e
MS
641 /* Allocate a page as dumping area for the store status sigps */
642 page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
10ad34bc 643 /* Set multi-threading state to the previous system. */
37c5f6c8 644 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 645 boot_cpu_addr = stap();
1a2c5840
MS
646 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
647 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 648 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
649 SIGP_CC_NOT_OPERATIONAL)
650 continue;
1592a8e4 651 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
652 /* Allocate save area */
653 sa = save_area_alloc(is_boot_cpu);
654 if (!sa)
655 panic("could not allocate memory for save area\n");
1a36a39e
MS
656 if (MACHINE_HAS_VX)
657 /* Get the vector registers */
1a2c5840 658 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
659 /*
660 * For a zfcp dump OLDMEM_BASE == NULL and the registers
661 * of the boot CPU are stored in the HSA. To retrieve
662 * these registers an SCLP request is required which is
663 * done by drivers/s390/char/zcore.c:init_cpu_info()
664 */
665 if (!is_boot_cpu || OLDMEM_BASE)
666 /* Get the CPU registers */
1a2c5840 667 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 668 }
1a36a39e 669 memblock_free(page, PAGE_SIZE);
1592a8e4
MH
670 diag308_reset();
671 pcpu_set_smt(0);
1af135a1 672}
1a36a39e 673#endif /* CONFIG_CRASH_DUMP */
08d07968 674
50ab9a9a
HC
675void smp_cpu_set_polarization(int cpu, int val)
676{
677 pcpu_devices[cpu].polarization = val;
678}
679
680int smp_cpu_get_polarization(int cpu)
681{
682 return pcpu_devices[cpu].polarization;
683}
684
af51160e 685static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 686{
8b646bd7 687 static int use_sigp_detection;
8b646bd7
MS
688 int address;
689
af51160e 690 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 691 use_sigp_detection = 1;
e7086eb1 692 for (address = 0;
d08d9430 693 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 694 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 695 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 696 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 697 continue;
d08d9430 698 info->core[info->configured].core_id =
10ad34bc 699 address >> smp_cpu_mt_shift;
8b646bd7
MS
700 info->configured++;
701 }
702 info->combined = info->configured;
08d07968 703 }
08d07968
HC
704}
705
e2741f17 706static int smp_add_present_cpu(int cpu);
8b646bd7 707
d08d9430 708static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 709{
8b646bd7 710 struct pcpu *pcpu;
08d07968 711 cpumask_t avail;
10ad34bc
MS
712 int cpu, nr, i, j;
713 u16 address;
08d07968 714
8b646bd7 715 nr = 0;
0f1959f5 716 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
717 cpu = cpumask_first(&avail);
718 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 719 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 720 continue;
d08d9430 721 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
722 for (j = 0; j <= smp_cpu_mtid; j++) {
723 if (pcpu_find_address(cpu_present_mask, address + j))
724 continue;
725 pcpu = pcpu_devices + cpu;
726 pcpu->address = address + j;
727 pcpu->state =
728 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
729 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
730 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
731 set_cpu_present(cpu, true);
732 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
733 set_cpu_present(cpu, false);
734 else
735 nr++;
736 cpu = cpumask_next(cpu, &avail);
737 if (cpu >= nr_cpu_ids)
738 break;
739 }
8b646bd7
MS
740 }
741 return nr;
1da177e4
LT
742}
743
af51160e 744void __init smp_detect_cpus(void)
48483b32 745{
10ad34bc 746 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 747 struct sclp_core_info *info;
10ad34bc 748 u16 address;
48483b32 749
10ad34bc 750 /* Get CPU information */
af51160e
HC
751 info = memblock_virt_alloc(sizeof(*info), 8);
752 smp_get_core_info(info, 1);
10ad34bc 753 /* Find boot CPU type */
d08d9430 754 if (sclp.has_core_type) {
10ad34bc
MS
755 address = stap();
756 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 757 if (info->core[cpu].core_id == address) {
10ad34bc 758 /* The boot cpu dictates the cpu type. */
d08d9430 759 boot_core_type = info->core[cpu].type;
10ad34bc
MS
760 break;
761 }
762 if (cpu >= info->combined)
763 panic("Could not find boot CPU type");
48483b32 764 }
10ad34bc 765
10ad34bc 766 /* Set multi-threading state for the current system */
d08d9430 767 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
768 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
769 pcpu_set_smt(mtid);
770
771 /* Print number of CPUs */
8b646bd7 772 c_cpus = s_cpus = 0;
48483b32 773 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
774 if (sclp.has_core_type &&
775 info->core[cpu].type != boot_core_type)
48483b32 776 continue;
10ad34bc
MS
777 if (cpu < info->configured)
778 c_cpus += smp_cpu_mtid + 1;
779 else
780 s_cpus += smp_cpu_mtid + 1;
48483b32 781 }
395d31d4 782 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
783
784 /* Add CPUs present at boot */
9d40d2e3 785 get_online_cpus();
8b646bd7 786 __smp_rescan_cpus(info, 0);
9d40d2e3 787 put_online_cpus();
af51160e 788 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
789}
790
1da177e4 791/*
39ce010d 792 * Activate a secondary processor.
1da177e4 793 */
e2741f17 794static void smp_start_secondary(void *cpuvoid)
1da177e4 795{
1887aa07
MS
796 int cpu = smp_processor_id();
797
1aae0560 798 S390_lowcore.last_update_clock = get_tod_clock();
8b646bd7
MS
799 S390_lowcore.restart_stack = (unsigned long) restart_stack;
800 S390_lowcore.restart_fn = (unsigned long) do_restart;
801 S390_lowcore.restart_data = 0;
802 S390_lowcore.restart_source = -1UL;
803 restore_access_regs(S390_lowcore.access_regs_save_area);
804 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
e258d719 805 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
39ce010d 806 cpu_init();
5bfb5d69 807 preempt_disable();
39ce010d 808 init_cpu_timer();
b5f87f15 809 vtime_init();
29b08d2b 810 pfault_init();
1887aa07
MS
811 notify_cpu_starting(cpu);
812 if (topology_cpu_dedicated(cpu))
813 set_cpu_flag(CIF_DEDICATED_CPU);
814 else
815 clear_cpu_flag(CIF_DEDICATED_CPU);
816 set_cpu_online(cpu, true);
93f3b2ee 817 inc_irq_stat(CPU_RST);
1da177e4 818 local_irq_enable();
fc6d73d6 819 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
820}
821
1da177e4 822/* Upping and downing of CPUs */
e2741f17 823int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 824{
8b646bd7 825 struct pcpu *pcpu;
10ad34bc 826 int base, i, rc;
1da177e4 827
8b646bd7
MS
828 pcpu = pcpu_devices + cpu;
829 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 830 return -EIO;
5423145f 831 base = smp_get_base_cpu(cpu);
10ad34bc
MS
832 for (i = 0; i <= smp_cpu_mtid; i++) {
833 if (base + i < nr_cpu_ids)
834 if (cpu_online(base + i))
835 break;
836 }
837 /*
838 * If this is the first CPU of the core to get online
839 * do an initial CPU reset.
840 */
841 if (i > smp_cpu_mtid &&
842 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 843 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 844 return -EIO;
e80e7813 845
8b646bd7
MS
846 rc = pcpu_alloc_lowcore(pcpu, cpu);
847 if (rc)
848 return rc;
849 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 850 pcpu_attach_task(pcpu, tidle);
8b646bd7 851 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 852 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 853 while (!cpu_online(cpu))
1da177e4
LT
854 cpu_relax();
855 return 0;
856}
857
d80512f8 858static unsigned int setup_possible_cpus __initdata;
255acee7 859
d80512f8
HC
860static int __init _setup_possible_cpus(char *s)
861{
862 get_option(&s, &setup_possible_cpus);
37a33026
HC
863 return 0;
864}
d80512f8 865early_param("possible_cpus", _setup_possible_cpus);
37a33026 866
48483b32
HC
867#ifdef CONFIG_HOTPLUG_CPU
868
39ce010d 869int __cpu_disable(void)
1da177e4 870{
8b646bd7 871 unsigned long cregs[16];
1da177e4 872
9acf73b7
HC
873 /* Handle possible pending IPIs */
874 smp_handle_ext_call();
8b646bd7
MS
875 set_cpu_online(smp_processor_id(), false);
876 /* Disable pseudo page faults on this cpu. */
29b08d2b 877 pfault_fini();
8b646bd7
MS
878 /* Disable interrupt sources via control register. */
879 __ctl_store(cregs, 0, 15);
880 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
881 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
882 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
883 __ctl_load(cregs, 0, 15);
fe0f4976 884 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
885 return 0;
886}
887
39ce010d 888void __cpu_die(unsigned int cpu)
1da177e4 889{
8b646bd7
MS
890 struct pcpu *pcpu;
891
1da177e4 892 /* Wait until target cpu is down */
8b646bd7
MS
893 pcpu = pcpu_devices + cpu;
894 while (!pcpu_stopped(pcpu))
1da177e4 895 cpu_relax();
8b646bd7 896 pcpu_free_lowcore(pcpu);
1b948d6c 897 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 898 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
899}
900
b456d94a 901void __noreturn cpu_die(void)
1da177e4
LT
902{
903 idle_task_exit();
a9ae32c3 904 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 905 for (;;) ;
1da177e4
LT
906}
907
255acee7
HC
908#endif /* CONFIG_HOTPLUG_CPU */
909
d80512f8
HC
910void __init smp_fill_possible_mask(void)
911{
9747bc47 912 unsigned int possible, sclp_max, cpu;
d80512f8 913
3a9f3fe6
DH
914 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
915 sclp_max = min(smp_max_threads, sclp_max);
61282aff 916 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 917 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 918 possible = min(possible, sclp_max);
d80512f8
HC
919 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
920 set_cpu_possible(cpu, true);
921}
922
1da177e4
LT
923void __init smp_prepare_cpus(unsigned int max_cpus)
924{
39ce010d 925 /* request the 0x1201 emergency signal external interrupt */
1dad093b 926 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 927 panic("Couldn't request external interrupt 0x1201");
d98e19cc 928 /* request the 0x1202 external call external interrupt */
1dad093b 929 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 930 panic("Couldn't request external interrupt 0x1202");
1da177e4
LT
931}
932
ea1f4eec 933void __init smp_prepare_boot_cpu(void)
1da177e4 934{
8b646bd7
MS
935 struct pcpu *pcpu = pcpu_devices;
936
0861b5a7 937 WARN_ON(!cpu_present(0) || !cpu_online(0));
8b646bd7 938 pcpu->state = CPU_STATE_CONFIGURED;
c667aeac 939 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 940 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 941 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1da177e4
LT
942}
943
ea1f4eec 944void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 945{
1da177e4
LT
946}
947
02beaccc
HC
948void __init smp_setup_processor_id(void)
949{
0861b5a7 950 pcpu_devices[0].address = stap();
02beaccc 951 S390_lowcore.cpu_nr = 0;
6c8cd5bb 952 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
b96f7d88 953 S390_lowcore.spinlock_index = 0;
02beaccc
HC
954}
955
1da177e4
LT
956/*
957 * the frequency of the profiling timer can be changed
958 * by writing a multiplier value into /proc/profile.
959 *
960 * usually you want to run this on all CPUs ;)
961 */
962int setup_profiling_timer(unsigned int multiplier)
963{
39ce010d 964 return 0;
1da177e4
LT
965}
966
08d07968 967#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 968static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 969 struct device_attribute *attr, char *buf)
08d07968
HC
970{
971 ssize_t count;
972
973 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 974 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
975 mutex_unlock(&smp_cpu_state_mutex);
976 return count;
977}
978
8a25a2fd 979static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
980 struct device_attribute *attr,
981 const char *buf, size_t count)
08d07968 982{
8b646bd7 983 struct pcpu *pcpu;
10ad34bc 984 int cpu, val, rc, i;
08d07968
HC
985 char delim;
986
987 if (sscanf(buf, "%d %c", &val, &delim) != 1)
988 return -EINVAL;
989 if (val != 0 && val != 1)
990 return -EINVAL;
9d40d2e3 991 get_online_cpus();
0b18d318 992 mutex_lock(&smp_cpu_state_mutex);
08d07968 993 rc = -EBUSY;
2c2df118 994 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 995 cpu = dev->id;
5423145f 996 cpu = smp_get_base_cpu(cpu);
10ad34bc 997 if (cpu == 0)
08d07968 998 goto out;
10ad34bc
MS
999 for (i = 0; i <= smp_cpu_mtid; i++)
1000 if (cpu_online(cpu + i))
1001 goto out;
8b646bd7 1002 pcpu = pcpu_devices + cpu;
08d07968
HC
1003 rc = 0;
1004 switch (val) {
1005 case 0:
8b646bd7
MS
1006 if (pcpu->state != CPU_STATE_CONFIGURED)
1007 break;
d08d9430 1008 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1009 if (rc)
1010 break;
10ad34bc
MS
1011 for (i = 0; i <= smp_cpu_mtid; i++) {
1012 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1013 continue;
1014 pcpu[i].state = CPU_STATE_STANDBY;
1015 smp_cpu_set_polarization(cpu + i,
1016 POLARIZATION_UNKNOWN);
1017 }
8b646bd7 1018 topology_expect_change();
08d07968
HC
1019 break;
1020 case 1:
8b646bd7
MS
1021 if (pcpu->state != CPU_STATE_STANDBY)
1022 break;
d08d9430 1023 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1024 if (rc)
1025 break;
10ad34bc
MS
1026 for (i = 0; i <= smp_cpu_mtid; i++) {
1027 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1028 continue;
1029 pcpu[i].state = CPU_STATE_CONFIGURED;
1030 smp_cpu_set_polarization(cpu + i,
1031 POLARIZATION_UNKNOWN);
1032 }
8b646bd7 1033 topology_expect_change();
08d07968
HC
1034 break;
1035 default:
1036 break;
1037 }
1038out:
08d07968 1039 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1040 put_online_cpus();
08d07968
HC
1041 return rc ? rc : count;
1042}
8a25a2fd 1043static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968
HC
1044#endif /* CONFIG_HOTPLUG_CPU */
1045
8a25a2fd
KS
1046static ssize_t show_cpu_address(struct device *dev,
1047 struct device_attribute *attr, char *buf)
08d07968 1048{
8b646bd7 1049 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1050}
8a25a2fd 1051static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1052
08d07968
HC
1053static struct attribute *cpu_common_attrs[] = {
1054#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1055 &dev_attr_configure.attr,
08d07968 1056#endif
8a25a2fd 1057 &dev_attr_address.attr,
08d07968
HC
1058 NULL,
1059};
1060
1061static struct attribute_group cpu_common_attr_group = {
1062 .attrs = cpu_common_attrs,
1063};
1da177e4 1064
08d07968 1065static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1066 &dev_attr_idle_count.attr,
1067 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1068 NULL,
1069};
1070
08d07968
HC
1071static struct attribute_group cpu_online_attr_group = {
1072 .attrs = cpu_online_attrs,
fae8b22d
HC
1073};
1074
dfbbd86a 1075static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1076{
2f859d0d 1077 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1078
dfbbd86a
SAS
1079 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1080}
1081static int smp_cpu_pre_down(unsigned int cpu)
1082{
1083 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1084
1085 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1086 return 0;
2fc2d1e9
HC
1087}
1088
e2741f17 1089static int smp_add_present_cpu(int cpu)
08d07968 1090{
96619fc1
HC
1091 struct device *s;
1092 struct cpu *c;
08d07968
HC
1093 int rc;
1094
96619fc1
HC
1095 c = kzalloc(sizeof(*c), GFP_KERNEL);
1096 if (!c)
1097 return -ENOMEM;
2f859d0d 1098 per_cpu(cpu_device, cpu) = c;
96619fc1 1099 s = &c->dev;
08d07968
HC
1100 c->hotpluggable = 1;
1101 rc = register_cpu(c, cpu);
1102 if (rc)
1103 goto out;
1104 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1105 if (rc)
1106 goto out_cpu;
83a24e32
HC
1107 rc = topology_cpu_init(c);
1108 if (rc)
1109 goto out_topology;
1110 return 0;
1111
1112out_topology:
08d07968
HC
1113 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1114out_cpu:
1115#ifdef CONFIG_HOTPLUG_CPU
1116 unregister_cpu(c);
1117#endif
1118out:
1119 return rc;
1120}
1121
1122#ifdef CONFIG_HOTPLUG_CPU
1e489518 1123
67060d9c 1124int __ref smp_rescan_cpus(void)
08d07968 1125{
d08d9430 1126 struct sclp_core_info *info;
8b646bd7 1127 int nr;
08d07968 1128
af51160e 1129 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1130 if (!info)
1131 return -ENOMEM;
af51160e 1132 smp_get_core_info(info, 0);
9d40d2e3 1133 get_online_cpus();
0b18d318 1134 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1135 nr = __smp_rescan_cpus(info, 1);
08d07968 1136 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1137 put_online_cpus();
8b646bd7
MS
1138 kfree(info);
1139 if (nr)
c10fde0d 1140 topology_schedule_update();
8b646bd7 1141 return 0;
1e489518
HC
1142}
1143
8a25a2fd
KS
1144static ssize_t __ref rescan_store(struct device *dev,
1145 struct device_attribute *attr,
c9be0a36 1146 const char *buf,
1e489518
HC
1147 size_t count)
1148{
1149 int rc;
1150
1151 rc = smp_rescan_cpus();
08d07968
HC
1152 return rc ? rc : count;
1153}
d6864bd8 1154static DEVICE_ATTR_WO(rescan);
08d07968
HC
1155#endif /* CONFIG_HOTPLUG_CPU */
1156
83a24e32 1157static int __init s390_smp_init(void)
1da177e4 1158{
f4edbcd5 1159 int cpu, rc = 0;
2fc2d1e9 1160
08d07968 1161#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1162 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1163 if (rc)
1164 return rc;
1165#endif
1166 for_each_present_cpu(cpu) {
1167 rc = smp_add_present_cpu(cpu);
fae8b22d 1168 if (rc)
f4edbcd5 1169 goto out;
1da177e4 1170 }
f4edbcd5 1171
dfbbd86a
SAS
1172 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1173 smp_cpu_online, smp_cpu_pre_down);
e1108e8f 1174 rc = rc <= 0 ? rc : 0;
f4edbcd5 1175out:
f4edbcd5 1176 return rc;
1da177e4 1177}
83a24e32 1178subsys_initcall(s390_smp_init);