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Commit | Line | Data |
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1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
1592a8e4 | 34 | #include <linux/memblock.h> |
cbb870c8 | 35 | #include <asm/asm-offsets.h> |
1ec2772e | 36 | #include <asm/diag.h> |
1e3cab2f HC |
37 | #include <asm/switch_to.h> |
38 | #include <asm/facility.h> | |
46b05d26 | 39 | #include <asm/ipl.h> |
2b67fc46 | 40 | #include <asm/setup.h> |
1da177e4 | 41 | #include <asm/irq.h> |
1da177e4 | 42 | #include <asm/tlbflush.h> |
27f6b416 | 43 | #include <asm/vtimer.h> |
411ed322 | 44 | #include <asm/lowcore.h> |
08d07968 | 45 | #include <asm/sclp.h> |
c742b31c | 46 | #include <asm/vdso.h> |
3ab121ab | 47 | #include <asm/debug.h> |
4857d4bb | 48 | #include <asm/os_info.h> |
a9ae32c3 | 49 | #include <asm/sigp.h> |
b5f87f15 | 50 | #include <asm/idle.h> |
a806170e | 51 | #include "entry.h" |
1da177e4 | 52 | |
8b646bd7 MS |
53 | enum { |
54 | ec_schedule = 0, | |
8b646bd7 MS |
55 | ec_call_function_single, |
56 | ec_stop_cpu, | |
57 | }; | |
08d07968 | 58 | |
8b646bd7 | 59 | enum { |
08d07968 HC |
60 | CPU_STATE_STANDBY, |
61 | CPU_STATE_CONFIGURED, | |
62 | }; | |
63 | ||
2f859d0d HC |
64 | static DEFINE_PER_CPU(struct cpu *, cpu_device); |
65 | ||
8b646bd7 | 66 | struct pcpu { |
8b646bd7 | 67 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
8b646bd7 | 68 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ |
2f859d0d HC |
69 | signed char state; /* physical cpu state */ |
70 | signed char polarization; /* physical polarization */ | |
8b646bd7 MS |
71 | u16 address; /* physical cpu address */ |
72 | }; | |
73 | ||
d08d9430 | 74 | static u8 boot_core_type; |
8b646bd7 MS |
75 | static struct pcpu pcpu_devices[NR_CPUS]; |
76 | ||
10ad34bc MS |
77 | unsigned int smp_cpu_mt_shift; |
78 | EXPORT_SYMBOL(smp_cpu_mt_shift); | |
79 | ||
80 | unsigned int smp_cpu_mtid; | |
81 | EXPORT_SYMBOL(smp_cpu_mtid); | |
82 | ||
83 | static unsigned int smp_max_threads __initdata = -1U; | |
84 | ||
85 | static int __init early_nosmt(char *s) | |
86 | { | |
87 | smp_max_threads = 1; | |
88 | return 0; | |
89 | } | |
90 | early_param("nosmt", early_nosmt); | |
91 | ||
92 | static int __init early_smt(char *s) | |
93 | { | |
94 | get_option(&s, &smp_max_threads); | |
95 | return 0; | |
96 | } | |
97 | early_param("smt", early_smt); | |
98 | ||
50ab9a9a HC |
99 | /* |
100 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
101 | * member of a pcpu data structure within the pcpu_devices arreay. | |
102 | */ | |
dbd70fb4 | 103 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 104 | |
8b646bd7 MS |
105 | /* |
106 | * Signal processor helper functions. | |
107 | */ | |
a62bc073 MH |
108 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm, |
109 | u32 *status) | |
5c0b912e | 110 | { |
8b646bd7 | 111 | int cc; |
5c0b912e | 112 | |
8b646bd7 | 113 | while (1) { |
c5e3acd6 | 114 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 115 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
116 | return cc; |
117 | cpu_relax(); | |
5c0b912e | 118 | } |
5c0b912e HC |
119 | } |
120 | ||
8b646bd7 | 121 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 122 | { |
8b646bd7 MS |
123 | int cc, retry; |
124 | ||
125 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 126 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 127 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
128 | break; |
129 | if (retry >= 3) | |
130 | udelay(10); | |
131 | } | |
132 | return cc; | |
133 | } | |
134 | ||
135 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
136 | { | |
41459d36 | 137 | u32 uninitialized_var(status); |
c5e3acd6 | 138 | |
a9ae32c3 | 139 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 140 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 141 | return 0; |
c5e3acd6 | 142 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
143 | } |
144 | ||
145 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 146 | { |
a9ae32c3 | 147 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 148 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 149 | return 1; |
524b24ad HC |
150 | /* Status stored condition code is equivalent to cpu not running. */ |
151 | return 0; | |
a93b8ec1 HC |
152 | } |
153 | ||
1943f53c | 154 | /* |
8b646bd7 | 155 | * Find struct pcpu by cpu address. |
1943f53c | 156 | */ |
10ad34bc | 157 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) |
1943f53c MH |
158 | { |
159 | int cpu; | |
160 | ||
8b646bd7 MS |
161 | for_each_cpu(cpu, mask) |
162 | if (pcpu_devices[cpu].address == address) | |
163 | return pcpu_devices + cpu; | |
164 | return NULL; | |
165 | } | |
166 | ||
167 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
168 | { | |
169 | int order; | |
170 | ||
dea24190 HC |
171 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
172 | return; | |
173 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
8b646bd7 MS |
174 | pcpu_sigp_retry(pcpu, order, 0); |
175 | } | |
176 | ||
2f859d0d HC |
177 | #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) |
178 | #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) | |
179 | ||
e2741f17 | 180 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 | 181 | { |
2f859d0d | 182 | unsigned long async_stack, panic_stack; |
8b646bd7 MS |
183 | struct _lowcore *lc; |
184 | ||
185 | if (pcpu != &pcpu_devices[0]) { | |
186 | pcpu->lowcore = (struct _lowcore *) | |
187 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
2f859d0d HC |
188 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); |
189 | panic_stack = __get_free_page(GFP_KERNEL); | |
190 | if (!pcpu->lowcore || !panic_stack || !async_stack) | |
8b646bd7 | 191 | goto out; |
2f859d0d HC |
192 | } else { |
193 | async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET; | |
194 | panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET; | |
1943f53c | 195 | } |
8b646bd7 MS |
196 | lc = pcpu->lowcore; |
197 | memcpy(lc, &S390_lowcore, 512); | |
198 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
2f859d0d HC |
199 | lc->async_stack = async_stack + ASYNC_FRAME_OFFSET; |
200 | lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET; | |
8b646bd7 | 201 | lc->cpu_nr = cpu; |
6c8cd5bb | 202 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
80703617 MS |
203 | if (MACHINE_HAS_VX) |
204 | lc->vector_save_area_addr = | |
205 | (unsigned long) &lc->vector_save_area; | |
8b646bd7 MS |
206 | if (vdso_alloc_per_cpu(lc)) |
207 | goto out; | |
8b646bd7 | 208 | lowcore_ptr[cpu] = lc; |
a9ae32c3 | 209 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
210 | return 0; |
211 | out: | |
212 | if (pcpu != &pcpu_devices[0]) { | |
2f859d0d HC |
213 | free_page(panic_stack); |
214 | free_pages(async_stack, ASYNC_ORDER); | |
8b646bd7 MS |
215 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); |
216 | } | |
217 | return -ENOMEM; | |
1943f53c MH |
218 | } |
219 | ||
9d0f46af HC |
220 | #ifdef CONFIG_HOTPLUG_CPU |
221 | ||
8b646bd7 | 222 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 223 | { |
a9ae32c3 | 224 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 | 225 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
8b646bd7 | 226 | vdso_free_per_cpu(pcpu->lowcore); |
2f859d0d HC |
227 | if (pcpu == &pcpu_devices[0]) |
228 | return; | |
229 | free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET); | |
230 | free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER); | |
231 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
8b646bd7 MS |
232 | } |
233 | ||
9d0f46af HC |
234 | #endif /* CONFIG_HOTPLUG_CPU */ |
235 | ||
8b646bd7 MS |
236 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
237 | { | |
238 | struct _lowcore *lc = pcpu->lowcore; | |
239 | ||
1b948d6c MS |
240 | if (MACHINE_HAS_TLB_LC) |
241 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
242 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); | |
8b646bd7 MS |
243 | atomic_inc(&init_mm.context.attach_count); |
244 | lc->cpu_nr = cpu; | |
6c8cd5bb | 245 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
8b646bd7 MS |
246 | lc->percpu_offset = __per_cpu_offset[cpu]; |
247 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
248 | lc->machine_flags = S390_lowcore.machine_flags; | |
8b646bd7 MS |
249 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; |
250 | __ctl_store(lc->cregs_save_area, 0, 15); | |
251 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
252 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
253 | MAX_FACILITY_BIT/8); | |
254 | } | |
255 | ||
256 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
257 | { | |
258 | struct _lowcore *lc = pcpu->lowcore; | |
259 | struct thread_info *ti = task_thread_info(tsk); | |
260 | ||
dc7ee00d MS |
261 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
262 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
263 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
264 | lc->current_task = (unsigned long) tsk; | |
e22cf8ca CB |
265 | lc->lpp = LPP_MAGIC; |
266 | lc->current_pid = tsk->pid; | |
8b646bd7 MS |
267 | lc->user_timer = ti->user_timer; |
268 | lc->system_timer = ti->system_timer; | |
269 | lc->steal_timer = 0; | |
270 | } | |
271 | ||
272 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
273 | { | |
274 | struct _lowcore *lc = pcpu->lowcore; | |
275 | ||
276 | lc->restart_stack = lc->kernel_stack; | |
277 | lc->restart_fn = (unsigned long) func; | |
278 | lc->restart_data = (unsigned long) data; | |
279 | lc->restart_source = -1UL; | |
a9ae32c3 | 280 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
281 | } |
282 | ||
283 | /* | |
284 | * Call function via PSW restart on pcpu and stop the current cpu. | |
285 | */ | |
286 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
287 | void *data, unsigned long stack) | |
288 | { | |
061da3df | 289 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 290 | unsigned long source_cpu = stap(); |
8b646bd7 | 291 | |
e258d719 | 292 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 293 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
294 | func(data); /* should not return */ |
295 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 296 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 297 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
298 | mem_assign_absolute(lc->restart_stack, stack); |
299 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
300 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
301 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 302 | asm volatile( |
eb546195 | 303 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 304 | " brc 2,0b # busy, try again\n" |
eb546195 | 305 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 306 | " brc 2,1b # busy, try again\n" |
fbe76568 | 307 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
308 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
309 | : "0", "1", "cc"); | |
8b646bd7 MS |
310 | for (;;) ; |
311 | } | |
312 | ||
10ad34bc MS |
313 | /* |
314 | * Enable additional logical cpus for multi-threading. | |
315 | */ | |
316 | static int pcpu_set_smt(unsigned int mtid) | |
317 | { | |
318 | register unsigned long reg1 asm ("1") = (unsigned long) mtid; | |
319 | int cc; | |
320 | ||
321 | if (smp_cpu_mtid == mtid) | |
322 | return 0; | |
323 | asm volatile( | |
324 | " sigp %1,0,%2 # sigp set multi-threading\n" | |
325 | " ipm %0\n" | |
326 | " srl %0,28\n" | |
327 | : "=d" (cc) : "d" (reg1), "K" (SIGP_SET_MULTI_THREADING) | |
328 | : "cc"); | |
329 | if (cc == 0) { | |
330 | smp_cpu_mtid = mtid; | |
331 | smp_cpu_mt_shift = 0; | |
332 | while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) | |
333 | smp_cpu_mt_shift++; | |
334 | pcpu_devices[0].address = stap(); | |
335 | } | |
336 | return cc; | |
337 | } | |
338 | ||
8b646bd7 MS |
339 | /* |
340 | * Call function on an online CPU. | |
341 | */ | |
342 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
343 | { | |
344 | struct pcpu *pcpu; | |
345 | ||
346 | /* Use the current cpu if it is online. */ | |
347 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
348 | if (!pcpu) | |
349 | /* Use the first online cpu. */ | |
350 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
351 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
352 | } | |
353 | ||
354 | /* | |
355 | * Call function on the ipl CPU. | |
356 | */ | |
357 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
358 | { | |
c6da39f2 | 359 | pcpu_delegate(&pcpu_devices[0], func, data, |
2f859d0d HC |
360 | pcpu_devices->lowcore->panic_stack - |
361 | PANIC_FRAME_OFFSET + PAGE_SIZE); | |
8b646bd7 MS |
362 | } |
363 | ||
364 | int smp_find_processor_id(u16 address) | |
365 | { | |
366 | int cpu; | |
367 | ||
368 | for_each_present_cpu(cpu) | |
369 | if (pcpu_devices[cpu].address == address) | |
370 | return cpu; | |
371 | return -1; | |
2c2df118 HC |
372 | } |
373 | ||
8b646bd7 | 374 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 375 | { |
8b646bd7 MS |
376 | return pcpu_running(pcpu_devices + cpu); |
377 | } | |
378 | ||
8b646bd7 | 379 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 380 | { |
1ec2772e | 381 | if (MACHINE_HAS_DIAG9C) { |
b5a6b71b | 382 | diag_stat_inc_norecursion(DIAG_STAT_X09C); |
8b646bd7 MS |
383 | asm volatile("diag %0,0,0x9c" |
384 | : : "d" (pcpu_devices[cpu].address)); | |
1ec2772e | 385 | } else if (MACHINE_HAS_DIAG44) { |
b5a6b71b | 386 | diag_stat_inc_norecursion(DIAG_STAT_X044); |
8b646bd7 | 387 | asm volatile("diag 0,0,0x44"); |
1ec2772e | 388 | } |
8b646bd7 MS |
389 | } |
390 | ||
391 | /* | |
392 | * Send cpus emergency shutdown signal. This gives the cpus the | |
393 | * opportunity to complete outstanding interrupts. | |
394 | */ | |
63df41d6 | 395 | static void smp_emergency_stop(cpumask_t *cpumask) |
8b646bd7 MS |
396 | { |
397 | u64 end; | |
398 | int cpu; | |
399 | ||
1aae0560 | 400 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
401 | for_each_cpu(cpu, cpumask) { |
402 | struct pcpu *pcpu = pcpu_devices + cpu; | |
403 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
404 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
405 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 406 | get_tod_clock() < end) |
8b646bd7 MS |
407 | cpu_relax(); |
408 | } | |
1aae0560 | 409 | while (get_tod_clock() < end) { |
8b646bd7 MS |
410 | for_each_cpu(cpu, cpumask) |
411 | if (pcpu_stopped(pcpu_devices + cpu)) | |
412 | cpumask_clear_cpu(cpu, cpumask); | |
413 | if (cpumask_empty(cpumask)) | |
414 | break; | |
85ac7ca5 | 415 | cpu_relax(); |
8b646bd7 | 416 | } |
85ac7ca5 MS |
417 | } |
418 | ||
8b646bd7 MS |
419 | /* |
420 | * Stop all cpus but the current one. | |
421 | */ | |
677d7623 | 422 | void smp_send_stop(void) |
1da177e4 | 423 | { |
85ac7ca5 MS |
424 | cpumask_t cpumask; |
425 | int cpu; | |
1da177e4 | 426 | |
677d7623 | 427 | /* Disable all interrupts/machine checks */ |
e258d719 | 428 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 429 | trace_hardirqs_off(); |
1da177e4 | 430 | |
3ab121ab | 431 | debug_set_critical(); |
85ac7ca5 MS |
432 | cpumask_copy(&cpumask, cpu_online_mask); |
433 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
434 | ||
8b646bd7 MS |
435 | if (oops_in_progress) |
436 | smp_emergency_stop(&cpumask); | |
1da177e4 | 437 | |
85ac7ca5 MS |
438 | /* stop all processors */ |
439 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 440 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 441 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 442 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
443 | cpu_relax(); |
444 | } | |
445 | } | |
446 | ||
1da177e4 LT |
447 | /* |
448 | * This is the main routine where commands issued by other | |
449 | * cpus are handled. | |
450 | */ | |
9acf73b7 | 451 | static void smp_handle_ext_call(void) |
1da177e4 | 452 | { |
39ce010d | 453 | unsigned long bits; |
1da177e4 | 454 | |
9acf73b7 HC |
455 | /* handle bit signal external calls */ |
456 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
457 | if (test_bit(ec_stop_cpu, &bits)) |
458 | smp_stop_cpu(); | |
184748cc PZ |
459 | if (test_bit(ec_schedule, &bits)) |
460 | scheduler_ipi(); | |
ca9fc75a HC |
461 | if (test_bit(ec_call_function_single, &bits)) |
462 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 463 | } |
85ac7ca5 | 464 | |
9acf73b7 HC |
465 | static void do_ext_call_interrupt(struct ext_code ext_code, |
466 | unsigned int param32, unsigned long param64) | |
467 | { | |
468 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
469 | smp_handle_ext_call(); | |
1da177e4 LT |
470 | } |
471 | ||
630cd046 | 472 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
473 | { |
474 | int cpu; | |
475 | ||
630cd046 | 476 | for_each_cpu(cpu, mask) |
b6ed49e0 | 477 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
478 | } |
479 | ||
480 | void arch_send_call_function_single_ipi(int cpu) | |
481 | { | |
8b646bd7 | 482 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
483 | } |
484 | ||
1da177e4 LT |
485 | /* |
486 | * this function sends a 'reschedule' IPI to another CPU. | |
487 | * it goes straight through and wastes no time serializing | |
488 | * anything. Worst case is that we lose a reschedule ... | |
489 | */ | |
490 | void smp_send_reschedule(int cpu) | |
491 | { | |
8b646bd7 | 492 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
493 | } |
494 | ||
495 | /* | |
496 | * parameter area for the set/clear control bit callbacks | |
497 | */ | |
94c12cc7 | 498 | struct ec_creg_mask_parms { |
8b646bd7 MS |
499 | unsigned long orval; |
500 | unsigned long andval; | |
501 | int cr; | |
94c12cc7 | 502 | }; |
1da177e4 LT |
503 | |
504 | /* | |
505 | * callback for setting/clearing control bits | |
506 | */ | |
39ce010d HC |
507 | static void smp_ctl_bit_callback(void *info) |
508 | { | |
94c12cc7 | 509 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 510 | unsigned long cregs[16]; |
39ce010d | 511 | |
94c12cc7 | 512 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 513 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 514 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
515 | } |
516 | ||
517 | /* | |
518 | * Set a bit in a control register of all cpus | |
519 | */ | |
94c12cc7 MS |
520 | void smp_ctl_set_bit(int cr, int bit) |
521 | { | |
8b646bd7 | 522 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 523 | |
15c8b6c1 | 524 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 525 | } |
39ce010d | 526 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
527 | |
528 | /* | |
529 | * Clear a bit in a control register of all cpus | |
530 | */ | |
94c12cc7 MS |
531 | void smp_ctl_clear_bit(int cr, int bit) |
532 | { | |
8b646bd7 | 533 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 534 | |
15c8b6c1 | 535 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 536 | } |
39ce010d | 537 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 538 | |
bf28a597 | 539 | #ifdef CONFIG_CRASH_DUMP |
411ed322 | 540 | |
e7f596de HC |
541 | static void __init __smp_store_cpu_state(struct save_area_ext *sa_ext, |
542 | u16 address, int is_boot_cpu) | |
411ed322 | 543 | { |
1592a8e4 | 544 | void *lc = (void *)(unsigned long) store_prefix(); |
a62bc073 | 545 | unsigned long vx_sa; |
8b646bd7 | 546 | |
10ad34bc MS |
547 | if (is_boot_cpu) { |
548 | /* Copy the registers of the boot CPU. */ | |
df9694c7 MS |
549 | copy_oldmem_kernel(&sa_ext->sa, (void *) SAVE_AREA_BASE, |
550 | sizeof(sa_ext->sa)); | |
a62bc073 MH |
551 | if (MACHINE_HAS_VX) |
552 | save_vx_regs_safe(sa_ext->vx_regs); | |
8b646bd7 MS |
553 | return; |
554 | } | |
8b646bd7 | 555 | /* Get the registers of a non-boot cpu. */ |
a9ae32c3 | 556 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
a62bc073 MH |
557 | memcpy_real(&sa_ext->sa, lc + SAVE_AREA_BASE, sizeof(sa_ext->sa)); |
558 | if (!MACHINE_HAS_VX) | |
559 | return; | |
560 | /* Get the VX registers */ | |
1592a8e4 | 561 | vx_sa = memblock_alloc(PAGE_SIZE, PAGE_SIZE); |
a62bc073 MH |
562 | if (!vx_sa) |
563 | panic("could not allocate memory for VX save area\n"); | |
564 | __pcpu_sigp_relax(address, SIGP_STORE_ADDITIONAL_STATUS, vx_sa, NULL); | |
565 | memcpy(sa_ext->vx_regs, (void *) vx_sa, sizeof(sa_ext->vx_regs)); | |
1592a8e4 | 566 | memblock_free(vx_sa, PAGE_SIZE); |
411ed322 MH |
567 | } |
568 | ||
1af135a1 HC |
569 | int smp_store_status(int cpu) |
570 | { | |
571 | unsigned long vx_sa; | |
572 | struct pcpu *pcpu; | |
573 | ||
574 | pcpu = pcpu_devices + cpu; | |
575 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, | |
576 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
577 | return -EIO; | |
578 | if (!MACHINE_HAS_VX) | |
579 | return 0; | |
580 | vx_sa = __pa(pcpu->lowcore->vector_save_area_addr); | |
581 | __pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, | |
582 | vx_sa, NULL); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | #endif /* CONFIG_CRASH_DUMP */ | |
587 | ||
10ad34bc MS |
588 | /* |
589 | * Collect CPU state of the previous, crashed system. | |
590 | * There are four cases: | |
591 | * 1) standard zfcp dump | |
592 | * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
593 | * The state for all CPUs except the boot CPU needs to be collected | |
594 | * with sigp stop-and-store-status. The boot CPU state is located in | |
595 | * the absolute lowcore of the memory stored in the HSA. The zcore code | |
596 | * will allocate the save area and copy the boot CPU state from the HSA. | |
597 | * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory) | |
598 | * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
599 | * The state for all CPUs except the boot CPU needs to be collected | |
600 | * with sigp stop-and-store-status. The firmware or the boot-loader | |
601 | * stored the registers of the boot CPU in the absolute lowcore in the | |
602 | * memory of the old system. | |
603 | * 3) kdump and the old kernel did not store the CPU state, | |
604 | * or stand-alone kdump for DASD | |
605 | * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() | |
606 | * The state for all CPUs except the boot CPU needs to be collected | |
607 | * with sigp stop-and-store-status. The kexec code or the boot-loader | |
608 | * stored the registers of the boot CPU in the memory of the old system. | |
609 | * 4) kdump and the old kernel stored the CPU state | |
610 | * condition: OLDMEM_BASE != NULL && is_kdump_kernel() | |
8a07dd02 MS |
611 | * This case does not exist for s390 anymore, setup_arch explicitly |
612 | * deactivates the elfcorehdr= kernel parameter | |
10ad34bc | 613 | */ |
1592a8e4 | 614 | void __init smp_save_dump_cpus(void) |
10ad34bc | 615 | { |
1af135a1 | 616 | #ifdef CONFIG_CRASH_DUMP |
1592a8e4 MH |
617 | int addr, cpu, boot_cpu_addr, max_cpu_addr; |
618 | struct save_area_ext *sa_ext; | |
619 | bool is_boot_cpu; | |
10ad34bc | 620 | |
10ad34bc MS |
621 | if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP)) |
622 | /* No previous system present, normal boot. */ | |
623 | return; | |
624 | /* Set multi-threading state to the previous system. */ | |
37c5f6c8 | 625 | pcpu_set_smt(sclp.mtid_prev); |
1592a8e4 MH |
626 | max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; |
627 | for (cpu = 0, addr = 0; addr <= max_cpu_addr; addr++) { | |
628 | if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0, NULL) == | |
629 | SIGP_CC_NOT_OPERATIONAL) | |
10ad34bc | 630 | continue; |
1592a8e4 MH |
631 | cpu += 1; |
632 | } | |
633 | dump_save_areas.areas = (void *)memblock_alloc(sizeof(void *) * cpu, 8); | |
634 | dump_save_areas.count = cpu; | |
635 | boot_cpu_addr = stap(); | |
636 | for (cpu = 0, addr = 0; addr <= max_cpu_addr; addr++) { | |
637 | if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0, NULL) == | |
638 | SIGP_CC_NOT_OPERATIONAL) | |
639 | continue; | |
640 | sa_ext = (void *) memblock_alloc(sizeof(*sa_ext), 8); | |
641 | dump_save_areas.areas[cpu] = sa_ext; | |
642 | if (!sa_ext) | |
643 | panic("could not allocate memory for save area\n"); | |
644 | is_boot_cpu = (addr == boot_cpu_addr); | |
645 | cpu += 1; | |
646 | if (is_boot_cpu && !OLDMEM_BASE) | |
647 | /* Skip boot CPU for standard zfcp dump. */ | |
648 | continue; | |
649 | /* Get state for this CPU. */ | |
650 | __smp_store_cpu_state(sa_ext, addr, is_boot_cpu); | |
10ad34bc | 651 | } |
1592a8e4 MH |
652 | diag308_reset(); |
653 | pcpu_set_smt(0); | |
bf28a597 | 654 | #endif /* CONFIG_CRASH_DUMP */ |
1af135a1 | 655 | } |
08d07968 | 656 | |
50ab9a9a HC |
657 | void smp_cpu_set_polarization(int cpu, int val) |
658 | { | |
659 | pcpu_devices[cpu].polarization = val; | |
660 | } | |
661 | ||
662 | int smp_cpu_get_polarization(int cpu) | |
663 | { | |
664 | return pcpu_devices[cpu].polarization; | |
665 | } | |
666 | ||
d08d9430 | 667 | static struct sclp_core_info *smp_get_core_info(void) |
08d07968 | 668 | { |
8b646bd7 | 669 | static int use_sigp_detection; |
d08d9430 | 670 | struct sclp_core_info *info; |
8b646bd7 MS |
671 | int address; |
672 | ||
673 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
d08d9430 | 674 | if (info && (use_sigp_detection || sclp_get_core_info(info))) { |
8b646bd7 | 675 | use_sigp_detection = 1; |
e7086eb1 | 676 | for (address = 0; |
d08d9430 | 677 | address < (SCLP_MAX_CORES << smp_cpu_mt_shift); |
10ad34bc | 678 | address += (1U << smp_cpu_mt_shift)) { |
a9ae32c3 HC |
679 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
680 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 | 681 | continue; |
d08d9430 | 682 | info->core[info->configured].core_id = |
10ad34bc | 683 | address >> smp_cpu_mt_shift; |
8b646bd7 MS |
684 | info->configured++; |
685 | } | |
686 | info->combined = info->configured; | |
08d07968 | 687 | } |
8b646bd7 | 688 | return info; |
08d07968 HC |
689 | } |
690 | ||
e2741f17 | 691 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 692 | |
d08d9430 | 693 | static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add) |
08d07968 | 694 | { |
8b646bd7 | 695 | struct pcpu *pcpu; |
08d07968 | 696 | cpumask_t avail; |
10ad34bc MS |
697 | int cpu, nr, i, j; |
698 | u16 address; | |
08d07968 | 699 | |
8b646bd7 | 700 | nr = 0; |
0f1959f5 | 701 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
702 | cpu = cpumask_first(&avail); |
703 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
d08d9430 | 704 | if (sclp.has_core_type && info->core[i].type != boot_core_type) |
8b646bd7 | 705 | continue; |
d08d9430 | 706 | address = info->core[i].core_id << smp_cpu_mt_shift; |
10ad34bc MS |
707 | for (j = 0; j <= smp_cpu_mtid; j++) { |
708 | if (pcpu_find_address(cpu_present_mask, address + j)) | |
709 | continue; | |
710 | pcpu = pcpu_devices + cpu; | |
711 | pcpu->address = address + j; | |
712 | pcpu->state = | |
713 | (cpu >= info->configured*(smp_cpu_mtid + 1)) ? | |
714 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; | |
715 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
716 | set_cpu_present(cpu, true); | |
717 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
718 | set_cpu_present(cpu, false); | |
719 | else | |
720 | nr++; | |
721 | cpu = cpumask_next(cpu, &avail); | |
722 | if (cpu >= nr_cpu_ids) | |
723 | break; | |
724 | } | |
8b646bd7 MS |
725 | } |
726 | return nr; | |
1da177e4 LT |
727 | } |
728 | ||
48483b32 HC |
729 | static void __init smp_detect_cpus(void) |
730 | { | |
10ad34bc | 731 | unsigned int cpu, mtid, c_cpus, s_cpus; |
d08d9430 | 732 | struct sclp_core_info *info; |
10ad34bc | 733 | u16 address; |
48483b32 | 734 | |
10ad34bc | 735 | /* Get CPU information */ |
d08d9430 | 736 | info = smp_get_core_info(); |
48483b32 HC |
737 | if (!info) |
738 | panic("smp_detect_cpus failed to allocate memory\n"); | |
10ad34bc MS |
739 | |
740 | /* Find boot CPU type */ | |
d08d9430 | 741 | if (sclp.has_core_type) { |
10ad34bc MS |
742 | address = stap(); |
743 | for (cpu = 0; cpu < info->combined; cpu++) | |
d08d9430 | 744 | if (info->core[cpu].core_id == address) { |
10ad34bc | 745 | /* The boot cpu dictates the cpu type. */ |
d08d9430 | 746 | boot_core_type = info->core[cpu].type; |
10ad34bc MS |
747 | break; |
748 | } | |
749 | if (cpu >= info->combined) | |
750 | panic("Could not find boot CPU type"); | |
48483b32 | 751 | } |
10ad34bc | 752 | |
10ad34bc | 753 | /* Set multi-threading state for the current system */ |
d08d9430 | 754 | mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; |
10ad34bc MS |
755 | mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; |
756 | pcpu_set_smt(mtid); | |
757 | ||
758 | /* Print number of CPUs */ | |
8b646bd7 | 759 | c_cpus = s_cpus = 0; |
48483b32 | 760 | for (cpu = 0; cpu < info->combined; cpu++) { |
d08d9430 MS |
761 | if (sclp.has_core_type && |
762 | info->core[cpu].type != boot_core_type) | |
48483b32 | 763 | continue; |
10ad34bc MS |
764 | if (cpu < info->configured) |
765 | c_cpus += smp_cpu_mtid + 1; | |
766 | else | |
767 | s_cpus += smp_cpu_mtid + 1; | |
48483b32 | 768 | } |
395d31d4 | 769 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
10ad34bc MS |
770 | |
771 | /* Add CPUs present at boot */ | |
9d40d2e3 | 772 | get_online_cpus(); |
8b646bd7 | 773 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 774 | put_online_cpus(); |
8b646bd7 | 775 | kfree(info); |
48483b32 HC |
776 | } |
777 | ||
1da177e4 | 778 | /* |
39ce010d | 779 | * Activate a secondary processor. |
1da177e4 | 780 | */ |
e2741f17 | 781 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 782 | { |
1aae0560 | 783 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
784 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
785 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
786 | S390_lowcore.restart_data = 0; | |
787 | S390_lowcore.restart_source = -1UL; | |
788 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
789 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 790 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 791 | cpu_init(); |
5bfb5d69 | 792 | preempt_disable(); |
39ce010d | 793 | init_cpu_timer(); |
b5f87f15 | 794 | vtime_init(); |
29b08d2b | 795 | pfault_init(); |
e545a614 | 796 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 797 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 798 | inc_irq_stat(CPU_RST); |
1da177e4 | 799 | local_irq_enable(); |
52c00659 | 800 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
801 | } |
802 | ||
1da177e4 | 803 | /* Upping and downing of CPUs */ |
e2741f17 | 804 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 805 | { |
8b646bd7 | 806 | struct pcpu *pcpu; |
10ad34bc | 807 | int base, i, rc; |
1da177e4 | 808 | |
8b646bd7 MS |
809 | pcpu = pcpu_devices + cpu; |
810 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 811 | return -EIO; |
10ad34bc MS |
812 | base = cpu - (cpu % (smp_cpu_mtid + 1)); |
813 | for (i = 0; i <= smp_cpu_mtid; i++) { | |
814 | if (base + i < nr_cpu_ids) | |
815 | if (cpu_online(base + i)) | |
816 | break; | |
817 | } | |
818 | /* | |
819 | * If this is the first CPU of the core to get online | |
820 | * do an initial CPU reset. | |
821 | */ | |
822 | if (i > smp_cpu_mtid && | |
823 | pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) != | |
a9ae32c3 | 824 | SIGP_CC_ORDER_CODE_ACCEPTED) |
08d07968 | 825 | return -EIO; |
e80e7813 | 826 | |
8b646bd7 MS |
827 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
828 | if (rc) | |
829 | return rc; | |
830 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 831 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 832 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
a1307bba HC |
833 | /* Wait until cpu puts itself in the online & active maps */ |
834 | while (!cpu_online(cpu) || !cpu_active(cpu)) | |
1da177e4 LT |
835 | cpu_relax(); |
836 | return 0; | |
837 | } | |
838 | ||
d80512f8 | 839 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 840 | |
d80512f8 HC |
841 | static int __init _setup_possible_cpus(char *s) |
842 | { | |
843 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
844 | return 0; |
845 | } | |
d80512f8 | 846 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 847 | |
48483b32 HC |
848 | #ifdef CONFIG_HOTPLUG_CPU |
849 | ||
39ce010d | 850 | int __cpu_disable(void) |
1da177e4 | 851 | { |
8b646bd7 | 852 | unsigned long cregs[16]; |
1da177e4 | 853 | |
9acf73b7 HC |
854 | /* Handle possible pending IPIs */ |
855 | smp_handle_ext_call(); | |
8b646bd7 MS |
856 | set_cpu_online(smp_processor_id(), false); |
857 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 858 | pfault_fini(); |
8b646bd7 MS |
859 | /* Disable interrupt sources via control register. */ |
860 | __ctl_store(cregs, 0, 15); | |
861 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
862 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
863 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
864 | __ctl_load(cregs, 0, 15); | |
fe0f4976 | 865 | clear_cpu_flag(CIF_NOHZ_DELAY); |
1da177e4 LT |
866 | return 0; |
867 | } | |
868 | ||
39ce010d | 869 | void __cpu_die(unsigned int cpu) |
1da177e4 | 870 | { |
8b646bd7 MS |
871 | struct pcpu *pcpu; |
872 | ||
1da177e4 | 873 | /* Wait until target cpu is down */ |
8b646bd7 MS |
874 | pcpu = pcpu_devices + cpu; |
875 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 876 | cpu_relax(); |
8b646bd7 | 877 | pcpu_free_lowcore(pcpu); |
050eef36 | 878 | atomic_dec(&init_mm.context.attach_count); |
1b948d6c MS |
879 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
880 | if (MACHINE_HAS_TLB_LC) | |
881 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); | |
1da177e4 LT |
882 | } |
883 | ||
b456d94a | 884 | void __noreturn cpu_die(void) |
1da177e4 LT |
885 | { |
886 | idle_task_exit(); | |
a9ae32c3 | 887 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 888 | for (;;) ; |
1da177e4 LT |
889 | } |
890 | ||
255acee7 HC |
891 | #endif /* CONFIG_HOTPLUG_CPU */ |
892 | ||
d80512f8 HC |
893 | void __init smp_fill_possible_mask(void) |
894 | { | |
9747bc47 | 895 | unsigned int possible, sclp_max, cpu; |
d80512f8 | 896 | |
3a9f3fe6 DH |
897 | sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; |
898 | sclp_max = min(smp_max_threads, sclp_max); | |
d08d9430 | 899 | sclp_max = sclp.max_cores * sclp_max ?: nr_cpu_ids; |
cf813db0 | 900 | possible = setup_possible_cpus ?: nr_cpu_ids; |
9747bc47 | 901 | possible = min(possible, sclp_max); |
d80512f8 HC |
902 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
903 | set_cpu_possible(cpu, true); | |
904 | } | |
905 | ||
1da177e4 LT |
906 | void __init smp_prepare_cpus(unsigned int max_cpus) |
907 | { | |
39ce010d | 908 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 909 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 910 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 911 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 912 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 913 | panic("Couldn't request external interrupt 0x1202"); |
8b646bd7 | 914 | smp_detect_cpus(); |
1da177e4 LT |
915 | } |
916 | ||
ea1f4eec | 917 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 918 | { |
8b646bd7 MS |
919 | struct pcpu *pcpu = pcpu_devices; |
920 | ||
8b646bd7 | 921 | pcpu->state = CPU_STATE_CONFIGURED; |
10ad34bc | 922 | pcpu->address = stap(); |
8b646bd7 | 923 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); |
1da177e4 | 924 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 925 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
926 | set_cpu_present(0, true); |
927 | set_cpu_online(0, true); | |
1da177e4 LT |
928 | } |
929 | ||
ea1f4eec | 930 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 931 | { |
1da177e4 LT |
932 | } |
933 | ||
02beaccc HC |
934 | void __init smp_setup_processor_id(void) |
935 | { | |
936 | S390_lowcore.cpu_nr = 0; | |
6c8cd5bb | 937 | S390_lowcore.spinlock_lockval = arch_spin_lockval(0); |
02beaccc HC |
938 | } |
939 | ||
1da177e4 LT |
940 | /* |
941 | * the frequency of the profiling timer can be changed | |
942 | * by writing a multiplier value into /proc/profile. | |
943 | * | |
944 | * usually you want to run this on all CPUs ;) | |
945 | */ | |
946 | int setup_profiling_timer(unsigned int multiplier) | |
947 | { | |
39ce010d | 948 | return 0; |
1da177e4 LT |
949 | } |
950 | ||
08d07968 | 951 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 952 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 953 | struct device_attribute *attr, char *buf) |
08d07968 HC |
954 | { |
955 | ssize_t count; | |
956 | ||
957 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 958 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
959 | mutex_unlock(&smp_cpu_state_mutex); |
960 | return count; | |
961 | } | |
962 | ||
8a25a2fd | 963 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
964 | struct device_attribute *attr, |
965 | const char *buf, size_t count) | |
08d07968 | 966 | { |
8b646bd7 | 967 | struct pcpu *pcpu; |
10ad34bc | 968 | int cpu, val, rc, i; |
08d07968 HC |
969 | char delim; |
970 | ||
971 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
972 | return -EINVAL; | |
973 | if (val != 0 && val != 1) | |
974 | return -EINVAL; | |
9d40d2e3 | 975 | get_online_cpus(); |
0b18d318 | 976 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 977 | rc = -EBUSY; |
2c2df118 | 978 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 979 | cpu = dev->id; |
10ad34bc MS |
980 | cpu -= cpu % (smp_cpu_mtid + 1); |
981 | if (cpu == 0) | |
08d07968 | 982 | goto out; |
10ad34bc MS |
983 | for (i = 0; i <= smp_cpu_mtid; i++) |
984 | if (cpu_online(cpu + i)) | |
985 | goto out; | |
8b646bd7 | 986 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
987 | rc = 0; |
988 | switch (val) { | |
989 | case 0: | |
8b646bd7 MS |
990 | if (pcpu->state != CPU_STATE_CONFIGURED) |
991 | break; | |
d08d9430 | 992 | rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
993 | if (rc) |
994 | break; | |
10ad34bc MS |
995 | for (i = 0; i <= smp_cpu_mtid; i++) { |
996 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
997 | continue; | |
998 | pcpu[i].state = CPU_STATE_STANDBY; | |
999 | smp_cpu_set_polarization(cpu + i, | |
1000 | POLARIZATION_UNKNOWN); | |
1001 | } | |
8b646bd7 | 1002 | topology_expect_change(); |
08d07968 HC |
1003 | break; |
1004 | case 1: | |
8b646bd7 MS |
1005 | if (pcpu->state != CPU_STATE_STANDBY) |
1006 | break; | |
d08d9430 | 1007 | rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
1008 | if (rc) |
1009 | break; | |
10ad34bc MS |
1010 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1011 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1012 | continue; | |
1013 | pcpu[i].state = CPU_STATE_CONFIGURED; | |
1014 | smp_cpu_set_polarization(cpu + i, | |
1015 | POLARIZATION_UNKNOWN); | |
1016 | } | |
8b646bd7 | 1017 | topology_expect_change(); |
08d07968 HC |
1018 | break; |
1019 | default: | |
1020 | break; | |
1021 | } | |
1022 | out: | |
08d07968 | 1023 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1024 | put_online_cpus(); |
08d07968 HC |
1025 | return rc ? rc : count; |
1026 | } | |
8a25a2fd | 1027 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
1028 | #endif /* CONFIG_HOTPLUG_CPU */ |
1029 | ||
8a25a2fd KS |
1030 | static ssize_t show_cpu_address(struct device *dev, |
1031 | struct device_attribute *attr, char *buf) | |
08d07968 | 1032 | { |
8b646bd7 | 1033 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 1034 | } |
8a25a2fd | 1035 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 1036 | |
08d07968 HC |
1037 | static struct attribute *cpu_common_attrs[] = { |
1038 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 1039 | &dev_attr_configure.attr, |
08d07968 | 1040 | #endif |
8a25a2fd | 1041 | &dev_attr_address.attr, |
08d07968 HC |
1042 | NULL, |
1043 | }; | |
1044 | ||
1045 | static struct attribute_group cpu_common_attr_group = { | |
1046 | .attrs = cpu_common_attrs, | |
1047 | }; | |
1da177e4 | 1048 | |
08d07968 | 1049 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1050 | &dev_attr_idle_count.attr, |
1051 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1052 | NULL, |
1053 | }; | |
1054 | ||
08d07968 HC |
1055 | static struct attribute_group cpu_online_attr_group = { |
1056 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1057 | }; |
1058 | ||
e2741f17 PG |
1059 | static int smp_cpu_notify(struct notifier_block *self, unsigned long action, |
1060 | void *hcpu) | |
2fc2d1e9 HC |
1061 | { |
1062 | unsigned int cpu = (unsigned int)(long)hcpu; | |
2f859d0d | 1063 | struct device *s = &per_cpu(cpu_device, cpu)->dev; |
d882ba69 | 1064 | int err = 0; |
2fc2d1e9 | 1065 | |
1c725922 | 1066 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 1067 | case CPU_ONLINE: |
d882ba69 | 1068 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1069 | break; |
1070 | case CPU_DEAD: | |
08d07968 | 1071 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1072 | break; |
1073 | } | |
d882ba69 | 1074 | return notifier_from_errno(err); |
2fc2d1e9 HC |
1075 | } |
1076 | ||
e2741f17 | 1077 | static int smp_add_present_cpu(int cpu) |
08d07968 | 1078 | { |
96619fc1 HC |
1079 | struct device *s; |
1080 | struct cpu *c; | |
08d07968 HC |
1081 | int rc; |
1082 | ||
96619fc1 HC |
1083 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
1084 | if (!c) | |
1085 | return -ENOMEM; | |
2f859d0d | 1086 | per_cpu(cpu_device, cpu) = c; |
96619fc1 | 1087 | s = &c->dev; |
08d07968 HC |
1088 | c->hotpluggable = 1; |
1089 | rc = register_cpu(c, cpu); | |
1090 | if (rc) | |
1091 | goto out; | |
1092 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1093 | if (rc) | |
1094 | goto out_cpu; | |
83a24e32 HC |
1095 | if (cpu_online(cpu)) { |
1096 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1097 | if (rc) | |
1098 | goto out_online; | |
1099 | } | |
1100 | rc = topology_cpu_init(c); | |
1101 | if (rc) | |
1102 | goto out_topology; | |
1103 | return 0; | |
1104 | ||
1105 | out_topology: | |
1106 | if (cpu_online(cpu)) | |
1107 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1108 | out_online: | |
08d07968 HC |
1109 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1110 | out_cpu: | |
1111 | #ifdef CONFIG_HOTPLUG_CPU | |
1112 | unregister_cpu(c); | |
1113 | #endif | |
1114 | out: | |
1115 | return rc; | |
1116 | } | |
1117 | ||
1118 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1119 | |
67060d9c | 1120 | int __ref smp_rescan_cpus(void) |
08d07968 | 1121 | { |
d08d9430 | 1122 | struct sclp_core_info *info; |
8b646bd7 | 1123 | int nr; |
08d07968 | 1124 | |
d08d9430 | 1125 | info = smp_get_core_info(); |
8b646bd7 MS |
1126 | if (!info) |
1127 | return -ENOMEM; | |
9d40d2e3 | 1128 | get_online_cpus(); |
0b18d318 | 1129 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1130 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1131 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1132 | put_online_cpus(); |
8b646bd7 MS |
1133 | kfree(info); |
1134 | if (nr) | |
c10fde0d | 1135 | topology_schedule_update(); |
8b646bd7 | 1136 | return 0; |
1e489518 HC |
1137 | } |
1138 | ||
8a25a2fd KS |
1139 | static ssize_t __ref rescan_store(struct device *dev, |
1140 | struct device_attribute *attr, | |
c9be0a36 | 1141 | const char *buf, |
1e489518 HC |
1142 | size_t count) |
1143 | { | |
1144 | int rc; | |
1145 | ||
1146 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1147 | return rc ? rc : count; |
1148 | } | |
8a25a2fd | 1149 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1150 | #endif /* CONFIG_HOTPLUG_CPU */ |
1151 | ||
83a24e32 | 1152 | static int __init s390_smp_init(void) |
1da177e4 | 1153 | { |
f4edbcd5 | 1154 | int cpu, rc = 0; |
2fc2d1e9 | 1155 | |
08d07968 | 1156 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1157 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1158 | if (rc) |
1159 | return rc; | |
1160 | #endif | |
f4edbcd5 | 1161 | cpu_notifier_register_begin(); |
08d07968 HC |
1162 | for_each_present_cpu(cpu) { |
1163 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1164 | if (rc) |
f4edbcd5 | 1165 | goto out; |
1da177e4 | 1166 | } |
f4edbcd5 SB |
1167 | |
1168 | __hotcpu_notifier(smp_cpu_notify, 0); | |
1169 | ||
1170 | out: | |
1171 | cpu_notifier_register_done(); | |
1172 | return rc; | |
1da177e4 | 1173 | } |
83a24e32 | 1174 | subsys_initcall(s390_smp_init); |