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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
8b646bd7 | 3 | * SMP related functions |
1da177e4 | 4 | * |
a53c8fab | 5 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
6 | * Author(s): Denis Joseph Barrow, |
7 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
8 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 9 | * |
39ce010d | 10 | * based on other smp stuff by |
1da177e4 LT |
11 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
12 | * (c) 1998 Ingo Molnar | |
13 | * | |
8b646bd7 MS |
14 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
15 | * the translation of logical to physical cpu ids. All new code that | |
16 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
17 | */ |
18 | ||
395d31d4 MS |
19 | #define KMSG_COMPONENT "cpu" |
20 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
21 | ||
f230886b | 22 | #include <linux/workqueue.h> |
af51160e | 23 | #include <linux/bootmem.h> |
3994a52b | 24 | #include <linux/export.h> |
1da177e4 | 25 | #include <linux/init.h> |
1da177e4 | 26 | #include <linux/mm.h> |
4e950f6f | 27 | #include <linux/err.h> |
1da177e4 LT |
28 | #include <linux/spinlock.h> |
29 | #include <linux/kernel_stat.h> | |
9cf8edb7 | 30 | #include <linux/kmemleak.h> |
1da177e4 | 31 | #include <linux/delay.h> |
1da177e4 | 32 | #include <linux/interrupt.h> |
3324e60a | 33 | #include <linux/irqflags.h> |
1da177e4 | 34 | #include <linux/cpu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
ef8bd77f | 36 | #include <linux/sched/hotplug.h> |
68db0cf1 | 37 | #include <linux/sched/task_stack.h> |
60a0c68d | 38 | #include <linux/crash_dump.h> |
1592a8e4 | 39 | #include <linux/memblock.h> |
00a8f886 | 40 | #include <linux/kprobes.h> |
cbb870c8 | 41 | #include <asm/asm-offsets.h> |
1ec2772e | 42 | #include <asm/diag.h> |
1e3cab2f HC |
43 | #include <asm/switch_to.h> |
44 | #include <asm/facility.h> | |
46b05d26 | 45 | #include <asm/ipl.h> |
2b67fc46 | 46 | #include <asm/setup.h> |
1da177e4 | 47 | #include <asm/irq.h> |
1da177e4 | 48 | #include <asm/tlbflush.h> |
27f6b416 | 49 | #include <asm/vtimer.h> |
411ed322 | 50 | #include <asm/lowcore.h> |
08d07968 | 51 | #include <asm/sclp.h> |
c742b31c | 52 | #include <asm/vdso.h> |
3ab121ab | 53 | #include <asm/debug.h> |
4857d4bb | 54 | #include <asm/os_info.h> |
a9ae32c3 | 55 | #include <asm/sigp.h> |
b5f87f15 | 56 | #include <asm/idle.h> |
916cda1a | 57 | #include <asm/nmi.h> |
38389ec8 | 58 | #include <asm/topology.h> |
a806170e | 59 | #include "entry.h" |
1da177e4 | 60 | |
8b646bd7 MS |
61 | enum { |
62 | ec_schedule = 0, | |
8b646bd7 MS |
63 | ec_call_function_single, |
64 | ec_stop_cpu, | |
65 | }; | |
08d07968 | 66 | |
8b646bd7 | 67 | enum { |
08d07968 HC |
68 | CPU_STATE_STANDBY, |
69 | CPU_STATE_CONFIGURED, | |
70 | }; | |
71 | ||
2f859d0d HC |
72 | static DEFINE_PER_CPU(struct cpu *, cpu_device); |
73 | ||
8b646bd7 | 74 | struct pcpu { |
c667aeac | 75 | struct lowcore *lowcore; /* lowcore page(s) for the cpu */ |
8b646bd7 | 76 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ |
3dbc78d3 | 77 | unsigned long ec_clk; /* sigp timestamp for ec_xxx */ |
2f859d0d HC |
78 | signed char state; /* physical cpu state */ |
79 | signed char polarization; /* physical polarization */ | |
8b646bd7 MS |
80 | u16 address; /* physical cpu address */ |
81 | }; | |
82 | ||
d08d9430 | 83 | static u8 boot_core_type; |
8b646bd7 MS |
84 | static struct pcpu pcpu_devices[NR_CPUS]; |
85 | ||
10ad34bc MS |
86 | unsigned int smp_cpu_mt_shift; |
87 | EXPORT_SYMBOL(smp_cpu_mt_shift); | |
88 | ||
89 | unsigned int smp_cpu_mtid; | |
90 | EXPORT_SYMBOL(smp_cpu_mtid); | |
91 | ||
1a36a39e MS |
92 | #ifdef CONFIG_CRASH_DUMP |
93 | __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; | |
94 | #endif | |
95 | ||
10ad34bc MS |
96 | static unsigned int smp_max_threads __initdata = -1U; |
97 | ||
98 | static int __init early_nosmt(char *s) | |
99 | { | |
100 | smp_max_threads = 1; | |
101 | return 0; | |
102 | } | |
103 | early_param("nosmt", early_nosmt); | |
104 | ||
105 | static int __init early_smt(char *s) | |
106 | { | |
107 | get_option(&s, &smp_max_threads); | |
108 | return 0; | |
109 | } | |
110 | early_param("smt", early_smt); | |
111 | ||
50ab9a9a HC |
112 | /* |
113 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
114 | * member of a pcpu data structure within the pcpu_devices arreay. | |
115 | */ | |
dbd70fb4 | 116 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 117 | |
8b646bd7 MS |
118 | /* |
119 | * Signal processor helper functions. | |
120 | */ | |
1a36a39e | 121 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) |
5c0b912e | 122 | { |
8b646bd7 | 123 | int cc; |
5c0b912e | 124 | |
8b646bd7 | 125 | while (1) { |
c5e3acd6 | 126 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 127 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
128 | return cc; |
129 | cpu_relax(); | |
5c0b912e | 130 | } |
5c0b912e HC |
131 | } |
132 | ||
8b646bd7 | 133 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 134 | { |
8b646bd7 MS |
135 | int cc, retry; |
136 | ||
137 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 138 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 139 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
140 | break; |
141 | if (retry >= 3) | |
142 | udelay(10); | |
143 | } | |
144 | return cc; | |
145 | } | |
146 | ||
147 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
148 | { | |
41459d36 | 149 | u32 uninitialized_var(status); |
c5e3acd6 | 150 | |
a9ae32c3 | 151 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 152 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 153 | return 0; |
c5e3acd6 | 154 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
155 | } |
156 | ||
157 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 158 | { |
a9ae32c3 | 159 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 160 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 161 | return 1; |
524b24ad HC |
162 | /* Status stored condition code is equivalent to cpu not running. */ |
163 | return 0; | |
a93b8ec1 HC |
164 | } |
165 | ||
1943f53c | 166 | /* |
8b646bd7 | 167 | * Find struct pcpu by cpu address. |
1943f53c | 168 | */ |
10ad34bc | 169 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) |
1943f53c MH |
170 | { |
171 | int cpu; | |
172 | ||
8b646bd7 MS |
173 | for_each_cpu(cpu, mask) |
174 | if (pcpu_devices[cpu].address == address) | |
175 | return pcpu_devices + cpu; | |
176 | return NULL; | |
177 | } | |
178 | ||
179 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
180 | { | |
181 | int order; | |
182 | ||
dea24190 HC |
183 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
184 | return; | |
185 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
3dbc78d3 | 186 | pcpu->ec_clk = get_tod_clock_fast(); |
8b646bd7 MS |
187 | pcpu_sigp_retry(pcpu, order, 0); |
188 | } | |
189 | ||
2f859d0d HC |
190 | #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) |
191 | #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) | |
192 | ||
e2741f17 | 193 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 | 194 | { |
2f859d0d | 195 | unsigned long async_stack, panic_stack; |
c667aeac | 196 | struct lowcore *lc; |
8b646bd7 MS |
197 | |
198 | if (pcpu != &pcpu_devices[0]) { | |
c667aeac | 199 | pcpu->lowcore = (struct lowcore *) |
8b646bd7 | 200 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
2f859d0d HC |
201 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); |
202 | panic_stack = __get_free_page(GFP_KERNEL); | |
203 | if (!pcpu->lowcore || !panic_stack || !async_stack) | |
8b646bd7 | 204 | goto out; |
2f859d0d HC |
205 | } else { |
206 | async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET; | |
207 | panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET; | |
1943f53c | 208 | } |
8b646bd7 MS |
209 | lc = pcpu->lowcore; |
210 | memcpy(lc, &S390_lowcore, 512); | |
211 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
2f859d0d HC |
212 | lc->async_stack = async_stack + ASYNC_FRAME_OFFSET; |
213 | lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET; | |
8b646bd7 | 214 | lc->cpu_nr = cpu; |
6c8cd5bb | 215 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
b96f7d88 | 216 | lc->spinlock_index = 0; |
00d54225 | 217 | lc->br_r1_trampoline = 0x07f1; /* br %r1 */ |
6c81511c | 218 | if (nmi_alloc_per_cpu(lc)) |
8b646bd7 | 219 | goto out; |
6c81511c MS |
220 | if (vdso_alloc_per_cpu(lc)) |
221 | goto out_mcesa; | |
8b646bd7 | 222 | lowcore_ptr[cpu] = lc; |
a9ae32c3 | 223 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 | 224 | return 0; |
6c81511c MS |
225 | |
226 | out_mcesa: | |
227 | nmi_free_per_cpu(lc); | |
8b646bd7 MS |
228 | out: |
229 | if (pcpu != &pcpu_devices[0]) { | |
2f859d0d HC |
230 | free_page(panic_stack); |
231 | free_pages(async_stack, ASYNC_ORDER); | |
8b646bd7 MS |
232 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); |
233 | } | |
234 | return -ENOMEM; | |
1943f53c MH |
235 | } |
236 | ||
9d0f46af HC |
237 | #ifdef CONFIG_HOTPLUG_CPU |
238 | ||
8b646bd7 | 239 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 240 | { |
a9ae32c3 | 241 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 | 242 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
8b646bd7 | 243 | vdso_free_per_cpu(pcpu->lowcore); |
6c81511c | 244 | nmi_free_per_cpu(pcpu->lowcore); |
2f859d0d HC |
245 | if (pcpu == &pcpu_devices[0]) |
246 | return; | |
247 | free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET); | |
248 | free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER); | |
249 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
8b646bd7 MS |
250 | } |
251 | ||
9d0f46af HC |
252 | #endif /* CONFIG_HOTPLUG_CPU */ |
253 | ||
8b646bd7 MS |
254 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
255 | { | |
c667aeac | 256 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 257 | |
64f31d58 | 258 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1b948d6c | 259 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); |
8b646bd7 | 260 | lc->cpu_nr = cpu; |
6c8cd5bb | 261 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
b96f7d88 | 262 | lc->spinlock_index = 0; |
8b646bd7 MS |
263 | lc->percpu_offset = __per_cpu_offset[cpu]; |
264 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
e12c9721 | 265 | lc->user_asce = S390_lowcore.kernel_asce; |
8b646bd7 | 266 | lc->machine_flags = S390_lowcore.machine_flags; |
8b646bd7 MS |
267 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; |
268 | __ctl_store(lc->cregs_save_area, 0, 15); | |
e12c9721 HC |
269 | lc->cregs_save_area[1] = lc->kernel_asce; |
270 | lc->cregs_save_area[7] = lc->vdso_asce; | |
8b646bd7 MS |
271 | save_access_regs((unsigned int *) lc->access_regs_save_area); |
272 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
db2b5991 MS |
273 | sizeof(lc->stfle_fac_list)); |
274 | memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list, | |
275 | sizeof(lc->alt_stfle_fac_list)); | |
b96f7d88 | 276 | arch_spin_lock_setup(cpu); |
8b646bd7 MS |
277 | } |
278 | ||
279 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
280 | { | |
c667aeac | 281 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 282 | |
dc7ee00d MS |
283 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
284 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 | 285 | lc->current_task = (unsigned long) tsk; |
e22cf8ca CB |
286 | lc->lpp = LPP_MAGIC; |
287 | lc->current_pid = tsk->pid; | |
90c53e65 | 288 | lc->user_timer = tsk->thread.user_timer; |
b7662eef | 289 | lc->guest_timer = tsk->thread.guest_timer; |
90c53e65 | 290 | lc->system_timer = tsk->thread.system_timer; |
b7662eef CB |
291 | lc->hardirq_timer = tsk->thread.hardirq_timer; |
292 | lc->softirq_timer = tsk->thread.softirq_timer; | |
8b646bd7 MS |
293 | lc->steal_timer = 0; |
294 | } | |
295 | ||
296 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
297 | { | |
c667aeac | 298 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 MS |
299 | |
300 | lc->restart_stack = lc->kernel_stack; | |
301 | lc->restart_fn = (unsigned long) func; | |
302 | lc->restart_data = (unsigned long) data; | |
303 | lc->restart_source = -1UL; | |
a9ae32c3 | 304 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
305 | } |
306 | ||
307 | /* | |
308 | * Call function via PSW restart on pcpu and stop the current cpu. | |
309 | */ | |
310 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
311 | void *data, unsigned long stack) | |
312 | { | |
c667aeac | 313 | struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 314 | unsigned long source_cpu = stap(); |
8b646bd7 | 315 | |
e258d719 | 316 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 317 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
318 | func(data); /* should not return */ |
319 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 320 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 321 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
322 | mem_assign_absolute(lc->restart_stack, stack); |
323 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
324 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
325 | mem_assign_absolute(lc->restart_source, source_cpu); | |
92fa2703 | 326 | __bpon(); |
8b646bd7 | 327 | asm volatile( |
eb546195 | 328 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 329 | " brc 2,0b # busy, try again\n" |
eb546195 | 330 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 331 | " brc 2,1b # busy, try again\n" |
fbe76568 | 332 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
333 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
334 | : "0", "1", "cc"); | |
8b646bd7 MS |
335 | for (;;) ; |
336 | } | |
337 | ||
10ad34bc MS |
338 | /* |
339 | * Enable additional logical cpus for multi-threading. | |
340 | */ | |
341 | static int pcpu_set_smt(unsigned int mtid) | |
342 | { | |
10ad34bc MS |
343 | int cc; |
344 | ||
345 | if (smp_cpu_mtid == mtid) | |
346 | return 0; | |
80a60f6e | 347 | cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); |
10ad34bc MS |
348 | if (cc == 0) { |
349 | smp_cpu_mtid = mtid; | |
350 | smp_cpu_mt_shift = 0; | |
351 | while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) | |
352 | smp_cpu_mt_shift++; | |
353 | pcpu_devices[0].address = stap(); | |
354 | } | |
355 | return cc; | |
356 | } | |
357 | ||
8b646bd7 MS |
358 | /* |
359 | * Call function on an online CPU. | |
360 | */ | |
361 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
362 | { | |
363 | struct pcpu *pcpu; | |
364 | ||
365 | /* Use the current cpu if it is online. */ | |
366 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
367 | if (!pcpu) | |
368 | /* Use the first online cpu. */ | |
369 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
370 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
371 | } | |
372 | ||
373 | /* | |
374 | * Call function on the ipl CPU. | |
375 | */ | |
376 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
377 | { | |
65985839 DH |
378 | struct lowcore *lc = pcpu_devices->lowcore; |
379 | ||
380 | if (pcpu_devices[0].address == stap()) | |
381 | lc = &S390_lowcore; | |
382 | ||
c6da39f2 | 383 | pcpu_delegate(&pcpu_devices[0], func, data, |
65985839 | 384 | lc->panic_stack - PANIC_FRAME_OFFSET + PAGE_SIZE); |
8b646bd7 MS |
385 | } |
386 | ||
387 | int smp_find_processor_id(u16 address) | |
388 | { | |
389 | int cpu; | |
390 | ||
391 | for_each_present_cpu(cpu) | |
392 | if (pcpu_devices[cpu].address == address) | |
393 | return cpu; | |
394 | return -1; | |
2c2df118 HC |
395 | } |
396 | ||
760928c0 | 397 | bool arch_vcpu_is_preempted(int cpu) |
85ac7ca5 | 398 | { |
760928c0 CB |
399 | if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) |
400 | return false; | |
401 | if (pcpu_running(pcpu_devices + cpu)) | |
402 | return false; | |
403 | return true; | |
8b646bd7 | 404 | } |
760928c0 | 405 | EXPORT_SYMBOL(arch_vcpu_is_preempted); |
8b646bd7 | 406 | |
8b646bd7 | 407 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 408 | { |
1ec2772e | 409 | if (MACHINE_HAS_DIAG9C) { |
b5a6b71b | 410 | diag_stat_inc_norecursion(DIAG_STAT_X09C); |
8b646bd7 MS |
411 | asm volatile("diag %0,0,0x9c" |
412 | : : "d" (pcpu_devices[cpu].address)); | |
1ec2772e | 413 | } else if (MACHINE_HAS_DIAG44) { |
b5a6b71b | 414 | diag_stat_inc_norecursion(DIAG_STAT_X044); |
8b646bd7 | 415 | asm volatile("diag 0,0,0x44"); |
1ec2772e | 416 | } |
8b646bd7 MS |
417 | } |
418 | ||
419 | /* | |
420 | * Send cpus emergency shutdown signal. This gives the cpus the | |
421 | * opportunity to complete outstanding interrupts. | |
422 | */ | |
00a8f886 | 423 | void notrace smp_emergency_stop(void) |
8b646bd7 | 424 | { |
00a8f886 | 425 | cpumask_t cpumask; |
8b646bd7 MS |
426 | u64 end; |
427 | int cpu; | |
428 | ||
00a8f886 MS |
429 | cpumask_copy(&cpumask, cpu_online_mask); |
430 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
431 | ||
1aae0560 | 432 | end = get_tod_clock() + (1000000UL << 12); |
00a8f886 | 433 | for_each_cpu(cpu, &cpumask) { |
8b646bd7 MS |
434 | struct pcpu *pcpu = pcpu_devices + cpu; |
435 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
436 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
437 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 438 | get_tod_clock() < end) |
8b646bd7 MS |
439 | cpu_relax(); |
440 | } | |
1aae0560 | 441 | while (get_tod_clock() < end) { |
00a8f886 | 442 | for_each_cpu(cpu, &cpumask) |
8b646bd7 | 443 | if (pcpu_stopped(pcpu_devices + cpu)) |
00a8f886 MS |
444 | cpumask_clear_cpu(cpu, &cpumask); |
445 | if (cpumask_empty(&cpumask)) | |
8b646bd7 | 446 | break; |
85ac7ca5 | 447 | cpu_relax(); |
8b646bd7 | 448 | } |
85ac7ca5 | 449 | } |
00a8f886 | 450 | NOKPROBE_SYMBOL(smp_emergency_stop); |
85ac7ca5 | 451 | |
8b646bd7 MS |
452 | /* |
453 | * Stop all cpus but the current one. | |
454 | */ | |
677d7623 | 455 | void smp_send_stop(void) |
1da177e4 | 456 | { |
85ac7ca5 | 457 | int cpu; |
1da177e4 | 458 | |
677d7623 | 459 | /* Disable all interrupts/machine checks */ |
e258d719 | 460 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 461 | trace_hardirqs_off(); |
1da177e4 | 462 | |
3ab121ab | 463 | debug_set_critical(); |
85ac7ca5 | 464 | |
8b646bd7 | 465 | if (oops_in_progress) |
00a8f886 | 466 | smp_emergency_stop(); |
1da177e4 | 467 | |
85ac7ca5 | 468 | /* stop all processors */ |
00a8f886 MS |
469 | for_each_online_cpu(cpu) { |
470 | if (cpu == smp_processor_id()) | |
471 | continue; | |
472 | pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0); | |
473 | while (!pcpu_stopped(pcpu_devices + cpu)) | |
c6b5b847 HC |
474 | cpu_relax(); |
475 | } | |
476 | } | |
477 | ||
1da177e4 LT |
478 | /* |
479 | * This is the main routine where commands issued by other | |
480 | * cpus are handled. | |
481 | */ | |
9acf73b7 | 482 | static void smp_handle_ext_call(void) |
1da177e4 | 483 | { |
39ce010d | 484 | unsigned long bits; |
1da177e4 | 485 | |
9acf73b7 HC |
486 | /* handle bit signal external calls */ |
487 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
488 | if (test_bit(ec_stop_cpu, &bits)) |
489 | smp_stop_cpu(); | |
184748cc PZ |
490 | if (test_bit(ec_schedule, &bits)) |
491 | scheduler_ipi(); | |
ca9fc75a HC |
492 | if (test_bit(ec_call_function_single, &bits)) |
493 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 494 | } |
85ac7ca5 | 495 | |
9acf73b7 HC |
496 | static void do_ext_call_interrupt(struct ext_code ext_code, |
497 | unsigned int param32, unsigned long param64) | |
498 | { | |
499 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
500 | smp_handle_ext_call(); | |
1da177e4 LT |
501 | } |
502 | ||
630cd046 | 503 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
504 | { |
505 | int cpu; | |
506 | ||
630cd046 | 507 | for_each_cpu(cpu, mask) |
b6ed49e0 | 508 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
509 | } |
510 | ||
511 | void arch_send_call_function_single_ipi(int cpu) | |
512 | { | |
8b646bd7 | 513 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
514 | } |
515 | ||
1da177e4 LT |
516 | /* |
517 | * this function sends a 'reschedule' IPI to another CPU. | |
518 | * it goes straight through and wastes no time serializing | |
519 | * anything. Worst case is that we lose a reschedule ... | |
520 | */ | |
521 | void smp_send_reschedule(int cpu) | |
522 | { | |
8b646bd7 | 523 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
524 | } |
525 | ||
526 | /* | |
527 | * parameter area for the set/clear control bit callbacks | |
528 | */ | |
94c12cc7 | 529 | struct ec_creg_mask_parms { |
8b646bd7 MS |
530 | unsigned long orval; |
531 | unsigned long andval; | |
532 | int cr; | |
94c12cc7 | 533 | }; |
1da177e4 LT |
534 | |
535 | /* | |
536 | * callback for setting/clearing control bits | |
537 | */ | |
39ce010d HC |
538 | static void smp_ctl_bit_callback(void *info) |
539 | { | |
94c12cc7 | 540 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 541 | unsigned long cregs[16]; |
39ce010d | 542 | |
94c12cc7 | 543 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 544 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 545 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
546 | } |
547 | ||
548 | /* | |
549 | * Set a bit in a control register of all cpus | |
550 | */ | |
94c12cc7 MS |
551 | void smp_ctl_set_bit(int cr, int bit) |
552 | { | |
8b646bd7 | 553 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 554 | |
15c8b6c1 | 555 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 556 | } |
39ce010d | 557 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
558 | |
559 | /* | |
560 | * Clear a bit in a control register of all cpus | |
561 | */ | |
94c12cc7 MS |
562 | void smp_ctl_clear_bit(int cr, int bit) |
563 | { | |
8b646bd7 | 564 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 565 | |
15c8b6c1 | 566 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 567 | } |
39ce010d | 568 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 569 | |
bf28a597 | 570 | #ifdef CONFIG_CRASH_DUMP |
411ed322 | 571 | |
1af135a1 HC |
572 | int smp_store_status(int cpu) |
573 | { | |
1a36a39e MS |
574 | struct pcpu *pcpu = pcpu_devices + cpu; |
575 | unsigned long pa; | |
1af135a1 | 576 | |
1a36a39e MS |
577 | pa = __pa(&pcpu->lowcore->floating_pt_save_area); |
578 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, | |
579 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
1af135a1 | 580 | return -EIO; |
916cda1a | 581 | if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) |
1af135a1 | 582 | return 0; |
916cda1a MS |
583 | pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK); |
584 | if (MACHINE_HAS_GS) | |
585 | pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK; | |
1a36a39e MS |
586 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, |
587 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
588 | return -EIO; | |
1af135a1 HC |
589 | return 0; |
590 | } | |
591 | ||
10ad34bc MS |
592 | /* |
593 | * Collect CPU state of the previous, crashed system. | |
594 | * There are four cases: | |
595 | * 1) standard zfcp dump | |
596 | * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
597 | * The state for all CPUs except the boot CPU needs to be collected | |
598 | * with sigp stop-and-store-status. The boot CPU state is located in | |
599 | * the absolute lowcore of the memory stored in the HSA. The zcore code | |
1a36a39e | 600 | * will copy the boot CPU state from the HSA. |
10ad34bc MS |
601 | * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory) |
602 | * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
603 | * The state for all CPUs except the boot CPU needs to be collected | |
604 | * with sigp stop-and-store-status. The firmware or the boot-loader | |
605 | * stored the registers of the boot CPU in the absolute lowcore in the | |
606 | * memory of the old system. | |
607 | * 3) kdump and the old kernel did not store the CPU state, | |
608 | * or stand-alone kdump for DASD | |
609 | * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() | |
610 | * The state for all CPUs except the boot CPU needs to be collected | |
611 | * with sigp stop-and-store-status. The kexec code or the boot-loader | |
612 | * stored the registers of the boot CPU in the memory of the old system. | |
613 | * 4) kdump and the old kernel stored the CPU state | |
614 | * condition: OLDMEM_BASE != NULL && is_kdump_kernel() | |
8a07dd02 MS |
615 | * This case does not exist for s390 anymore, setup_arch explicitly |
616 | * deactivates the elfcorehdr= kernel parameter | |
10ad34bc | 617 | */ |
1a2c5840 | 618 | static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, |
1a36a39e MS |
619 | bool is_boot_cpu, unsigned long page) |
620 | { | |
621 | __vector128 *vxrs = (__vector128 *) page; | |
622 | ||
623 | if (is_boot_cpu) | |
624 | vxrs = boot_cpu_vector_save_area; | |
625 | else | |
626 | __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); | |
1a2c5840 | 627 | save_area_add_vxrs(sa, vxrs); |
1a36a39e MS |
628 | } |
629 | ||
1a2c5840 | 630 | static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, |
1a36a39e MS |
631 | bool is_boot_cpu, unsigned long page) |
632 | { | |
633 | void *regs = (void *) page; | |
634 | ||
635 | if (is_boot_cpu) | |
636 | copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); | |
637 | else | |
638 | __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); | |
1a2c5840 | 639 | save_area_add_regs(sa, regs); |
1a36a39e MS |
640 | } |
641 | ||
1592a8e4 | 642 | void __init smp_save_dump_cpus(void) |
10ad34bc | 643 | { |
1a2c5840 MS |
644 | int addr, boot_cpu_addr, max_cpu_addr; |
645 | struct save_area *sa; | |
1a36a39e | 646 | unsigned long page; |
1592a8e4 | 647 | bool is_boot_cpu; |
10ad34bc | 648 | |
10ad34bc MS |
649 | if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP)) |
650 | /* No previous system present, normal boot. */ | |
651 | return; | |
1a36a39e MS |
652 | /* Allocate a page as dumping area for the store status sigps */ |
653 | page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31); | |
10ad34bc | 654 | /* Set multi-threading state to the previous system. */ |
37c5f6c8 | 655 | pcpu_set_smt(sclp.mtid_prev); |
1592a8e4 | 656 | boot_cpu_addr = stap(); |
1a2c5840 MS |
657 | max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; |
658 | for (addr = 0; addr <= max_cpu_addr; addr++) { | |
1a36a39e | 659 | if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == |
1592a8e4 MH |
660 | SIGP_CC_NOT_OPERATIONAL) |
661 | continue; | |
1592a8e4 | 662 | is_boot_cpu = (addr == boot_cpu_addr); |
1a2c5840 MS |
663 | /* Allocate save area */ |
664 | sa = save_area_alloc(is_boot_cpu); | |
665 | if (!sa) | |
666 | panic("could not allocate memory for save area\n"); | |
1a36a39e MS |
667 | if (MACHINE_HAS_VX) |
668 | /* Get the vector registers */ | |
1a2c5840 | 669 | smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page); |
1a36a39e MS |
670 | /* |
671 | * For a zfcp dump OLDMEM_BASE == NULL and the registers | |
672 | * of the boot CPU are stored in the HSA. To retrieve | |
673 | * these registers an SCLP request is required which is | |
674 | * done by drivers/s390/char/zcore.c:init_cpu_info() | |
675 | */ | |
676 | if (!is_boot_cpu || OLDMEM_BASE) | |
677 | /* Get the CPU registers */ | |
1a2c5840 | 678 | smp_save_cpu_regs(sa, addr, is_boot_cpu, page); |
10ad34bc | 679 | } |
1a36a39e | 680 | memblock_free(page, PAGE_SIZE); |
1592a8e4 MH |
681 | diag308_reset(); |
682 | pcpu_set_smt(0); | |
1af135a1 | 683 | } |
1a36a39e | 684 | #endif /* CONFIG_CRASH_DUMP */ |
08d07968 | 685 | |
50ab9a9a HC |
686 | void smp_cpu_set_polarization(int cpu, int val) |
687 | { | |
688 | pcpu_devices[cpu].polarization = val; | |
689 | } | |
690 | ||
691 | int smp_cpu_get_polarization(int cpu) | |
692 | { | |
693 | return pcpu_devices[cpu].polarization; | |
694 | } | |
695 | ||
af51160e | 696 | static void __ref smp_get_core_info(struct sclp_core_info *info, int early) |
08d07968 | 697 | { |
8b646bd7 | 698 | static int use_sigp_detection; |
8b646bd7 MS |
699 | int address; |
700 | ||
af51160e | 701 | if (use_sigp_detection || sclp_get_core_info(info, early)) { |
8b646bd7 | 702 | use_sigp_detection = 1; |
e7086eb1 | 703 | for (address = 0; |
d08d9430 | 704 | address < (SCLP_MAX_CORES << smp_cpu_mt_shift); |
10ad34bc | 705 | address += (1U << smp_cpu_mt_shift)) { |
1a36a39e | 706 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == |
a9ae32c3 | 707 | SIGP_CC_NOT_OPERATIONAL) |
8b646bd7 | 708 | continue; |
d08d9430 | 709 | info->core[info->configured].core_id = |
10ad34bc | 710 | address >> smp_cpu_mt_shift; |
8b646bd7 MS |
711 | info->configured++; |
712 | } | |
713 | info->combined = info->configured; | |
08d07968 | 714 | } |
08d07968 HC |
715 | } |
716 | ||
e2741f17 | 717 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 718 | |
0c996cd9 HC |
719 | static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, |
720 | bool configured, bool early) | |
08d07968 | 721 | { |
8b646bd7 | 722 | struct pcpu *pcpu; |
0c996cd9 | 723 | int cpu, nr, i; |
10ad34bc | 724 | u16 address; |
08d07968 | 725 | |
8b646bd7 | 726 | nr = 0; |
0c996cd9 HC |
727 | if (sclp.has_core_type && core->type != boot_core_type) |
728 | return nr; | |
729 | cpu = cpumask_first(avail); | |
730 | address = core->core_id << smp_cpu_mt_shift; | |
731 | for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) { | |
732 | if (pcpu_find_address(cpu_present_mask, address + i)) | |
8b646bd7 | 733 | continue; |
0c996cd9 HC |
734 | pcpu = pcpu_devices + cpu; |
735 | pcpu->address = address + i; | |
736 | if (configured) | |
737 | pcpu->state = CPU_STATE_CONFIGURED; | |
738 | else | |
739 | pcpu->state = CPU_STATE_STANDBY; | |
740 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
741 | set_cpu_present(cpu, true); | |
742 | if (!early && smp_add_present_cpu(cpu) != 0) | |
743 | set_cpu_present(cpu, false); | |
744 | else | |
745 | nr++; | |
746 | cpumask_clear_cpu(cpu, avail); | |
747 | cpu = cpumask_next(cpu, avail); | |
748 | } | |
749 | return nr; | |
750 | } | |
751 | ||
752 | static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) | |
753 | { | |
754 | struct sclp_core_entry *core; | |
755 | cpumask_t avail; | |
756 | bool configured; | |
757 | u16 core_id; | |
758 | int nr, i; | |
759 | ||
760 | nr = 0; | |
761 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); | |
762 | /* | |
763 | * Add IPL core first (which got logical CPU number 0) to make sure | |
764 | * that all SMT threads get subsequent logical CPU numbers. | |
765 | */ | |
766 | if (early) { | |
767 | core_id = pcpu_devices[0].address >> smp_cpu_mt_shift; | |
768 | for (i = 0; i < info->configured; i++) { | |
769 | core = &info->core[i]; | |
770 | if (core->core_id == core_id) { | |
771 | nr += smp_add_core(core, &avail, true, early); | |
10ad34bc | 772 | break; |
0c996cd9 | 773 | } |
10ad34bc | 774 | } |
8b646bd7 | 775 | } |
0c996cd9 HC |
776 | for (i = 0; i < info->combined; i++) { |
777 | configured = i < info->configured; | |
778 | nr += smp_add_core(&info->core[i], &avail, configured, early); | |
779 | } | |
8b646bd7 | 780 | return nr; |
1da177e4 LT |
781 | } |
782 | ||
af51160e | 783 | void __init smp_detect_cpus(void) |
48483b32 | 784 | { |
10ad34bc | 785 | unsigned int cpu, mtid, c_cpus, s_cpus; |
d08d9430 | 786 | struct sclp_core_info *info; |
10ad34bc | 787 | u16 address; |
48483b32 | 788 | |
10ad34bc | 789 | /* Get CPU information */ |
af51160e HC |
790 | info = memblock_virt_alloc(sizeof(*info), 8); |
791 | smp_get_core_info(info, 1); | |
10ad34bc | 792 | /* Find boot CPU type */ |
d08d9430 | 793 | if (sclp.has_core_type) { |
10ad34bc MS |
794 | address = stap(); |
795 | for (cpu = 0; cpu < info->combined; cpu++) | |
d08d9430 | 796 | if (info->core[cpu].core_id == address) { |
10ad34bc | 797 | /* The boot cpu dictates the cpu type. */ |
d08d9430 | 798 | boot_core_type = info->core[cpu].type; |
10ad34bc MS |
799 | break; |
800 | } | |
801 | if (cpu >= info->combined) | |
802 | panic("Could not find boot CPU type"); | |
48483b32 | 803 | } |
10ad34bc | 804 | |
10ad34bc | 805 | /* Set multi-threading state for the current system */ |
d08d9430 | 806 | mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; |
10ad34bc MS |
807 | mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; |
808 | pcpu_set_smt(mtid); | |
809 | ||
810 | /* Print number of CPUs */ | |
8b646bd7 | 811 | c_cpus = s_cpus = 0; |
48483b32 | 812 | for (cpu = 0; cpu < info->combined; cpu++) { |
d08d9430 MS |
813 | if (sclp.has_core_type && |
814 | info->core[cpu].type != boot_core_type) | |
48483b32 | 815 | continue; |
10ad34bc MS |
816 | if (cpu < info->configured) |
817 | c_cpus += smp_cpu_mtid + 1; | |
818 | else | |
819 | s_cpus += smp_cpu_mtid + 1; | |
48483b32 | 820 | } |
395d31d4 | 821 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
10ad34bc MS |
822 | |
823 | /* Add CPUs present at boot */ | |
9d40d2e3 | 824 | get_online_cpus(); |
0c996cd9 | 825 | __smp_rescan_cpus(info, true); |
9d40d2e3 | 826 | put_online_cpus(); |
af51160e | 827 | memblock_free_early((unsigned long)info, sizeof(*info)); |
48483b32 HC |
828 | } |
829 | ||
1da177e4 | 830 | /* |
39ce010d | 831 | * Activate a secondary processor. |
1da177e4 | 832 | */ |
e2741f17 | 833 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 834 | { |
1887aa07 MS |
835 | int cpu = smp_processor_id(); |
836 | ||
1aae0560 | 837 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
838 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
839 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
840 | S390_lowcore.restart_data = 0; | |
841 | S390_lowcore.restart_source = -1UL; | |
842 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
843 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 844 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
e12c9721 HC |
845 | set_cpu_flag(CIF_ASCE_PRIMARY); |
846 | set_cpu_flag(CIF_ASCE_SECONDARY); | |
39ce010d | 847 | cpu_init(); |
5bfb5d69 | 848 | preempt_disable(); |
39ce010d | 849 | init_cpu_timer(); |
b5f87f15 | 850 | vtime_init(); |
29b08d2b | 851 | pfault_init(); |
1887aa07 MS |
852 | notify_cpu_starting(cpu); |
853 | if (topology_cpu_dedicated(cpu)) | |
854 | set_cpu_flag(CIF_DEDICATED_CPU); | |
855 | else | |
856 | clear_cpu_flag(CIF_DEDICATED_CPU); | |
857 | set_cpu_online(cpu, true); | |
93f3b2ee | 858 | inc_irq_stat(CPU_RST); |
1da177e4 | 859 | local_irq_enable(); |
fc6d73d6 | 860 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
861 | } |
862 | ||
1da177e4 | 863 | /* Upping and downing of CPUs */ |
e2741f17 | 864 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 865 | { |
8b646bd7 | 866 | struct pcpu *pcpu; |
10ad34bc | 867 | int base, i, rc; |
1da177e4 | 868 | |
8b646bd7 MS |
869 | pcpu = pcpu_devices + cpu; |
870 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 871 | return -EIO; |
5423145f | 872 | base = smp_get_base_cpu(cpu); |
10ad34bc MS |
873 | for (i = 0; i <= smp_cpu_mtid; i++) { |
874 | if (base + i < nr_cpu_ids) | |
875 | if (cpu_online(base + i)) | |
876 | break; | |
877 | } | |
878 | /* | |
879 | * If this is the first CPU of the core to get online | |
880 | * do an initial CPU reset. | |
881 | */ | |
882 | if (i > smp_cpu_mtid && | |
883 | pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) != | |
a9ae32c3 | 884 | SIGP_CC_ORDER_CODE_ACCEPTED) |
08d07968 | 885 | return -EIO; |
e80e7813 | 886 | |
8b646bd7 MS |
887 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
888 | if (rc) | |
889 | return rc; | |
890 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 891 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 892 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
a1307bba | 893 | /* Wait until cpu puts itself in the online & active maps */ |
e9d867a6 | 894 | while (!cpu_online(cpu)) |
1da177e4 LT |
895 | cpu_relax(); |
896 | return 0; | |
897 | } | |
898 | ||
d80512f8 | 899 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 900 | |
d80512f8 HC |
901 | static int __init _setup_possible_cpus(char *s) |
902 | { | |
903 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
904 | return 0; |
905 | } | |
d80512f8 | 906 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 907 | |
48483b32 HC |
908 | #ifdef CONFIG_HOTPLUG_CPU |
909 | ||
39ce010d | 910 | int __cpu_disable(void) |
1da177e4 | 911 | { |
8b646bd7 | 912 | unsigned long cregs[16]; |
1da177e4 | 913 | |
9acf73b7 HC |
914 | /* Handle possible pending IPIs */ |
915 | smp_handle_ext_call(); | |
8b646bd7 MS |
916 | set_cpu_online(smp_processor_id(), false); |
917 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 918 | pfault_fini(); |
8b646bd7 MS |
919 | /* Disable interrupt sources via control register. */ |
920 | __ctl_store(cregs, 0, 15); | |
921 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
922 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
923 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
924 | __ctl_load(cregs, 0, 15); | |
fe0f4976 | 925 | clear_cpu_flag(CIF_NOHZ_DELAY); |
1da177e4 LT |
926 | return 0; |
927 | } | |
928 | ||
39ce010d | 929 | void __cpu_die(unsigned int cpu) |
1da177e4 | 930 | { |
8b646bd7 MS |
931 | struct pcpu *pcpu; |
932 | ||
1da177e4 | 933 | /* Wait until target cpu is down */ |
8b646bd7 MS |
934 | pcpu = pcpu_devices + cpu; |
935 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 936 | cpu_relax(); |
8b646bd7 | 937 | pcpu_free_lowcore(pcpu); |
1b948d6c | 938 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
64f31d58 | 939 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1da177e4 LT |
940 | } |
941 | ||
b456d94a | 942 | void __noreturn cpu_die(void) |
1da177e4 LT |
943 | { |
944 | idle_task_exit(); | |
92fa2703 | 945 | __bpon(); |
a9ae32c3 | 946 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 947 | for (;;) ; |
1da177e4 LT |
948 | } |
949 | ||
255acee7 HC |
950 | #endif /* CONFIG_HOTPLUG_CPU */ |
951 | ||
d80512f8 HC |
952 | void __init smp_fill_possible_mask(void) |
953 | { | |
9747bc47 | 954 | unsigned int possible, sclp_max, cpu; |
d80512f8 | 955 | |
3a9f3fe6 DH |
956 | sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; |
957 | sclp_max = min(smp_max_threads, sclp_max); | |
61282aff | 958 | sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; |
cf813db0 | 959 | possible = setup_possible_cpus ?: nr_cpu_ids; |
9747bc47 | 960 | possible = min(possible, sclp_max); |
d80512f8 HC |
961 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
962 | set_cpu_possible(cpu, true); | |
963 | } | |
964 | ||
1da177e4 LT |
965 | void __init smp_prepare_cpus(unsigned int max_cpus) |
966 | { | |
39ce010d | 967 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 968 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 969 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 970 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 971 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 972 | panic("Couldn't request external interrupt 0x1202"); |
1da177e4 LT |
973 | } |
974 | ||
ea1f4eec | 975 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 976 | { |
8b646bd7 MS |
977 | struct pcpu *pcpu = pcpu_devices; |
978 | ||
0861b5a7 | 979 | WARN_ON(!cpu_present(0) || !cpu_online(0)); |
8b646bd7 | 980 | pcpu->state = CPU_STATE_CONFIGURED; |
c667aeac | 981 | pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix(); |
1da177e4 | 982 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 983 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
1da177e4 LT |
984 | } |
985 | ||
ea1f4eec | 986 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 987 | { |
1da177e4 LT |
988 | } |
989 | ||
02beaccc HC |
990 | void __init smp_setup_processor_id(void) |
991 | { | |
0861b5a7 | 992 | pcpu_devices[0].address = stap(); |
02beaccc | 993 | S390_lowcore.cpu_nr = 0; |
6c8cd5bb | 994 | S390_lowcore.spinlock_lockval = arch_spin_lockval(0); |
b96f7d88 | 995 | S390_lowcore.spinlock_index = 0; |
02beaccc HC |
996 | } |
997 | ||
1da177e4 LT |
998 | /* |
999 | * the frequency of the profiling timer can be changed | |
1000 | * by writing a multiplier value into /proc/profile. | |
1001 | * | |
1002 | * usually you want to run this on all CPUs ;) | |
1003 | */ | |
1004 | int setup_profiling_timer(unsigned int multiplier) | |
1005 | { | |
39ce010d | 1006 | return 0; |
1da177e4 LT |
1007 | } |
1008 | ||
08d07968 | 1009 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1010 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 1011 | struct device_attribute *attr, char *buf) |
08d07968 HC |
1012 | { |
1013 | ssize_t count; | |
1014 | ||
1015 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 1016 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
1017 | mutex_unlock(&smp_cpu_state_mutex); |
1018 | return count; | |
1019 | } | |
1020 | ||
8a25a2fd | 1021 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
1022 | struct device_attribute *attr, |
1023 | const char *buf, size_t count) | |
08d07968 | 1024 | { |
8b646bd7 | 1025 | struct pcpu *pcpu; |
10ad34bc | 1026 | int cpu, val, rc, i; |
08d07968 HC |
1027 | char delim; |
1028 | ||
1029 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
1030 | return -EINVAL; | |
1031 | if (val != 0 && val != 1) | |
1032 | return -EINVAL; | |
9d40d2e3 | 1033 | get_online_cpus(); |
0b18d318 | 1034 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 1035 | rc = -EBUSY; |
2c2df118 | 1036 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 1037 | cpu = dev->id; |
5423145f | 1038 | cpu = smp_get_base_cpu(cpu); |
10ad34bc | 1039 | if (cpu == 0) |
08d07968 | 1040 | goto out; |
10ad34bc MS |
1041 | for (i = 0; i <= smp_cpu_mtid; i++) |
1042 | if (cpu_online(cpu + i)) | |
1043 | goto out; | |
8b646bd7 | 1044 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
1045 | rc = 0; |
1046 | switch (val) { | |
1047 | case 0: | |
8b646bd7 MS |
1048 | if (pcpu->state != CPU_STATE_CONFIGURED) |
1049 | break; | |
d08d9430 | 1050 | rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
1051 | if (rc) |
1052 | break; | |
10ad34bc MS |
1053 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1054 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1055 | continue; | |
1056 | pcpu[i].state = CPU_STATE_STANDBY; | |
1057 | smp_cpu_set_polarization(cpu + i, | |
1058 | POLARIZATION_UNKNOWN); | |
1059 | } | |
8b646bd7 | 1060 | topology_expect_change(); |
08d07968 HC |
1061 | break; |
1062 | case 1: | |
8b646bd7 MS |
1063 | if (pcpu->state != CPU_STATE_STANDBY) |
1064 | break; | |
d08d9430 | 1065 | rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
1066 | if (rc) |
1067 | break; | |
10ad34bc MS |
1068 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1069 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1070 | continue; | |
1071 | pcpu[i].state = CPU_STATE_CONFIGURED; | |
1072 | smp_cpu_set_polarization(cpu + i, | |
1073 | POLARIZATION_UNKNOWN); | |
1074 | } | |
8b646bd7 | 1075 | topology_expect_change(); |
08d07968 HC |
1076 | break; |
1077 | default: | |
1078 | break; | |
1079 | } | |
1080 | out: | |
08d07968 | 1081 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1082 | put_online_cpus(); |
08d07968 HC |
1083 | return rc ? rc : count; |
1084 | } | |
8a25a2fd | 1085 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
1086 | #endif /* CONFIG_HOTPLUG_CPU */ |
1087 | ||
8a25a2fd KS |
1088 | static ssize_t show_cpu_address(struct device *dev, |
1089 | struct device_attribute *attr, char *buf) | |
08d07968 | 1090 | { |
8b646bd7 | 1091 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 1092 | } |
8a25a2fd | 1093 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 1094 | |
08d07968 HC |
1095 | static struct attribute *cpu_common_attrs[] = { |
1096 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 1097 | &dev_attr_configure.attr, |
08d07968 | 1098 | #endif |
8a25a2fd | 1099 | &dev_attr_address.attr, |
08d07968 HC |
1100 | NULL, |
1101 | }; | |
1102 | ||
1103 | static struct attribute_group cpu_common_attr_group = { | |
1104 | .attrs = cpu_common_attrs, | |
1105 | }; | |
1da177e4 | 1106 | |
08d07968 | 1107 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1108 | &dev_attr_idle_count.attr, |
1109 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1110 | NULL, |
1111 | }; | |
1112 | ||
08d07968 HC |
1113 | static struct attribute_group cpu_online_attr_group = { |
1114 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1115 | }; |
1116 | ||
dfbbd86a | 1117 | static int smp_cpu_online(unsigned int cpu) |
2fc2d1e9 | 1118 | { |
2f859d0d | 1119 | struct device *s = &per_cpu(cpu_device, cpu)->dev; |
2fc2d1e9 | 1120 | |
dfbbd86a SAS |
1121 | return sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
1122 | } | |
1123 | static int smp_cpu_pre_down(unsigned int cpu) | |
1124 | { | |
1125 | struct device *s = &per_cpu(cpu_device, cpu)->dev; | |
1126 | ||
1127 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1128 | return 0; | |
2fc2d1e9 HC |
1129 | } |
1130 | ||
e2741f17 | 1131 | static int smp_add_present_cpu(int cpu) |
08d07968 | 1132 | { |
96619fc1 HC |
1133 | struct device *s; |
1134 | struct cpu *c; | |
08d07968 HC |
1135 | int rc; |
1136 | ||
96619fc1 HC |
1137 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
1138 | if (!c) | |
1139 | return -ENOMEM; | |
2f859d0d | 1140 | per_cpu(cpu_device, cpu) = c; |
96619fc1 | 1141 | s = &c->dev; |
08d07968 HC |
1142 | c->hotpluggable = 1; |
1143 | rc = register_cpu(c, cpu); | |
1144 | if (rc) | |
1145 | goto out; | |
1146 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1147 | if (rc) | |
1148 | goto out_cpu; | |
83a24e32 HC |
1149 | rc = topology_cpu_init(c); |
1150 | if (rc) | |
1151 | goto out_topology; | |
1152 | return 0; | |
1153 | ||
1154 | out_topology: | |
08d07968 HC |
1155 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1156 | out_cpu: | |
1157 | #ifdef CONFIG_HOTPLUG_CPU | |
1158 | unregister_cpu(c); | |
1159 | #endif | |
1160 | out: | |
1161 | return rc; | |
1162 | } | |
1163 | ||
1164 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1165 | |
67060d9c | 1166 | int __ref smp_rescan_cpus(void) |
08d07968 | 1167 | { |
d08d9430 | 1168 | struct sclp_core_info *info; |
8b646bd7 | 1169 | int nr; |
08d07968 | 1170 | |
af51160e | 1171 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
8b646bd7 MS |
1172 | if (!info) |
1173 | return -ENOMEM; | |
af51160e | 1174 | smp_get_core_info(info, 0); |
9d40d2e3 | 1175 | get_online_cpus(); |
0b18d318 | 1176 | mutex_lock(&smp_cpu_state_mutex); |
0c996cd9 | 1177 | nr = __smp_rescan_cpus(info, false); |
08d07968 | 1178 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1179 | put_online_cpus(); |
8b646bd7 MS |
1180 | kfree(info); |
1181 | if (nr) | |
c10fde0d | 1182 | topology_schedule_update(); |
8b646bd7 | 1183 | return 0; |
1e489518 HC |
1184 | } |
1185 | ||
8a25a2fd KS |
1186 | static ssize_t __ref rescan_store(struct device *dev, |
1187 | struct device_attribute *attr, | |
c9be0a36 | 1188 | const char *buf, |
1e489518 HC |
1189 | size_t count) |
1190 | { | |
1191 | int rc; | |
1192 | ||
106c4894 GS |
1193 | rc = lock_device_hotplug_sysfs(); |
1194 | if (rc) | |
1195 | return rc; | |
1e489518 | 1196 | rc = smp_rescan_cpus(); |
106c4894 | 1197 | unlock_device_hotplug(); |
08d07968 HC |
1198 | return rc ? rc : count; |
1199 | } | |
d6864bd8 | 1200 | static DEVICE_ATTR_WO(rescan); |
08d07968 HC |
1201 | #endif /* CONFIG_HOTPLUG_CPU */ |
1202 | ||
83a24e32 | 1203 | static int __init s390_smp_init(void) |
1da177e4 | 1204 | { |
f4edbcd5 | 1205 | int cpu, rc = 0; |
2fc2d1e9 | 1206 | |
08d07968 | 1207 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1208 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1209 | if (rc) |
1210 | return rc; | |
1211 | #endif | |
1212 | for_each_present_cpu(cpu) { | |
1213 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1214 | if (rc) |
f4edbcd5 | 1215 | goto out; |
1da177e4 | 1216 | } |
f4edbcd5 | 1217 | |
dfbbd86a SAS |
1218 | rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", |
1219 | smp_cpu_online, smp_cpu_pre_down); | |
e1108e8f | 1220 | rc = rc <= 0 ? rc : 0; |
f4edbcd5 | 1221 | out: |
f4edbcd5 | 1222 | return rc; |
1da177e4 | 1223 | } |
83a24e32 | 1224 | subsys_initcall(s390_smp_init); |