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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
8b646bd7 3 * SMP related functions
1da177e4 4 *
a53c8fab 5 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
6 * Author(s): Denis Joseph Barrow,
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
8 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 9 *
39ce010d 10 * based on other smp stuff by
1da177e4
LT
11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
12 * (c) 1998 Ingo Molnar
13 *
8b646bd7
MS
14 * The code outside of smp.c uses logical cpu numbers, only smp.c does
15 * the translation of logical to physical cpu ids. All new code that
16 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
17 */
18
395d31d4
MS
19#define KMSG_COMPONENT "cpu"
20#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
f230886b 22#include <linux/workqueue.h>
57c8a661 23#include <linux/memblock.h>
3994a52b 24#include <linux/export.h>
1da177e4 25#include <linux/init.h>
1da177e4 26#include <linux/mm.h>
4e950f6f 27#include <linux/err.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/kernel_stat.h>
1da177e4 30#include <linux/delay.h>
1da177e4 31#include <linux/interrupt.h>
3324e60a 32#include <linux/irqflags.h>
1da177e4 33#include <linux/cpu.h>
5a0e3ad6 34#include <linux/slab.h>
ef8bd77f 35#include <linux/sched/hotplug.h>
68db0cf1 36#include <linux/sched/task_stack.h>
60a0c68d 37#include <linux/crash_dump.h>
00a8f886 38#include <linux/kprobes.h>
cbb870c8 39#include <asm/asm-offsets.h>
1ec2772e 40#include <asm/diag.h>
1e3cab2f
HC
41#include <asm/switch_to.h>
42#include <asm/facility.h>
46b05d26 43#include <asm/ipl.h>
2b67fc46 44#include <asm/setup.h>
1da177e4 45#include <asm/irq.h>
1da177e4 46#include <asm/tlbflush.h>
27f6b416 47#include <asm/vtimer.h>
411ed322 48#include <asm/lowcore.h>
08d07968 49#include <asm/sclp.h>
c742b31c 50#include <asm/vdso.h>
3ab121ab 51#include <asm/debug.h>
4857d4bb 52#include <asm/os_info.h>
a9ae32c3 53#include <asm/sigp.h>
b5f87f15 54#include <asm/idle.h>
916cda1a 55#include <asm/nmi.h>
78c98f90 56#include <asm/stacktrace.h>
38389ec8 57#include <asm/topology.h>
a806170e 58#include "entry.h"
1da177e4 59
8b646bd7
MS
60enum {
61 ec_schedule = 0,
8b646bd7
MS
62 ec_call_function_single,
63 ec_stop_cpu,
64};
08d07968 65
8b646bd7 66enum {
08d07968
HC
67 CPU_STATE_STANDBY,
68 CPU_STATE_CONFIGURED,
69};
70
2f859d0d
HC
71static DEFINE_PER_CPU(struct cpu *, cpu_device);
72
8b646bd7 73struct pcpu {
c667aeac 74 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 75 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 76 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
77 signed char state; /* physical cpu state */
78 signed char polarization; /* physical polarization */
8b646bd7
MS
79 u16 address; /* physical cpu address */
80};
81
d08d9430 82static u8 boot_core_type;
8b646bd7
MS
83static struct pcpu pcpu_devices[NR_CPUS];
84
10ad34bc
MS
85unsigned int smp_cpu_mt_shift;
86EXPORT_SYMBOL(smp_cpu_mt_shift);
87
88unsigned int smp_cpu_mtid;
89EXPORT_SYMBOL(smp_cpu_mtid);
90
1a36a39e
MS
91#ifdef CONFIG_CRASH_DUMP
92__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
93#endif
94
10ad34bc
MS
95static unsigned int smp_max_threads __initdata = -1U;
96
97static int __init early_nosmt(char *s)
98{
99 smp_max_threads = 1;
100 return 0;
101}
102early_param("nosmt", early_nosmt);
103
104static int __init early_smt(char *s)
105{
106 get_option(&s, &smp_max_threads);
107 return 0;
108}
109early_param("smt", early_smt);
110
50ab9a9a
HC
111/*
112 * The smp_cpu_state_mutex must be held when changing the state or polarization
113 * member of a pcpu data structure within the pcpu_devices arreay.
114 */
dbd70fb4 115DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 116
8b646bd7
MS
117/*
118 * Signal processor helper functions.
119 */
1a36a39e 120static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 121{
8b646bd7 122 int cc;
5c0b912e 123
8b646bd7 124 while (1) {
c5e3acd6 125 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 126 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
127 return cc;
128 cpu_relax();
5c0b912e 129 }
5c0b912e
HC
130}
131
8b646bd7 132static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 133{
8b646bd7
MS
134 int cc, retry;
135
136 for (retry = 0; ; retry++) {
c5e3acd6 137 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 138 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
139 break;
140 if (retry >= 3)
141 udelay(10);
142 }
143 return cc;
144}
145
146static inline int pcpu_stopped(struct pcpu *pcpu)
147{
41459d36 148 u32 uninitialized_var(status);
c5e3acd6 149
a9ae32c3 150 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 151 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 152 return 0;
c5e3acd6 153 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
154}
155
156static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 157{
a9ae32c3 158 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 159 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 160 return 1;
524b24ad
HC
161 /* Status stored condition code is equivalent to cpu not running. */
162 return 0;
a93b8ec1
HC
163}
164
1943f53c 165/*
8b646bd7 166 * Find struct pcpu by cpu address.
1943f53c 167 */
10ad34bc 168static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
169{
170 int cpu;
171
8b646bd7
MS
172 for_each_cpu(cpu, mask)
173 if (pcpu_devices[cpu].address == address)
174 return pcpu_devices + cpu;
175 return NULL;
176}
177
178static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
179{
180 int order;
181
dea24190
HC
182 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
183 return;
184 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 185 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
186 pcpu_sigp_retry(pcpu, order, 0);
187}
188
e2741f17 189static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 190{
ce3dc447 191 unsigned long async_stack, nodat_stack;
c667aeac 192 struct lowcore *lc;
8b646bd7
MS
193
194 if (pcpu != &pcpu_devices[0]) {
c667aeac 195 pcpu->lowcore = (struct lowcore *)
8b646bd7 196 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
32ce55a6 197 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
ce3dc447 198 if (!pcpu->lowcore || !nodat_stack)
8b646bd7 199 goto out;
2f859d0d 200 } else {
ce3dc447 201 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
1943f53c 202 }
ce3dc447
MS
203 async_stack = stack_alloc();
204 if (!async_stack)
205 goto out;
8b646bd7
MS
206 lc = pcpu->lowcore;
207 memcpy(lc, &S390_lowcore, 512);
208 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
ce3dc447
MS
209 lc->async_stack = async_stack + STACK_INIT_OFFSET;
210 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET;
8b646bd7 211 lc->cpu_nr = cpu;
6c8cd5bb 212 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 213 lc->spinlock_index = 0;
f19fbd5e 214 lc->br_r1_trampoline = 0x07f1; /* br %r1 */
6c81511c 215 if (nmi_alloc_per_cpu(lc))
ce3dc447 216 goto out_async;
6c81511c
MS
217 if (vdso_alloc_per_cpu(lc))
218 goto out_mcesa;
8b646bd7 219 lowcore_ptr[cpu] = lc;
a9ae32c3 220 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7 221 return 0;
6c81511c
MS
222
223out_mcesa:
224 nmi_free_per_cpu(lc);
ce3dc447
MS
225out_async:
226 stack_free(async_stack);
8b646bd7
MS
227out:
228 if (pcpu != &pcpu_devices[0]) {
32ce55a6 229 free_pages(nodat_stack, THREAD_SIZE_ORDER);
8b646bd7
MS
230 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
231 }
232 return -ENOMEM;
1943f53c
MH
233}
234
8b646bd7 235static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 236{
ce3dc447
MS
237 unsigned long async_stack, nodat_stack, lowcore;
238
239 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
240 async_stack = pcpu->lowcore->async_stack - STACK_INIT_OFFSET;
241 lowcore = (unsigned long) pcpu->lowcore;
242
a9ae32c3 243 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 244 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 245 vdso_free_per_cpu(pcpu->lowcore);
6c81511c 246 nmi_free_per_cpu(pcpu->lowcore);
ce3dc447 247 stack_free(async_stack);
2f859d0d
HC
248 if (pcpu == &pcpu_devices[0])
249 return;
32ce55a6 250 free_pages(nodat_stack, THREAD_SIZE_ORDER);
ce3dc447 251 free_pages(lowcore, LC_ORDER);
8b646bd7
MS
252}
253
254static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
255{
c667aeac 256 struct lowcore *lc = pcpu->lowcore;
8b646bd7 257
64f31d58 258 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 259 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 260 lc->cpu_nr = cpu;
6c8cd5bb 261 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 262 lc->spinlock_index = 0;
8b646bd7
MS
263 lc->percpu_offset = __per_cpu_offset[cpu];
264 lc->kernel_asce = S390_lowcore.kernel_asce;
265 lc->machine_flags = S390_lowcore.machine_flags;
152e9b86
MS
266 lc->user_timer = lc->system_timer =
267 lc->steal_timer = lc->avg_steal_timer = 0;
8b646bd7
MS
268 __ctl_store(lc->cregs_save_area, 0, 15);
269 save_access_regs((unsigned int *) lc->access_regs_save_area);
270 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
cf148998
MS
271 sizeof(lc->stfle_fac_list));
272 memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list,
273 sizeof(lc->alt_stfle_fac_list));
b96f7d88 274 arch_spin_lock_setup(cpu);
8b646bd7
MS
275}
276
277static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
278{
c667aeac 279 struct lowcore *lc = pcpu->lowcore;
8b646bd7 280
dc7ee00d
MS
281 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
282 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 283 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
284 lc->lpp = LPP_MAGIC;
285 lc->current_pid = tsk->pid;
90c53e65 286 lc->user_timer = tsk->thread.user_timer;
b7662eef 287 lc->guest_timer = tsk->thread.guest_timer;
90c53e65 288 lc->system_timer = tsk->thread.system_timer;
b7662eef
CB
289 lc->hardirq_timer = tsk->thread.hardirq_timer;
290 lc->softirq_timer = tsk->thread.softirq_timer;
8b646bd7
MS
291 lc->steal_timer = 0;
292}
293
294static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
295{
c667aeac 296 struct lowcore *lc = pcpu->lowcore;
8b646bd7 297
ce3dc447 298 lc->restart_stack = lc->nodat_stack;
8b646bd7
MS
299 lc->restart_fn = (unsigned long) func;
300 lc->restart_data = (unsigned long) data;
301 lc->restart_source = -1UL;
a9ae32c3 302 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
303}
304
305/*
306 * Call function via PSW restart on pcpu and stop the current cpu.
307 */
ce3dc447
MS
308static void __pcpu_delegate(void (*func)(void*), void *data)
309{
310 func(data); /* should not return */
311}
312
ac1256f8
VG
313static void __no_sanitize_address pcpu_delegate(struct pcpu *pcpu,
314 void (*func)(void *),
315 void *data, unsigned long stack)
8b646bd7 316{
c667aeac 317 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 318 unsigned long source_cpu = stap();
8b646bd7 319
ce3dc447 320 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
fbe76568 321 if (pcpu->address == source_cpu)
ce3dc447 322 CALL_ON_STACK(__pcpu_delegate, stack, 2, func, data);
8b646bd7 323 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 324 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 325 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
326 mem_assign_absolute(lc->restart_stack, stack);
327 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
328 mem_assign_absolute(lc->restart_data, (unsigned long) data);
329 mem_assign_absolute(lc->restart_source, source_cpu);
d768bd89 330 __bpon();
8b646bd7 331 asm volatile(
eb546195 332 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 333 " brc 2,0b # busy, try again\n"
eb546195 334 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 335 " brc 2,1b # busy, try again\n"
fbe76568 336 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
337 "K" (SIGP_RESTART), "K" (SIGP_STOP)
338 : "0", "1", "cc");
8b646bd7
MS
339 for (;;) ;
340}
341
10ad34bc
MS
342/*
343 * Enable additional logical cpus for multi-threading.
344 */
345static int pcpu_set_smt(unsigned int mtid)
346{
10ad34bc
MS
347 int cc;
348
349 if (smp_cpu_mtid == mtid)
350 return 0;
80a60f6e 351 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
352 if (cc == 0) {
353 smp_cpu_mtid = mtid;
354 smp_cpu_mt_shift = 0;
355 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
356 smp_cpu_mt_shift++;
357 pcpu_devices[0].address = stap();
358 }
359 return cc;
360}
361
8b646bd7
MS
362/*
363 * Call function on an online CPU.
364 */
365void smp_call_online_cpu(void (*func)(void *), void *data)
366{
367 struct pcpu *pcpu;
368
369 /* Use the current cpu if it is online. */
370 pcpu = pcpu_find_address(cpu_online_mask, stap());
371 if (!pcpu)
372 /* Use the first online cpu. */
373 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
374 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
375}
376
377/*
378 * Call function on the ipl CPU.
379 */
380void smp_call_ipl_cpu(void (*func)(void *), void *data)
381{
60f1bf29
DH
382 struct lowcore *lc = pcpu_devices->lowcore;
383
384 if (pcpu_devices[0].address == stap())
385 lc = &S390_lowcore;
386
c6da39f2 387 pcpu_delegate(&pcpu_devices[0], func, data,
60f1bf29 388 lc->nodat_stack);
8b646bd7
MS
389}
390
391int smp_find_processor_id(u16 address)
392{
393 int cpu;
394
395 for_each_present_cpu(cpu)
396 if (pcpu_devices[cpu].address == address)
397 return cpu;
398 return -1;
2c2df118
HC
399}
400
760928c0 401bool arch_vcpu_is_preempted(int cpu)
85ac7ca5 402{
760928c0
CB
403 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
404 return false;
405 if (pcpu_running(pcpu_devices + cpu))
406 return false;
407 return true;
8b646bd7 408}
760928c0 409EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 410
8b646bd7 411void smp_yield_cpu(int cpu)
85ac7ca5 412{
1ec2772e 413 if (MACHINE_HAS_DIAG9C) {
b5a6b71b 414 diag_stat_inc_norecursion(DIAG_STAT_X09C);
8b646bd7
MS
415 asm volatile("diag %0,0,0x9c"
416 : : "d" (pcpu_devices[cpu].address));
38f2c691 417 } else if (MACHINE_HAS_DIAG44 && !smp_cpu_mtid) {
b5a6b71b 418 diag_stat_inc_norecursion(DIAG_STAT_X044);
8b646bd7 419 asm volatile("diag 0,0,0x44");
1ec2772e 420 }
8b646bd7
MS
421}
422
423/*
424 * Send cpus emergency shutdown signal. This gives the cpus the
425 * opportunity to complete outstanding interrupts.
426 */
00a8f886 427void notrace smp_emergency_stop(void)
8b646bd7 428{
00a8f886 429 cpumask_t cpumask;
8b646bd7
MS
430 u64 end;
431 int cpu;
432
00a8f886
MS
433 cpumask_copy(&cpumask, cpu_online_mask);
434 cpumask_clear_cpu(smp_processor_id(), &cpumask);
435
1aae0560 436 end = get_tod_clock() + (1000000UL << 12);
00a8f886 437 for_each_cpu(cpu, &cpumask) {
8b646bd7
MS
438 struct pcpu *pcpu = pcpu_devices + cpu;
439 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
440 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
441 0, NULL) == SIGP_CC_BUSY &&
1aae0560 442 get_tod_clock() < end)
8b646bd7
MS
443 cpu_relax();
444 }
1aae0560 445 while (get_tod_clock() < end) {
00a8f886 446 for_each_cpu(cpu, &cpumask)
8b646bd7 447 if (pcpu_stopped(pcpu_devices + cpu))
00a8f886
MS
448 cpumask_clear_cpu(cpu, &cpumask);
449 if (cpumask_empty(&cpumask))
8b646bd7 450 break;
85ac7ca5 451 cpu_relax();
8b646bd7 452 }
85ac7ca5 453}
00a8f886 454NOKPROBE_SYMBOL(smp_emergency_stop);
85ac7ca5 455
8b646bd7
MS
456/*
457 * Stop all cpus but the current one.
458 */
677d7623 459void smp_send_stop(void)
1da177e4 460{
85ac7ca5 461 int cpu;
1da177e4 462
677d7623 463 /* Disable all interrupts/machine checks */
e258d719 464 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 465 trace_hardirqs_off();
1da177e4 466
3ab121ab 467 debug_set_critical();
85ac7ca5 468
8b646bd7 469 if (oops_in_progress)
00a8f886 470 smp_emergency_stop();
1da177e4 471
85ac7ca5 472 /* stop all processors */
00a8f886
MS
473 for_each_online_cpu(cpu) {
474 if (cpu == smp_processor_id())
475 continue;
476 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
477 while (!pcpu_stopped(pcpu_devices + cpu))
c6b5b847
HC
478 cpu_relax();
479 }
480}
481
1da177e4
LT
482/*
483 * This is the main routine where commands issued by other
484 * cpus are handled.
485 */
9acf73b7 486static void smp_handle_ext_call(void)
1da177e4 487{
39ce010d 488 unsigned long bits;
1da177e4 489
9acf73b7
HC
490 /* handle bit signal external calls */
491 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
492 if (test_bit(ec_stop_cpu, &bits))
493 smp_stop_cpu();
184748cc
PZ
494 if (test_bit(ec_schedule, &bits))
495 scheduler_ipi();
ca9fc75a
HC
496 if (test_bit(ec_call_function_single, &bits))
497 generic_smp_call_function_single_interrupt();
9acf73b7 498}
85ac7ca5 499
9acf73b7
HC
500static void do_ext_call_interrupt(struct ext_code ext_code,
501 unsigned int param32, unsigned long param64)
502{
503 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
504 smp_handle_ext_call();
1da177e4
LT
505}
506
630cd046 507void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
508{
509 int cpu;
510
630cd046 511 for_each_cpu(cpu, mask)
b6ed49e0 512 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
513}
514
515void arch_send_call_function_single_ipi(int cpu)
516{
8b646bd7 517 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
518}
519
1da177e4
LT
520/*
521 * this function sends a 'reschedule' IPI to another CPU.
522 * it goes straight through and wastes no time serializing
523 * anything. Worst case is that we lose a reschedule ...
524 */
525void smp_send_reschedule(int cpu)
526{
8b646bd7 527 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
528}
529
530/*
531 * parameter area for the set/clear control bit callbacks
532 */
94c12cc7 533struct ec_creg_mask_parms {
8b646bd7
MS
534 unsigned long orval;
535 unsigned long andval;
536 int cr;
94c12cc7 537};
1da177e4
LT
538
539/*
540 * callback for setting/clearing control bits
541 */
39ce010d
HC
542static void smp_ctl_bit_callback(void *info)
543{
94c12cc7 544 struct ec_creg_mask_parms *pp = info;
1da177e4 545 unsigned long cregs[16];
39ce010d 546
94c12cc7 547 __ctl_store(cregs, 0, 15);
8b646bd7 548 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 549 __ctl_load(cregs, 0, 15);
1da177e4
LT
550}
551
552/*
553 * Set a bit in a control register of all cpus
554 */
94c12cc7
MS
555void smp_ctl_set_bit(int cr, int bit)
556{
8b646bd7 557 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 558
15c8b6c1 559 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 560}
39ce010d 561EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
562
563/*
564 * Clear a bit in a control register of all cpus
565 */
94c12cc7
MS
566void smp_ctl_clear_bit(int cr, int bit)
567{
8b646bd7 568 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 569
15c8b6c1 570 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 571}
39ce010d 572EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 573
bf28a597 574#ifdef CONFIG_CRASH_DUMP
411ed322 575
1af135a1
HC
576int smp_store_status(int cpu)
577{
1a36a39e
MS
578 struct pcpu *pcpu = pcpu_devices + cpu;
579 unsigned long pa;
1af135a1 580
1a36a39e
MS
581 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
582 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
583 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1 584 return -EIO;
916cda1a 585 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
1af135a1 586 return 0;
916cda1a
MS
587 pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
588 if (MACHINE_HAS_GS)
589 pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
1a36a39e
MS
590 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
591 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
592 return -EIO;
1af135a1
HC
593 return 0;
594}
595
10ad34bc
MS
596/*
597 * Collect CPU state of the previous, crashed system.
598 * There are four cases:
599 * 1) standard zfcp dump
600 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
601 * The state for all CPUs except the boot CPU needs to be collected
602 * with sigp stop-and-store-status. The boot CPU state is located in
603 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 604 * will copy the boot CPU state from the HSA.
10ad34bc
MS
605 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
606 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
607 * The state for all CPUs except the boot CPU needs to be collected
608 * with sigp stop-and-store-status. The firmware or the boot-loader
609 * stored the registers of the boot CPU in the absolute lowcore in the
610 * memory of the old system.
611 * 3) kdump and the old kernel did not store the CPU state,
612 * or stand-alone kdump for DASD
613 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
614 * The state for all CPUs except the boot CPU needs to be collected
615 * with sigp stop-and-store-status. The kexec code or the boot-loader
616 * stored the registers of the boot CPU in the memory of the old system.
617 * 4) kdump and the old kernel stored the CPU state
618 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
619 * This case does not exist for s390 anymore, setup_arch explicitly
620 * deactivates the elfcorehdr= kernel parameter
10ad34bc 621 */
1a2c5840 622static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
623 bool is_boot_cpu, unsigned long page)
624{
625 __vector128 *vxrs = (__vector128 *) page;
626
627 if (is_boot_cpu)
628 vxrs = boot_cpu_vector_save_area;
629 else
630 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 631 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
632}
633
1a2c5840 634static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
635 bool is_boot_cpu, unsigned long page)
636{
637 void *regs = (void *) page;
638
639 if (is_boot_cpu)
640 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
641 else
642 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 643 save_area_add_regs(sa, regs);
1a36a39e
MS
644}
645
1592a8e4 646void __init smp_save_dump_cpus(void)
10ad34bc 647{
1a2c5840
MS
648 int addr, boot_cpu_addr, max_cpu_addr;
649 struct save_area *sa;
1a36a39e 650 unsigned long page;
1592a8e4 651 bool is_boot_cpu;
10ad34bc 652
10ad34bc
MS
653 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
654 /* No previous system present, normal boot. */
655 return;
1a36a39e 656 /* Allocate a page as dumping area for the store status sigps */
0ba9e6ed
MR
657 page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31);
658 if (!page)
8a7f97b9 659 panic("ERROR: Failed to allocate %lx bytes below %lx\n",
0ba9e6ed
MR
660 PAGE_SIZE, 1UL << 31);
661
10ad34bc 662 /* Set multi-threading state to the previous system. */
37c5f6c8 663 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 664 boot_cpu_addr = stap();
1a2c5840
MS
665 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
666 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 667 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
668 SIGP_CC_NOT_OPERATIONAL)
669 continue;
1592a8e4 670 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
671 /* Allocate save area */
672 sa = save_area_alloc(is_boot_cpu);
673 if (!sa)
674 panic("could not allocate memory for save area\n");
1a36a39e
MS
675 if (MACHINE_HAS_VX)
676 /* Get the vector registers */
1a2c5840 677 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
678 /*
679 * For a zfcp dump OLDMEM_BASE == NULL and the registers
680 * of the boot CPU are stored in the HSA. To retrieve
681 * these registers an SCLP request is required which is
682 * done by drivers/s390/char/zcore.c:init_cpu_info()
683 */
684 if (!is_boot_cpu || OLDMEM_BASE)
685 /* Get the CPU registers */
1a2c5840 686 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 687 }
1a36a39e 688 memblock_free(page, PAGE_SIZE);
a80313ff 689 diag_dma_ops.diag308_reset();
1592a8e4 690 pcpu_set_smt(0);
1af135a1 691}
1a36a39e 692#endif /* CONFIG_CRASH_DUMP */
08d07968 693
50ab9a9a
HC
694void smp_cpu_set_polarization(int cpu, int val)
695{
696 pcpu_devices[cpu].polarization = val;
697}
698
699int smp_cpu_get_polarization(int cpu)
700{
701 return pcpu_devices[cpu].polarization;
702}
703
af51160e 704static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 705{
8b646bd7 706 static int use_sigp_detection;
8b646bd7
MS
707 int address;
708
af51160e 709 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 710 use_sigp_detection = 1;
e7086eb1 711 for (address = 0;
d08d9430 712 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 713 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 714 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 715 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 716 continue;
d08d9430 717 info->core[info->configured].core_id =
10ad34bc 718 address >> smp_cpu_mt_shift;
8b646bd7
MS
719 info->configured++;
720 }
721 info->combined = info->configured;
08d07968 722 }
08d07968
HC
723}
724
e2741f17 725static int smp_add_present_cpu(int cpu);
8b646bd7 726
d08d9430 727static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 728{
8b646bd7 729 struct pcpu *pcpu;
08d07968 730 cpumask_t avail;
10ad34bc
MS
731 int cpu, nr, i, j;
732 u16 address;
08d07968 733
8b646bd7 734 nr = 0;
0f1959f5 735 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
736 cpu = cpumask_first(&avail);
737 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 738 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 739 continue;
d08d9430 740 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
741 for (j = 0; j <= smp_cpu_mtid; j++) {
742 if (pcpu_find_address(cpu_present_mask, address + j))
743 continue;
744 pcpu = pcpu_devices + cpu;
745 pcpu->address = address + j;
746 pcpu->state =
747 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
748 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
749 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
750 set_cpu_present(cpu, true);
751 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
752 set_cpu_present(cpu, false);
753 else
754 nr++;
755 cpu = cpumask_next(cpu, &avail);
756 if (cpu >= nr_cpu_ids)
757 break;
758 }
8b646bd7
MS
759 }
760 return nr;
1da177e4
LT
761}
762
af51160e 763void __init smp_detect_cpus(void)
48483b32 764{
10ad34bc 765 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 766 struct sclp_core_info *info;
10ad34bc 767 u16 address;
48483b32 768
10ad34bc 769 /* Get CPU information */
eb31d559 770 info = memblock_alloc(sizeof(*info), 8);
8a7f97b9
MR
771 if (!info)
772 panic("%s: Failed to allocate %zu bytes align=0x%x\n",
773 __func__, sizeof(*info), 8);
af51160e 774 smp_get_core_info(info, 1);
10ad34bc 775 /* Find boot CPU type */
d08d9430 776 if (sclp.has_core_type) {
10ad34bc
MS
777 address = stap();
778 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 779 if (info->core[cpu].core_id == address) {
10ad34bc 780 /* The boot cpu dictates the cpu type. */
d08d9430 781 boot_core_type = info->core[cpu].type;
10ad34bc
MS
782 break;
783 }
784 if (cpu >= info->combined)
785 panic("Could not find boot CPU type");
48483b32 786 }
10ad34bc 787
10ad34bc 788 /* Set multi-threading state for the current system */
d08d9430 789 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
790 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
791 pcpu_set_smt(mtid);
792
793 /* Print number of CPUs */
8b646bd7 794 c_cpus = s_cpus = 0;
48483b32 795 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
796 if (sclp.has_core_type &&
797 info->core[cpu].type != boot_core_type)
48483b32 798 continue;
10ad34bc
MS
799 if (cpu < info->configured)
800 c_cpus += smp_cpu_mtid + 1;
801 else
802 s_cpus += smp_cpu_mtid + 1;
48483b32 803 }
395d31d4 804 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
805
806 /* Add CPUs present at boot */
9d40d2e3 807 get_online_cpus();
8b646bd7 808 __smp_rescan_cpus(info, 0);
9d40d2e3 809 put_online_cpus();
af51160e 810 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
811}
812
ce3dc447 813static void smp_init_secondary(void)
1da177e4 814{
1887aa07
MS
815 int cpu = smp_processor_id();
816
9e8df6da
VG
817 S390_lowcore.last_update_clock = get_tod_clock();
818 restore_access_regs(S390_lowcore.access_regs_save_area);
39ce010d 819 cpu_init();
5bfb5d69 820 preempt_disable();
39ce010d 821 init_cpu_timer();
b5f87f15 822 vtime_init();
29b08d2b 823 pfault_init();
ce3dc447 824 notify_cpu_starting(smp_processor_id());
1887aa07
MS
825 if (topology_cpu_dedicated(cpu))
826 set_cpu_flag(CIF_DEDICATED_CPU);
827 else
828 clear_cpu_flag(CIF_DEDICATED_CPU);
ce3dc447 829 set_cpu_online(smp_processor_id(), true);
93f3b2ee 830 inc_irq_stat(CPU_RST);
1da177e4 831 local_irq_enable();
fc6d73d6 832 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
833}
834
ce3dc447
MS
835/*
836 * Activate a secondary processor.
837 */
9e8df6da 838static void __no_sanitize_address smp_start_secondary(void *cpuvoid)
ce3dc447 839{
ce3dc447
MS
840 S390_lowcore.restart_stack = (unsigned long) restart_stack;
841 S390_lowcore.restart_fn = (unsigned long) do_restart;
842 S390_lowcore.restart_data = 0;
843 S390_lowcore.restart_source = -1UL;
ce3dc447
MS
844 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
845 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
846 CALL_ON_STACK(smp_init_secondary, S390_lowcore.kernel_stack, 0);
847}
848
1da177e4 849/* Upping and downing of CPUs */
e2741f17 850int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 851{
8b646bd7 852 struct pcpu *pcpu;
10ad34bc 853 int base, i, rc;
1da177e4 854
8b646bd7
MS
855 pcpu = pcpu_devices + cpu;
856 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 857 return -EIO;
5423145f 858 base = smp_get_base_cpu(cpu);
10ad34bc
MS
859 for (i = 0; i <= smp_cpu_mtid; i++) {
860 if (base + i < nr_cpu_ids)
861 if (cpu_online(base + i))
862 break;
863 }
864 /*
865 * If this is the first CPU of the core to get online
866 * do an initial CPU reset.
867 */
868 if (i > smp_cpu_mtid &&
869 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 870 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 871 return -EIO;
e80e7813 872
8b646bd7
MS
873 rc = pcpu_alloc_lowcore(pcpu, cpu);
874 if (rc)
875 return rc;
876 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 877 pcpu_attach_task(pcpu, tidle);
8b646bd7 878 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 879 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 880 while (!cpu_online(cpu))
1da177e4
LT
881 cpu_relax();
882 return 0;
883}
884
d80512f8 885static unsigned int setup_possible_cpus __initdata;
255acee7 886
d80512f8
HC
887static int __init _setup_possible_cpus(char *s)
888{
889 get_option(&s, &setup_possible_cpus);
37a33026
HC
890 return 0;
891}
d80512f8 892early_param("possible_cpus", _setup_possible_cpus);
37a33026 893
39ce010d 894int __cpu_disable(void)
1da177e4 895{
8b646bd7 896 unsigned long cregs[16];
1da177e4 897
9acf73b7
HC
898 /* Handle possible pending IPIs */
899 smp_handle_ext_call();
8b646bd7
MS
900 set_cpu_online(smp_processor_id(), false);
901 /* Disable pseudo page faults on this cpu. */
29b08d2b 902 pfault_fini();
8b646bd7
MS
903 /* Disable interrupt sources via control register. */
904 __ctl_store(cregs, 0, 15);
905 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
906 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
907 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
908 __ctl_load(cregs, 0, 15);
fe0f4976 909 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
910 return 0;
911}
912
39ce010d 913void __cpu_die(unsigned int cpu)
1da177e4 914{
8b646bd7
MS
915 struct pcpu *pcpu;
916
1da177e4 917 /* Wait until target cpu is down */
8b646bd7
MS
918 pcpu = pcpu_devices + cpu;
919 while (!pcpu_stopped(pcpu))
1da177e4 920 cpu_relax();
8b646bd7 921 pcpu_free_lowcore(pcpu);
1b948d6c 922 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 923 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
924}
925
b456d94a 926void __noreturn cpu_die(void)
1da177e4
LT
927{
928 idle_task_exit();
d768bd89 929 __bpon();
a9ae32c3 930 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 931 for (;;) ;
1da177e4
LT
932}
933
d80512f8
HC
934void __init smp_fill_possible_mask(void)
935{
9747bc47 936 unsigned int possible, sclp_max, cpu;
d80512f8 937
3a9f3fe6
DH
938 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
939 sclp_max = min(smp_max_threads, sclp_max);
61282aff 940 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 941 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 942 possible = min(possible, sclp_max);
d80512f8
HC
943 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
944 set_cpu_possible(cpu, true);
945}
946
1da177e4
LT
947void __init smp_prepare_cpus(unsigned int max_cpus)
948{
39ce010d 949 /* request the 0x1201 emergency signal external interrupt */
1dad093b 950 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 951 panic("Couldn't request external interrupt 0x1201");
d98e19cc 952 /* request the 0x1202 external call external interrupt */
1dad093b 953 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 954 panic("Couldn't request external interrupt 0x1202");
1da177e4
LT
955}
956
ea1f4eec 957void __init smp_prepare_boot_cpu(void)
1da177e4 958{
8b646bd7
MS
959 struct pcpu *pcpu = pcpu_devices;
960
0861b5a7 961 WARN_ON(!cpu_present(0) || !cpu_online(0));
8b646bd7 962 pcpu->state = CPU_STATE_CONFIGURED;
c667aeac 963 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 964 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 965 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1da177e4
LT
966}
967
ea1f4eec 968void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 969{
1da177e4
LT
970}
971
02beaccc
HC
972void __init smp_setup_processor_id(void)
973{
0861b5a7 974 pcpu_devices[0].address = stap();
02beaccc 975 S390_lowcore.cpu_nr = 0;
6c8cd5bb 976 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
b96f7d88 977 S390_lowcore.spinlock_index = 0;
02beaccc
HC
978}
979
1da177e4
LT
980/*
981 * the frequency of the profiling timer can be changed
982 * by writing a multiplier value into /proc/profile.
983 *
984 * usually you want to run this on all CPUs ;)
985 */
986int setup_profiling_timer(unsigned int multiplier)
987{
39ce010d 988 return 0;
1da177e4
LT
989}
990
8a25a2fd 991static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 992 struct device_attribute *attr, char *buf)
08d07968
HC
993{
994 ssize_t count;
995
996 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 997 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
998 mutex_unlock(&smp_cpu_state_mutex);
999 return count;
1000}
1001
8a25a2fd 1002static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
1003 struct device_attribute *attr,
1004 const char *buf, size_t count)
08d07968 1005{
8b646bd7 1006 struct pcpu *pcpu;
10ad34bc 1007 int cpu, val, rc, i;
08d07968
HC
1008 char delim;
1009
1010 if (sscanf(buf, "%d %c", &val, &delim) != 1)
1011 return -EINVAL;
1012 if (val != 0 && val != 1)
1013 return -EINVAL;
9d40d2e3 1014 get_online_cpus();
0b18d318 1015 mutex_lock(&smp_cpu_state_mutex);
08d07968 1016 rc = -EBUSY;
2c2df118 1017 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 1018 cpu = dev->id;
5423145f 1019 cpu = smp_get_base_cpu(cpu);
10ad34bc 1020 if (cpu == 0)
08d07968 1021 goto out;
10ad34bc
MS
1022 for (i = 0; i <= smp_cpu_mtid; i++)
1023 if (cpu_online(cpu + i))
1024 goto out;
8b646bd7 1025 pcpu = pcpu_devices + cpu;
08d07968
HC
1026 rc = 0;
1027 switch (val) {
1028 case 0:
8b646bd7
MS
1029 if (pcpu->state != CPU_STATE_CONFIGURED)
1030 break;
d08d9430 1031 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1032 if (rc)
1033 break;
10ad34bc
MS
1034 for (i = 0; i <= smp_cpu_mtid; i++) {
1035 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1036 continue;
1037 pcpu[i].state = CPU_STATE_STANDBY;
1038 smp_cpu_set_polarization(cpu + i,
1039 POLARIZATION_UNKNOWN);
1040 }
8b646bd7 1041 topology_expect_change();
08d07968
HC
1042 break;
1043 case 1:
8b646bd7
MS
1044 if (pcpu->state != CPU_STATE_STANDBY)
1045 break;
d08d9430 1046 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1047 if (rc)
1048 break;
10ad34bc
MS
1049 for (i = 0; i <= smp_cpu_mtid; i++) {
1050 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1051 continue;
1052 pcpu[i].state = CPU_STATE_CONFIGURED;
1053 smp_cpu_set_polarization(cpu + i,
1054 POLARIZATION_UNKNOWN);
1055 }
8b646bd7 1056 topology_expect_change();
08d07968
HC
1057 break;
1058 default:
1059 break;
1060 }
1061out:
08d07968 1062 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1063 put_online_cpus();
08d07968
HC
1064 return rc ? rc : count;
1065}
8a25a2fd 1066static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968 1067
8a25a2fd
KS
1068static ssize_t show_cpu_address(struct device *dev,
1069 struct device_attribute *attr, char *buf)
08d07968 1070{
8b646bd7 1071 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1072}
8a25a2fd 1073static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1074
08d07968 1075static struct attribute *cpu_common_attrs[] = {
8a25a2fd 1076 &dev_attr_configure.attr,
8a25a2fd 1077 &dev_attr_address.attr,
08d07968
HC
1078 NULL,
1079};
1080
1081static struct attribute_group cpu_common_attr_group = {
1082 .attrs = cpu_common_attrs,
1083};
1da177e4 1084
08d07968 1085static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1086 &dev_attr_idle_count.attr,
1087 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1088 NULL,
1089};
1090
08d07968
HC
1091static struct attribute_group cpu_online_attr_group = {
1092 .attrs = cpu_online_attrs,
fae8b22d
HC
1093};
1094
dfbbd86a 1095static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1096{
2f859d0d 1097 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1098
dfbbd86a
SAS
1099 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1100}
1101static int smp_cpu_pre_down(unsigned int cpu)
1102{
1103 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1104
1105 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1106 return 0;
2fc2d1e9
HC
1107}
1108
e2741f17 1109static int smp_add_present_cpu(int cpu)
08d07968 1110{
96619fc1
HC
1111 struct device *s;
1112 struct cpu *c;
08d07968
HC
1113 int rc;
1114
96619fc1
HC
1115 c = kzalloc(sizeof(*c), GFP_KERNEL);
1116 if (!c)
1117 return -ENOMEM;
2f859d0d 1118 per_cpu(cpu_device, cpu) = c;
96619fc1 1119 s = &c->dev;
08d07968
HC
1120 c->hotpluggable = 1;
1121 rc = register_cpu(c, cpu);
1122 if (rc)
1123 goto out;
1124 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1125 if (rc)
1126 goto out_cpu;
83a24e32
HC
1127 rc = topology_cpu_init(c);
1128 if (rc)
1129 goto out_topology;
1130 return 0;
1131
1132out_topology:
08d07968
HC
1133 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1134out_cpu:
08d07968 1135 unregister_cpu(c);
08d07968
HC
1136out:
1137 return rc;
1138}
1139
67060d9c 1140int __ref smp_rescan_cpus(void)
08d07968 1141{
d08d9430 1142 struct sclp_core_info *info;
8b646bd7 1143 int nr;
08d07968 1144
af51160e 1145 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1146 if (!info)
1147 return -ENOMEM;
af51160e 1148 smp_get_core_info(info, 0);
9d40d2e3 1149 get_online_cpus();
0b18d318 1150 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1151 nr = __smp_rescan_cpus(info, 1);
08d07968 1152 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1153 put_online_cpus();
8b646bd7
MS
1154 kfree(info);
1155 if (nr)
c10fde0d 1156 topology_schedule_update();
8b646bd7 1157 return 0;
1e489518
HC
1158}
1159
8a25a2fd
KS
1160static ssize_t __ref rescan_store(struct device *dev,
1161 struct device_attribute *attr,
c9be0a36 1162 const char *buf,
1e489518
HC
1163 size_t count)
1164{
1165 int rc;
1166
b7cb707c
GS
1167 rc = lock_device_hotplug_sysfs();
1168 if (rc)
1169 return rc;
1e489518 1170 rc = smp_rescan_cpus();
b7cb707c 1171 unlock_device_hotplug();
08d07968
HC
1172 return rc ? rc : count;
1173}
6cbaefb4 1174static DEVICE_ATTR_WO(rescan);
08d07968 1175
83a24e32 1176static int __init s390_smp_init(void)
1da177e4 1177{
f4edbcd5 1178 int cpu, rc = 0;
2fc2d1e9 1179
8a25a2fd 1180 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1181 if (rc)
1182 return rc;
08d07968
HC
1183 for_each_present_cpu(cpu) {
1184 rc = smp_add_present_cpu(cpu);
fae8b22d 1185 if (rc)
f4edbcd5 1186 goto out;
1da177e4 1187 }
f4edbcd5 1188
dfbbd86a
SAS
1189 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1190 smp_cpu_online, smp_cpu_pre_down);
e1108e8f 1191 rc = rc <= 0 ? rc : 0;
f4edbcd5 1192out:
f4edbcd5 1193 return rc;
1da177e4 1194}
83a24e32 1195subsys_initcall(s390_smp_init);