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1da177e4 1/*
8b646bd7 2 * SMP related functions
1da177e4 3 *
a53c8fab 4 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
5 * Author(s): Denis Joseph Barrow,
6 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
7 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 8 *
39ce010d 9 * based on other smp stuff by
1da177e4
LT
10 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
11 * (c) 1998 Ingo Molnar
12 *
8b646bd7
MS
13 * The code outside of smp.c uses logical cpu numbers, only smp.c does
14 * the translation of logical to physical cpu ids. All new code that
15 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
16 */
17
395d31d4
MS
18#define KMSG_COMPONENT "cpu"
19#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
f230886b 21#include <linux/workqueue.h>
af51160e 22#include <linux/bootmem.h>
1da177e4
LT
23#include <linux/module.h>
24#include <linux/init.h>
1da177e4 25#include <linux/mm.h>
4e950f6f 26#include <linux/err.h>
1da177e4
LT
27#include <linux/spinlock.h>
28#include <linux/kernel_stat.h>
1da177e4 29#include <linux/delay.h>
1da177e4 30#include <linux/interrupt.h>
3324e60a 31#include <linux/irqflags.h>
1da177e4 32#include <linux/cpu.h>
5a0e3ad6 33#include <linux/slab.h>
60a0c68d 34#include <linux/crash_dump.h>
1592a8e4 35#include <linux/memblock.h>
cbb870c8 36#include <asm/asm-offsets.h>
1ec2772e 37#include <asm/diag.h>
1e3cab2f
HC
38#include <asm/switch_to.h>
39#include <asm/facility.h>
46b05d26 40#include <asm/ipl.h>
2b67fc46 41#include <asm/setup.h>
1da177e4 42#include <asm/irq.h>
1da177e4 43#include <asm/tlbflush.h>
27f6b416 44#include <asm/vtimer.h>
411ed322 45#include <asm/lowcore.h>
08d07968 46#include <asm/sclp.h>
c742b31c 47#include <asm/vdso.h>
3ab121ab 48#include <asm/debug.h>
4857d4bb 49#include <asm/os_info.h>
a9ae32c3 50#include <asm/sigp.h>
b5f87f15 51#include <asm/idle.h>
a806170e 52#include "entry.h"
1da177e4 53
8b646bd7
MS
54enum {
55 ec_schedule = 0,
8b646bd7
MS
56 ec_call_function_single,
57 ec_stop_cpu,
58};
08d07968 59
8b646bd7 60enum {
08d07968
HC
61 CPU_STATE_STANDBY,
62 CPU_STATE_CONFIGURED,
63};
64
2f859d0d
HC
65static DEFINE_PER_CPU(struct cpu *, cpu_device);
66
8b646bd7 67struct pcpu {
c667aeac 68 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 69 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 70 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
71 signed char state; /* physical cpu state */
72 signed char polarization; /* physical polarization */
8b646bd7
MS
73 u16 address; /* physical cpu address */
74};
75
d08d9430 76static u8 boot_core_type;
8b646bd7
MS
77static struct pcpu pcpu_devices[NR_CPUS];
78
10ad34bc
MS
79unsigned int smp_cpu_mt_shift;
80EXPORT_SYMBOL(smp_cpu_mt_shift);
81
82unsigned int smp_cpu_mtid;
83EXPORT_SYMBOL(smp_cpu_mtid);
84
1a36a39e
MS
85#ifdef CONFIG_CRASH_DUMP
86__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
87#endif
88
10ad34bc
MS
89static unsigned int smp_max_threads __initdata = -1U;
90
91static int __init early_nosmt(char *s)
92{
93 smp_max_threads = 1;
94 return 0;
95}
96early_param("nosmt", early_nosmt);
97
98static int __init early_smt(char *s)
99{
100 get_option(&s, &smp_max_threads);
101 return 0;
102}
103early_param("smt", early_smt);
104
50ab9a9a
HC
105/*
106 * The smp_cpu_state_mutex must be held when changing the state or polarization
107 * member of a pcpu data structure within the pcpu_devices arreay.
108 */
dbd70fb4 109DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 110
8b646bd7
MS
111/*
112 * Signal processor helper functions.
113 */
1a36a39e 114static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 115{
8b646bd7 116 int cc;
5c0b912e 117
8b646bd7 118 while (1) {
c5e3acd6 119 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 120 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
121 return cc;
122 cpu_relax();
5c0b912e 123 }
5c0b912e
HC
124}
125
8b646bd7 126static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 127{
8b646bd7
MS
128 int cc, retry;
129
130 for (retry = 0; ; retry++) {
c5e3acd6 131 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 132 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
133 break;
134 if (retry >= 3)
135 udelay(10);
136 }
137 return cc;
138}
139
140static inline int pcpu_stopped(struct pcpu *pcpu)
141{
41459d36 142 u32 uninitialized_var(status);
c5e3acd6 143
a9ae32c3 144 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 145 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 146 return 0;
c5e3acd6 147 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
148}
149
150static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 151{
a9ae32c3 152 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 153 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 154 return 1;
524b24ad
HC
155 /* Status stored condition code is equivalent to cpu not running. */
156 return 0;
a93b8ec1
HC
157}
158
1943f53c 159/*
8b646bd7 160 * Find struct pcpu by cpu address.
1943f53c 161 */
10ad34bc 162static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
163{
164 int cpu;
165
8b646bd7
MS
166 for_each_cpu(cpu, mask)
167 if (pcpu_devices[cpu].address == address)
168 return pcpu_devices + cpu;
169 return NULL;
170}
171
172static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
173{
174 int order;
175
dea24190
HC
176 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
177 return;
178 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 179 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
180 pcpu_sigp_retry(pcpu, order, 0);
181}
182
2f859d0d
HC
183#define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
184#define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
185
e2741f17 186static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 187{
2f859d0d 188 unsigned long async_stack, panic_stack;
c667aeac 189 struct lowcore *lc;
8b646bd7
MS
190
191 if (pcpu != &pcpu_devices[0]) {
c667aeac 192 pcpu->lowcore = (struct lowcore *)
8b646bd7 193 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
2f859d0d
HC
194 async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
195 panic_stack = __get_free_page(GFP_KERNEL);
196 if (!pcpu->lowcore || !panic_stack || !async_stack)
8b646bd7 197 goto out;
2f859d0d
HC
198 } else {
199 async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
200 panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
1943f53c 201 }
8b646bd7
MS
202 lc = pcpu->lowcore;
203 memcpy(lc, &S390_lowcore, 512);
204 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
2f859d0d
HC
205 lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
206 lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
8b646bd7 207 lc->cpu_nr = cpu;
6c8cd5bb 208 lc->spinlock_lockval = arch_spin_lockval(cpu);
80703617
MS
209 if (MACHINE_HAS_VX)
210 lc->vector_save_area_addr =
211 (unsigned long) &lc->vector_save_area;
8b646bd7
MS
212 if (vdso_alloc_per_cpu(lc))
213 goto out;
8b646bd7 214 lowcore_ptr[cpu] = lc;
a9ae32c3 215 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7
MS
216 return 0;
217out:
218 if (pcpu != &pcpu_devices[0]) {
2f859d0d
HC
219 free_page(panic_stack);
220 free_pages(async_stack, ASYNC_ORDER);
8b646bd7
MS
221 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
222 }
223 return -ENOMEM;
1943f53c
MH
224}
225
9d0f46af
HC
226#ifdef CONFIG_HOTPLUG_CPU
227
8b646bd7 228static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 229{
a9ae32c3 230 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 231 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 232 vdso_free_per_cpu(pcpu->lowcore);
2f859d0d
HC
233 if (pcpu == &pcpu_devices[0])
234 return;
235 free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
236 free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
237 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
8b646bd7
MS
238}
239
9d0f46af
HC
240#endif /* CONFIG_HOTPLUG_CPU */
241
8b646bd7
MS
242static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
243{
c667aeac 244 struct lowcore *lc = pcpu->lowcore;
8b646bd7 245
64f31d58 246 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 247 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 248 lc->cpu_nr = cpu;
6c8cd5bb 249 lc->spinlock_lockval = arch_spin_lockval(cpu);
8b646bd7
MS
250 lc->percpu_offset = __per_cpu_offset[cpu];
251 lc->kernel_asce = S390_lowcore.kernel_asce;
252 lc->machine_flags = S390_lowcore.machine_flags;
8b646bd7
MS
253 lc->user_timer = lc->system_timer = lc->steal_timer = 0;
254 __ctl_store(lc->cregs_save_area, 0, 15);
255 save_access_regs((unsigned int *) lc->access_regs_save_area);
256 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
257 MAX_FACILITY_BIT/8);
258}
259
260static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
261{
c667aeac 262 struct lowcore *lc = pcpu->lowcore;
8b646bd7 263
dc7ee00d
MS
264 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
265 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 266 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
267 lc->lpp = LPP_MAGIC;
268 lc->current_pid = tsk->pid;
90c53e65
MS
269 lc->user_timer = tsk->thread.user_timer;
270 lc->system_timer = tsk->thread.system_timer;
8b646bd7
MS
271 lc->steal_timer = 0;
272}
273
274static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
275{
c667aeac 276 struct lowcore *lc = pcpu->lowcore;
8b646bd7
MS
277
278 lc->restart_stack = lc->kernel_stack;
279 lc->restart_fn = (unsigned long) func;
280 lc->restart_data = (unsigned long) data;
281 lc->restart_source = -1UL;
a9ae32c3 282 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
283}
284
285/*
286 * Call function via PSW restart on pcpu and stop the current cpu.
287 */
288static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
289 void *data, unsigned long stack)
290{
c667aeac 291 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 292 unsigned long source_cpu = stap();
8b646bd7 293
e258d719 294 __load_psw_mask(PSW_KERNEL_BITS);
fbe76568 295 if (pcpu->address == source_cpu)
8b646bd7
MS
296 func(data); /* should not return */
297 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 298 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 299 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
300 mem_assign_absolute(lc->restart_stack, stack);
301 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
302 mem_assign_absolute(lc->restart_data, (unsigned long) data);
303 mem_assign_absolute(lc->restart_source, source_cpu);
8b646bd7 304 asm volatile(
eb546195 305 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 306 " brc 2,0b # busy, try again\n"
eb546195 307 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 308 " brc 2,1b # busy, try again\n"
fbe76568 309 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
310 "K" (SIGP_RESTART), "K" (SIGP_STOP)
311 : "0", "1", "cc");
8b646bd7
MS
312 for (;;) ;
313}
314
10ad34bc
MS
315/*
316 * Enable additional logical cpus for multi-threading.
317 */
318static int pcpu_set_smt(unsigned int mtid)
319{
10ad34bc
MS
320 int cc;
321
322 if (smp_cpu_mtid == mtid)
323 return 0;
80a60f6e 324 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
325 if (cc == 0) {
326 smp_cpu_mtid = mtid;
327 smp_cpu_mt_shift = 0;
328 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
329 smp_cpu_mt_shift++;
330 pcpu_devices[0].address = stap();
331 }
332 return cc;
333}
334
8b646bd7
MS
335/*
336 * Call function on an online CPU.
337 */
338void smp_call_online_cpu(void (*func)(void *), void *data)
339{
340 struct pcpu *pcpu;
341
342 /* Use the current cpu if it is online. */
343 pcpu = pcpu_find_address(cpu_online_mask, stap());
344 if (!pcpu)
345 /* Use the first online cpu. */
346 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
347 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
348}
349
350/*
351 * Call function on the ipl CPU.
352 */
353void smp_call_ipl_cpu(void (*func)(void *), void *data)
354{
c6da39f2 355 pcpu_delegate(&pcpu_devices[0], func, data,
2f859d0d
HC
356 pcpu_devices->lowcore->panic_stack -
357 PANIC_FRAME_OFFSET + PAGE_SIZE);
8b646bd7
MS
358}
359
360int smp_find_processor_id(u16 address)
361{
362 int cpu;
363
364 for_each_present_cpu(cpu)
365 if (pcpu_devices[cpu].address == address)
366 return cpu;
367 return -1;
2c2df118
HC
368}
369
760928c0 370bool arch_vcpu_is_preempted(int cpu)
85ac7ca5 371{
760928c0
CB
372 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
373 return false;
374 if (pcpu_running(pcpu_devices + cpu))
375 return false;
376 return true;
8b646bd7 377}
760928c0 378EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 379
8b646bd7 380void smp_yield_cpu(int cpu)
85ac7ca5 381{
1ec2772e 382 if (MACHINE_HAS_DIAG9C) {
b5a6b71b 383 diag_stat_inc_norecursion(DIAG_STAT_X09C);
8b646bd7
MS
384 asm volatile("diag %0,0,0x9c"
385 : : "d" (pcpu_devices[cpu].address));
1ec2772e 386 } else if (MACHINE_HAS_DIAG44) {
b5a6b71b 387 diag_stat_inc_norecursion(DIAG_STAT_X044);
8b646bd7 388 asm volatile("diag 0,0,0x44");
1ec2772e 389 }
8b646bd7
MS
390}
391
392/*
393 * Send cpus emergency shutdown signal. This gives the cpus the
394 * opportunity to complete outstanding interrupts.
395 */
63df41d6 396static void smp_emergency_stop(cpumask_t *cpumask)
8b646bd7
MS
397{
398 u64 end;
399 int cpu;
400
1aae0560 401 end = get_tod_clock() + (1000000UL << 12);
8b646bd7
MS
402 for_each_cpu(cpu, cpumask) {
403 struct pcpu *pcpu = pcpu_devices + cpu;
404 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
405 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
406 0, NULL) == SIGP_CC_BUSY &&
1aae0560 407 get_tod_clock() < end)
8b646bd7
MS
408 cpu_relax();
409 }
1aae0560 410 while (get_tod_clock() < end) {
8b646bd7
MS
411 for_each_cpu(cpu, cpumask)
412 if (pcpu_stopped(pcpu_devices + cpu))
413 cpumask_clear_cpu(cpu, cpumask);
414 if (cpumask_empty(cpumask))
415 break;
85ac7ca5 416 cpu_relax();
8b646bd7 417 }
85ac7ca5
MS
418}
419
8b646bd7
MS
420/*
421 * Stop all cpus but the current one.
422 */
677d7623 423void smp_send_stop(void)
1da177e4 424{
85ac7ca5
MS
425 cpumask_t cpumask;
426 int cpu;
1da177e4 427
677d7623 428 /* Disable all interrupts/machine checks */
e258d719 429 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 430 trace_hardirqs_off();
1da177e4 431
3ab121ab 432 debug_set_critical();
85ac7ca5
MS
433 cpumask_copy(&cpumask, cpu_online_mask);
434 cpumask_clear_cpu(smp_processor_id(), &cpumask);
435
8b646bd7
MS
436 if (oops_in_progress)
437 smp_emergency_stop(&cpumask);
1da177e4 438
85ac7ca5
MS
439 /* stop all processors */
440 for_each_cpu(cpu, &cpumask) {
8b646bd7 441 struct pcpu *pcpu = pcpu_devices + cpu;
a9ae32c3 442 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 443 while (!pcpu_stopped(pcpu))
c6b5b847
HC
444 cpu_relax();
445 }
446}
447
1da177e4
LT
448/*
449 * This is the main routine where commands issued by other
450 * cpus are handled.
451 */
9acf73b7 452static void smp_handle_ext_call(void)
1da177e4 453{
39ce010d 454 unsigned long bits;
1da177e4 455
9acf73b7
HC
456 /* handle bit signal external calls */
457 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
458 if (test_bit(ec_stop_cpu, &bits))
459 smp_stop_cpu();
184748cc
PZ
460 if (test_bit(ec_schedule, &bits))
461 scheduler_ipi();
ca9fc75a
HC
462 if (test_bit(ec_call_function_single, &bits))
463 generic_smp_call_function_single_interrupt();
9acf73b7 464}
85ac7ca5 465
9acf73b7
HC
466static void do_ext_call_interrupt(struct ext_code ext_code,
467 unsigned int param32, unsigned long param64)
468{
469 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
470 smp_handle_ext_call();
1da177e4
LT
471}
472
630cd046 473void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
474{
475 int cpu;
476
630cd046 477 for_each_cpu(cpu, mask)
b6ed49e0 478 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
479}
480
481void arch_send_call_function_single_ipi(int cpu)
482{
8b646bd7 483 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
484}
485
1da177e4
LT
486/*
487 * this function sends a 'reschedule' IPI to another CPU.
488 * it goes straight through and wastes no time serializing
489 * anything. Worst case is that we lose a reschedule ...
490 */
491void smp_send_reschedule(int cpu)
492{
8b646bd7 493 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
494}
495
496/*
497 * parameter area for the set/clear control bit callbacks
498 */
94c12cc7 499struct ec_creg_mask_parms {
8b646bd7
MS
500 unsigned long orval;
501 unsigned long andval;
502 int cr;
94c12cc7 503};
1da177e4
LT
504
505/*
506 * callback for setting/clearing control bits
507 */
39ce010d
HC
508static void smp_ctl_bit_callback(void *info)
509{
94c12cc7 510 struct ec_creg_mask_parms *pp = info;
1da177e4 511 unsigned long cregs[16];
39ce010d 512
94c12cc7 513 __ctl_store(cregs, 0, 15);
8b646bd7 514 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 515 __ctl_load(cregs, 0, 15);
1da177e4
LT
516}
517
518/*
519 * Set a bit in a control register of all cpus
520 */
94c12cc7
MS
521void smp_ctl_set_bit(int cr, int bit)
522{
8b646bd7 523 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 524
15c8b6c1 525 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 526}
39ce010d 527EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
528
529/*
530 * Clear a bit in a control register of all cpus
531 */
94c12cc7
MS
532void smp_ctl_clear_bit(int cr, int bit)
533{
8b646bd7 534 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 535
15c8b6c1 536 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 537}
39ce010d 538EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 539
bf28a597 540#ifdef CONFIG_CRASH_DUMP
411ed322 541
1af135a1
HC
542int smp_store_status(int cpu)
543{
1a36a39e
MS
544 struct pcpu *pcpu = pcpu_devices + cpu;
545 unsigned long pa;
1af135a1 546
1a36a39e
MS
547 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
548 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
549 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1
HC
550 return -EIO;
551 if (!MACHINE_HAS_VX)
552 return 0;
1a36a39e
MS
553 pa = __pa(pcpu->lowcore->vector_save_area_addr);
554 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
555 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
556 return -EIO;
1af135a1
HC
557 return 0;
558}
559
10ad34bc
MS
560/*
561 * Collect CPU state of the previous, crashed system.
562 * There are four cases:
563 * 1) standard zfcp dump
564 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
565 * The state for all CPUs except the boot CPU needs to be collected
566 * with sigp stop-and-store-status. The boot CPU state is located in
567 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 568 * will copy the boot CPU state from the HSA.
10ad34bc
MS
569 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
570 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
571 * The state for all CPUs except the boot CPU needs to be collected
572 * with sigp stop-and-store-status. The firmware or the boot-loader
573 * stored the registers of the boot CPU in the absolute lowcore in the
574 * memory of the old system.
575 * 3) kdump and the old kernel did not store the CPU state,
576 * or stand-alone kdump for DASD
577 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
578 * The state for all CPUs except the boot CPU needs to be collected
579 * with sigp stop-and-store-status. The kexec code or the boot-loader
580 * stored the registers of the boot CPU in the memory of the old system.
581 * 4) kdump and the old kernel stored the CPU state
582 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
583 * This case does not exist for s390 anymore, setup_arch explicitly
584 * deactivates the elfcorehdr= kernel parameter
10ad34bc 585 */
1a2c5840 586static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
587 bool is_boot_cpu, unsigned long page)
588{
589 __vector128 *vxrs = (__vector128 *) page;
590
591 if (is_boot_cpu)
592 vxrs = boot_cpu_vector_save_area;
593 else
594 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 595 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
596}
597
1a2c5840 598static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
599 bool is_boot_cpu, unsigned long page)
600{
601 void *regs = (void *) page;
602
603 if (is_boot_cpu)
604 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
605 else
606 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 607 save_area_add_regs(sa, regs);
1a36a39e
MS
608}
609
1592a8e4 610void __init smp_save_dump_cpus(void)
10ad34bc 611{
1a2c5840
MS
612 int addr, boot_cpu_addr, max_cpu_addr;
613 struct save_area *sa;
1a36a39e 614 unsigned long page;
1592a8e4 615 bool is_boot_cpu;
10ad34bc 616
10ad34bc
MS
617 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
618 /* No previous system present, normal boot. */
619 return;
1a36a39e
MS
620 /* Allocate a page as dumping area for the store status sigps */
621 page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
10ad34bc 622 /* Set multi-threading state to the previous system. */
37c5f6c8 623 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 624 boot_cpu_addr = stap();
1a2c5840
MS
625 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
626 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 627 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
628 SIGP_CC_NOT_OPERATIONAL)
629 continue;
1592a8e4 630 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
631 /* Allocate save area */
632 sa = save_area_alloc(is_boot_cpu);
633 if (!sa)
634 panic("could not allocate memory for save area\n");
1a36a39e
MS
635 if (MACHINE_HAS_VX)
636 /* Get the vector registers */
1a2c5840 637 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
638 /*
639 * For a zfcp dump OLDMEM_BASE == NULL and the registers
640 * of the boot CPU are stored in the HSA. To retrieve
641 * these registers an SCLP request is required which is
642 * done by drivers/s390/char/zcore.c:init_cpu_info()
643 */
644 if (!is_boot_cpu || OLDMEM_BASE)
645 /* Get the CPU registers */
1a2c5840 646 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 647 }
1a36a39e 648 memblock_free(page, PAGE_SIZE);
1592a8e4
MH
649 diag308_reset();
650 pcpu_set_smt(0);
1af135a1 651}
1a36a39e 652#endif /* CONFIG_CRASH_DUMP */
08d07968 653
50ab9a9a
HC
654void smp_cpu_set_polarization(int cpu, int val)
655{
656 pcpu_devices[cpu].polarization = val;
657}
658
659int smp_cpu_get_polarization(int cpu)
660{
661 return pcpu_devices[cpu].polarization;
662}
663
af51160e 664static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 665{
8b646bd7 666 static int use_sigp_detection;
8b646bd7
MS
667 int address;
668
af51160e 669 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 670 use_sigp_detection = 1;
e7086eb1 671 for (address = 0;
d08d9430 672 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 673 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 674 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 675 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 676 continue;
d08d9430 677 info->core[info->configured].core_id =
10ad34bc 678 address >> smp_cpu_mt_shift;
8b646bd7
MS
679 info->configured++;
680 }
681 info->combined = info->configured;
08d07968 682 }
08d07968
HC
683}
684
e2741f17 685static int smp_add_present_cpu(int cpu);
8b646bd7 686
d08d9430 687static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 688{
8b646bd7 689 struct pcpu *pcpu;
08d07968 690 cpumask_t avail;
10ad34bc
MS
691 int cpu, nr, i, j;
692 u16 address;
08d07968 693
8b646bd7 694 nr = 0;
0f1959f5 695 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
696 cpu = cpumask_first(&avail);
697 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 698 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 699 continue;
d08d9430 700 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
701 for (j = 0; j <= smp_cpu_mtid; j++) {
702 if (pcpu_find_address(cpu_present_mask, address + j))
703 continue;
704 pcpu = pcpu_devices + cpu;
705 pcpu->address = address + j;
706 pcpu->state =
707 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
708 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
709 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
710 set_cpu_present(cpu, true);
711 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
712 set_cpu_present(cpu, false);
713 else
714 nr++;
715 cpu = cpumask_next(cpu, &avail);
716 if (cpu >= nr_cpu_ids)
717 break;
718 }
8b646bd7
MS
719 }
720 return nr;
1da177e4
LT
721}
722
af51160e 723void __init smp_detect_cpus(void)
48483b32 724{
10ad34bc 725 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 726 struct sclp_core_info *info;
10ad34bc 727 u16 address;
48483b32 728
10ad34bc 729 /* Get CPU information */
af51160e
HC
730 info = memblock_virt_alloc(sizeof(*info), 8);
731 smp_get_core_info(info, 1);
10ad34bc 732 /* Find boot CPU type */
d08d9430 733 if (sclp.has_core_type) {
10ad34bc
MS
734 address = stap();
735 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 736 if (info->core[cpu].core_id == address) {
10ad34bc 737 /* The boot cpu dictates the cpu type. */
d08d9430 738 boot_core_type = info->core[cpu].type;
10ad34bc
MS
739 break;
740 }
741 if (cpu >= info->combined)
742 panic("Could not find boot CPU type");
48483b32 743 }
10ad34bc 744
10ad34bc 745 /* Set multi-threading state for the current system */
d08d9430 746 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
747 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
748 pcpu_set_smt(mtid);
749
750 /* Print number of CPUs */
8b646bd7 751 c_cpus = s_cpus = 0;
48483b32 752 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
753 if (sclp.has_core_type &&
754 info->core[cpu].type != boot_core_type)
48483b32 755 continue;
10ad34bc
MS
756 if (cpu < info->configured)
757 c_cpus += smp_cpu_mtid + 1;
758 else
759 s_cpus += smp_cpu_mtid + 1;
48483b32 760 }
395d31d4 761 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
762
763 /* Add CPUs present at boot */
9d40d2e3 764 get_online_cpus();
8b646bd7 765 __smp_rescan_cpus(info, 0);
9d40d2e3 766 put_online_cpus();
af51160e 767 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
768}
769
1da177e4 770/*
39ce010d 771 * Activate a secondary processor.
1da177e4 772 */
e2741f17 773static void smp_start_secondary(void *cpuvoid)
1da177e4 774{
1aae0560 775 S390_lowcore.last_update_clock = get_tod_clock();
8b646bd7
MS
776 S390_lowcore.restart_stack = (unsigned long) restart_stack;
777 S390_lowcore.restart_fn = (unsigned long) do_restart;
778 S390_lowcore.restart_data = 0;
779 S390_lowcore.restart_source = -1UL;
780 restore_access_regs(S390_lowcore.access_regs_save_area);
781 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
e258d719 782 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
39ce010d 783 cpu_init();
5bfb5d69 784 preempt_disable();
39ce010d 785 init_cpu_timer();
b5f87f15 786 vtime_init();
29b08d2b 787 pfault_init();
e545a614 788 notify_cpu_starting(smp_processor_id());
0f1959f5 789 set_cpu_online(smp_processor_id(), true);
93f3b2ee 790 inc_irq_stat(CPU_RST);
1da177e4 791 local_irq_enable();
fc6d73d6 792 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
793}
794
1da177e4 795/* Upping and downing of CPUs */
e2741f17 796int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 797{
8b646bd7 798 struct pcpu *pcpu;
10ad34bc 799 int base, i, rc;
1da177e4 800
8b646bd7
MS
801 pcpu = pcpu_devices + cpu;
802 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 803 return -EIO;
5423145f 804 base = smp_get_base_cpu(cpu);
10ad34bc
MS
805 for (i = 0; i <= smp_cpu_mtid; i++) {
806 if (base + i < nr_cpu_ids)
807 if (cpu_online(base + i))
808 break;
809 }
810 /*
811 * If this is the first CPU of the core to get online
812 * do an initial CPU reset.
813 */
814 if (i > smp_cpu_mtid &&
815 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 816 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 817 return -EIO;
e80e7813 818
8b646bd7
MS
819 rc = pcpu_alloc_lowcore(pcpu, cpu);
820 if (rc)
821 return rc;
822 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 823 pcpu_attach_task(pcpu, tidle);
8b646bd7 824 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 825 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 826 while (!cpu_online(cpu))
1da177e4
LT
827 cpu_relax();
828 return 0;
829}
830
d80512f8 831static unsigned int setup_possible_cpus __initdata;
255acee7 832
d80512f8
HC
833static int __init _setup_possible_cpus(char *s)
834{
835 get_option(&s, &setup_possible_cpus);
37a33026
HC
836 return 0;
837}
d80512f8 838early_param("possible_cpus", _setup_possible_cpus);
37a33026 839
48483b32
HC
840#ifdef CONFIG_HOTPLUG_CPU
841
39ce010d 842int __cpu_disable(void)
1da177e4 843{
8b646bd7 844 unsigned long cregs[16];
1da177e4 845
9acf73b7
HC
846 /* Handle possible pending IPIs */
847 smp_handle_ext_call();
8b646bd7
MS
848 set_cpu_online(smp_processor_id(), false);
849 /* Disable pseudo page faults on this cpu. */
29b08d2b 850 pfault_fini();
8b646bd7
MS
851 /* Disable interrupt sources via control register. */
852 __ctl_store(cregs, 0, 15);
853 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
854 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
855 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
856 __ctl_load(cregs, 0, 15);
fe0f4976 857 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
858 return 0;
859}
860
39ce010d 861void __cpu_die(unsigned int cpu)
1da177e4 862{
8b646bd7
MS
863 struct pcpu *pcpu;
864
1da177e4 865 /* Wait until target cpu is down */
8b646bd7
MS
866 pcpu = pcpu_devices + cpu;
867 while (!pcpu_stopped(pcpu))
1da177e4 868 cpu_relax();
8b646bd7 869 pcpu_free_lowcore(pcpu);
1b948d6c 870 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 871 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
872}
873
b456d94a 874void __noreturn cpu_die(void)
1da177e4
LT
875{
876 idle_task_exit();
a9ae32c3 877 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 878 for (;;) ;
1da177e4
LT
879}
880
255acee7
HC
881#endif /* CONFIG_HOTPLUG_CPU */
882
d80512f8
HC
883void __init smp_fill_possible_mask(void)
884{
9747bc47 885 unsigned int possible, sclp_max, cpu;
d80512f8 886
3a9f3fe6
DH
887 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
888 sclp_max = min(smp_max_threads, sclp_max);
61282aff 889 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 890 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 891 possible = min(possible, sclp_max);
d80512f8
HC
892 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
893 set_cpu_possible(cpu, true);
894}
895
1da177e4
LT
896void __init smp_prepare_cpus(unsigned int max_cpus)
897{
39ce010d 898 /* request the 0x1201 emergency signal external interrupt */
1dad093b 899 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 900 panic("Couldn't request external interrupt 0x1201");
d98e19cc 901 /* request the 0x1202 external call external interrupt */
1dad093b 902 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 903 panic("Couldn't request external interrupt 0x1202");
1da177e4
LT
904}
905
ea1f4eec 906void __init smp_prepare_boot_cpu(void)
1da177e4 907{
8b646bd7
MS
908 struct pcpu *pcpu = pcpu_devices;
909
8b646bd7 910 pcpu->state = CPU_STATE_CONFIGURED;
10ad34bc 911 pcpu->address = stap();
c667aeac 912 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 913 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 914 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
8b646bd7
MS
915 set_cpu_present(0, true);
916 set_cpu_online(0, true);
1da177e4
LT
917}
918
ea1f4eec 919void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 920{
1da177e4
LT
921}
922
02beaccc
HC
923void __init smp_setup_processor_id(void)
924{
925 S390_lowcore.cpu_nr = 0;
6c8cd5bb 926 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
02beaccc
HC
927}
928
1da177e4
LT
929/*
930 * the frequency of the profiling timer can be changed
931 * by writing a multiplier value into /proc/profile.
932 *
933 * usually you want to run this on all CPUs ;)
934 */
935int setup_profiling_timer(unsigned int multiplier)
936{
39ce010d 937 return 0;
1da177e4
LT
938}
939
08d07968 940#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 941static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 942 struct device_attribute *attr, char *buf)
08d07968
HC
943{
944 ssize_t count;
945
946 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 947 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
948 mutex_unlock(&smp_cpu_state_mutex);
949 return count;
950}
951
8a25a2fd 952static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
953 struct device_attribute *attr,
954 const char *buf, size_t count)
08d07968 955{
8b646bd7 956 struct pcpu *pcpu;
10ad34bc 957 int cpu, val, rc, i;
08d07968
HC
958 char delim;
959
960 if (sscanf(buf, "%d %c", &val, &delim) != 1)
961 return -EINVAL;
962 if (val != 0 && val != 1)
963 return -EINVAL;
9d40d2e3 964 get_online_cpus();
0b18d318 965 mutex_lock(&smp_cpu_state_mutex);
08d07968 966 rc = -EBUSY;
2c2df118 967 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 968 cpu = dev->id;
5423145f 969 cpu = smp_get_base_cpu(cpu);
10ad34bc 970 if (cpu == 0)
08d07968 971 goto out;
10ad34bc
MS
972 for (i = 0; i <= smp_cpu_mtid; i++)
973 if (cpu_online(cpu + i))
974 goto out;
8b646bd7 975 pcpu = pcpu_devices + cpu;
08d07968
HC
976 rc = 0;
977 switch (val) {
978 case 0:
8b646bd7
MS
979 if (pcpu->state != CPU_STATE_CONFIGURED)
980 break;
d08d9430 981 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
982 if (rc)
983 break;
10ad34bc
MS
984 for (i = 0; i <= smp_cpu_mtid; i++) {
985 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
986 continue;
987 pcpu[i].state = CPU_STATE_STANDBY;
988 smp_cpu_set_polarization(cpu + i,
989 POLARIZATION_UNKNOWN);
990 }
8b646bd7 991 topology_expect_change();
08d07968
HC
992 break;
993 case 1:
8b646bd7
MS
994 if (pcpu->state != CPU_STATE_STANDBY)
995 break;
d08d9430 996 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
997 if (rc)
998 break;
10ad34bc
MS
999 for (i = 0; i <= smp_cpu_mtid; i++) {
1000 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1001 continue;
1002 pcpu[i].state = CPU_STATE_CONFIGURED;
1003 smp_cpu_set_polarization(cpu + i,
1004 POLARIZATION_UNKNOWN);
1005 }
8b646bd7 1006 topology_expect_change();
08d07968
HC
1007 break;
1008 default:
1009 break;
1010 }
1011out:
08d07968 1012 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1013 put_online_cpus();
08d07968
HC
1014 return rc ? rc : count;
1015}
8a25a2fd 1016static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968
HC
1017#endif /* CONFIG_HOTPLUG_CPU */
1018
8a25a2fd
KS
1019static ssize_t show_cpu_address(struct device *dev,
1020 struct device_attribute *attr, char *buf)
08d07968 1021{
8b646bd7 1022 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1023}
8a25a2fd 1024static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1025
08d07968
HC
1026static struct attribute *cpu_common_attrs[] = {
1027#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1028 &dev_attr_configure.attr,
08d07968 1029#endif
8a25a2fd 1030 &dev_attr_address.attr,
08d07968
HC
1031 NULL,
1032};
1033
1034static struct attribute_group cpu_common_attr_group = {
1035 .attrs = cpu_common_attrs,
1036};
1da177e4 1037
08d07968 1038static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1039 &dev_attr_idle_count.attr,
1040 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1041 NULL,
1042};
1043
08d07968
HC
1044static struct attribute_group cpu_online_attr_group = {
1045 .attrs = cpu_online_attrs,
fae8b22d
HC
1046};
1047
dfbbd86a 1048static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1049{
2f859d0d 1050 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1051
dfbbd86a
SAS
1052 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1053}
1054static int smp_cpu_pre_down(unsigned int cpu)
1055{
1056 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1057
1058 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1059 return 0;
2fc2d1e9
HC
1060}
1061
e2741f17 1062static int smp_add_present_cpu(int cpu)
08d07968 1063{
96619fc1
HC
1064 struct device *s;
1065 struct cpu *c;
08d07968
HC
1066 int rc;
1067
96619fc1
HC
1068 c = kzalloc(sizeof(*c), GFP_KERNEL);
1069 if (!c)
1070 return -ENOMEM;
2f859d0d 1071 per_cpu(cpu_device, cpu) = c;
96619fc1 1072 s = &c->dev;
08d07968
HC
1073 c->hotpluggable = 1;
1074 rc = register_cpu(c, cpu);
1075 if (rc)
1076 goto out;
1077 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1078 if (rc)
1079 goto out_cpu;
83a24e32
HC
1080 rc = topology_cpu_init(c);
1081 if (rc)
1082 goto out_topology;
1083 return 0;
1084
1085out_topology:
08d07968
HC
1086 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1087out_cpu:
1088#ifdef CONFIG_HOTPLUG_CPU
1089 unregister_cpu(c);
1090#endif
1091out:
1092 return rc;
1093}
1094
1095#ifdef CONFIG_HOTPLUG_CPU
1e489518 1096
67060d9c 1097int __ref smp_rescan_cpus(void)
08d07968 1098{
d08d9430 1099 struct sclp_core_info *info;
8b646bd7 1100 int nr;
08d07968 1101
af51160e 1102 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1103 if (!info)
1104 return -ENOMEM;
af51160e 1105 smp_get_core_info(info, 0);
9d40d2e3 1106 get_online_cpus();
0b18d318 1107 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1108 nr = __smp_rescan_cpus(info, 1);
08d07968 1109 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1110 put_online_cpus();
8b646bd7
MS
1111 kfree(info);
1112 if (nr)
c10fde0d 1113 topology_schedule_update();
8b646bd7 1114 return 0;
1e489518
HC
1115}
1116
8a25a2fd
KS
1117static ssize_t __ref rescan_store(struct device *dev,
1118 struct device_attribute *attr,
c9be0a36 1119 const char *buf,
1e489518
HC
1120 size_t count)
1121{
1122 int rc;
1123
1124 rc = smp_rescan_cpus();
08d07968
HC
1125 return rc ? rc : count;
1126}
8a25a2fd 1127static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
08d07968
HC
1128#endif /* CONFIG_HOTPLUG_CPU */
1129
83a24e32 1130static int __init s390_smp_init(void)
1da177e4 1131{
f4edbcd5 1132 int cpu, rc = 0;
2fc2d1e9 1133
08d07968 1134#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1135 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1136 if (rc)
1137 return rc;
1138#endif
1139 for_each_present_cpu(cpu) {
1140 rc = smp_add_present_cpu(cpu);
fae8b22d 1141 if (rc)
f4edbcd5 1142 goto out;
1da177e4 1143 }
f4edbcd5 1144
dfbbd86a
SAS
1145 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1146 smp_cpu_online, smp_cpu_pre_down);
f4edbcd5 1147out:
f4edbcd5 1148 return rc;
1da177e4 1149}
83a24e32 1150subsys_initcall(s390_smp_init);