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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Time of day based timer functions. |
3 | * | |
4 | * S390 version | |
d2fec595 | 5 | * Copyright IBM Corp. 1999, 2008 |
1da177e4 LT |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
9 | * | |
10 | * Derived from "arch/i386/kernel/time.c" | |
11 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
12 | */ | |
13 | ||
feab6501 MS |
14 | #define KMSG_COMPONENT "time" |
15 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
16 | ||
052ff461 | 17 | #include <linux/kernel_stat.h> |
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/interrupt.h> | |
750887de HC |
26 | #include <linux/cpu.h> |
27 | #include <linux/stop_machine.h> | |
1da177e4 | 28 | #include <linux/time.h> |
3fbacffb | 29 | #include <linux/device.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/profile.h> | |
35 | #include <linux/timex.h> | |
36 | #include <linux/notifier.h> | |
189374ae | 37 | #include <linux/timekeeper_internal.h> |
5a62b192 | 38 | #include <linux/clockchips.h> |
5a0e3ad6 | 39 | #include <linux/gfp.h> |
860dba45 | 40 | #include <linux/kprobes.h> |
1da177e4 LT |
41 | #include <asm/uaccess.h> |
42 | #include <asm/delay.h> | |
1da177e4 | 43 | #include <asm/div64.h> |
b020632e | 44 | #include <asm/vdso.h> |
1da177e4 | 45 | #include <asm/irq.h> |
5a489b98 | 46 | #include <asm/irq_regs.h> |
27f6b416 | 47 | #include <asm/vtimer.h> |
d54853ef | 48 | #include <asm/etr.h> |
a806170e | 49 | #include <asm/cio.h> |
638ad34a | 50 | #include "entry.h" |
1da177e4 LT |
51 | |
52 | /* change this if you have some constant time drift */ | |
53 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
54 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
55 | ||
b6112ccb | 56 | u64 sched_clock_base_cc = -1; /* Force to data section. */ |
05e7ff7d | 57 | EXPORT_SYMBOL_GPL(sched_clock_base_cc); |
b6112ccb | 58 | |
5a62b192 | 59 | static DEFINE_PER_CPU(struct clock_event_device, comparators); |
1da177e4 | 60 | |
1da177e4 LT |
61 | /* |
62 | * Scheduler clock - returns current time in nanosec units. | |
63 | */ | |
7a5388de | 64 | unsigned long long notrace sched_clock(void) |
1da177e4 | 65 | { |
1aae0560 | 66 | return tod_to_ns(get_tod_clock_monotonic()); |
1da177e4 | 67 | } |
7a5388de | 68 | NOKPROBE_SYMBOL(sched_clock); |
1da177e4 | 69 | |
32f65f27 JG |
70 | /* |
71 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
72 | */ | |
73 | unsigned long long monotonic_clock(void) | |
74 | { | |
75 | return sched_clock(); | |
76 | } | |
77 | EXPORT_SYMBOL(monotonic_clock); | |
78 | ||
689911c7 | 79 | void tod_to_timeval(__u64 todval, struct timespec64 *xt) |
1da177e4 LT |
80 | { |
81 | unsigned long long sec; | |
82 | ||
83 | sec = todval >> 12; | |
84 | do_div(sec, 1000000); | |
b1e2ba8d | 85 | xt->tv_sec = sec; |
1da177e4 | 86 | todval -= (sec * 1000000) << 12; |
b1e2ba8d | 87 | xt->tv_nsec = ((todval * 1000) >> 12); |
1da177e4 | 88 | } |
b592e89a | 89 | EXPORT_SYMBOL(tod_to_timeval); |
1da177e4 | 90 | |
5a62b192 | 91 | void clock_comparator_work(void) |
1da177e4 | 92 | { |
5a62b192 | 93 | struct clock_event_device *cd; |
1da177e4 | 94 | |
5a62b192 | 95 | S390_lowcore.clock_comparator = -1ULL; |
eb7e7d76 | 96 | cd = this_cpu_ptr(&comparators); |
5a62b192 | 97 | cd->event_handler(cd); |
1da177e4 LT |
98 | } |
99 | ||
1da177e4 | 100 | /* |
5a62b192 | 101 | * Fixup the clock comparator. |
1da177e4 | 102 | */ |
5a62b192 | 103 | static void fixup_clock_comparator(unsigned long long delta) |
1da177e4 | 104 | { |
5a62b192 HC |
105 | /* If nobody is waiting there's nothing to fix. */ |
106 | if (S390_lowcore.clock_comparator == -1ULL) | |
1da177e4 | 107 | return; |
5a62b192 HC |
108 | S390_lowcore.clock_comparator += delta; |
109 | set_clock_comparator(S390_lowcore.clock_comparator); | |
1da177e4 LT |
110 | } |
111 | ||
8adbf78e | 112 | static int s390_next_event(unsigned long delta, |
5a62b192 | 113 | struct clock_event_device *evt) |
1da177e4 | 114 | { |
8adbf78e | 115 | S390_lowcore.clock_comparator = get_tod_clock() + delta; |
5a62b192 HC |
116 | set_clock_comparator(S390_lowcore.clock_comparator); |
117 | return 0; | |
1da177e4 LT |
118 | } |
119 | ||
5a62b192 HC |
120 | static void s390_set_mode(enum clock_event_mode mode, |
121 | struct clock_event_device *evt) | |
1da177e4 | 122 | { |
d54853ef MS |
123 | } |
124 | ||
125 | /* | |
126 | * Set up lowcore and control register of the current cpu to | |
127 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
128 | */ |
129 | void init_cpu_timer(void) | |
130 | { | |
5a62b192 HC |
131 | struct clock_event_device *cd; |
132 | int cpu; | |
133 | ||
134 | S390_lowcore.clock_comparator = -1ULL; | |
135 | set_clock_comparator(S390_lowcore.clock_comparator); | |
136 | ||
137 | cpu = smp_processor_id(); | |
138 | cd = &per_cpu(comparators, cpu); | |
139 | cd->name = "comparator"; | |
8adbf78e | 140 | cd->features = CLOCK_EVT_FEAT_ONESHOT; |
5a62b192 HC |
141 | cd->mult = 16777; |
142 | cd->shift = 12; | |
143 | cd->min_delta_ns = 1; | |
144 | cd->max_delta_ns = LONG_MAX; | |
145 | cd->rating = 400; | |
320ab2b0 | 146 | cd->cpumask = cpumask_of(cpu); |
8adbf78e | 147 | cd->set_next_event = s390_next_event; |
5a62b192 HC |
148 | cd->set_mode = s390_set_mode; |
149 | ||
150 | clockevents_register_device(cd); | |
d54853ef MS |
151 | |
152 | /* Enable clock comparator timer interrupt. */ | |
153 | __ctl_set_bit(0,11); | |
154 | ||
d2fec595 | 155 | /* Always allow the timing alert external interrupt. */ |
d54853ef MS |
156 | __ctl_set_bit(0, 4); |
157 | } | |
158 | ||
fde15c3a | 159 | static void clock_comparator_interrupt(struct ext_code ext_code, |
f6649a7e MS |
160 | unsigned int param32, |
161 | unsigned long param64) | |
d54853ef | 162 | { |
420f42ec | 163 | inc_irq_stat(IRQEXT_CLK); |
d3d238c7 HC |
164 | if (S390_lowcore.clock_comparator == -1ULL) |
165 | set_clock_comparator(S390_lowcore.clock_comparator); | |
d54853ef MS |
166 | } |
167 | ||
d2fec595 MS |
168 | static void etr_timing_alert(struct etr_irq_parm *); |
169 | static void stp_timing_alert(struct stp_irq_parm *); | |
170 | ||
fde15c3a | 171 | static void timing_alert_interrupt(struct ext_code ext_code, |
f6649a7e | 172 | unsigned int param32, unsigned long param64) |
d2fec595 | 173 | { |
420f42ec | 174 | inc_irq_stat(IRQEXT_TLA); |
f6649a7e MS |
175 | if (param32 & 0x00c40000) |
176 | etr_timing_alert((struct etr_irq_parm *) ¶m32); | |
177 | if (param32 & 0x00038000) | |
178 | stp_timing_alert((struct stp_irq_parm *) ¶m32); | |
d2fec595 MS |
179 | } |
180 | ||
d54853ef | 181 | static void etr_reset(void); |
d2fec595 | 182 | static void stp_reset(void); |
d54853ef | 183 | |
689911c7 | 184 | void read_persistent_clock64(struct timespec64 *ts) |
d54853ef | 185 | { |
1aae0560 | 186 | tod_to_timeval(get_tod_clock() - TOD_UNIX_EPOCH, ts); |
1da177e4 | 187 | } |
d54853ef | 188 | |
689911c7 | 189 | void read_boot_clock64(struct timespec64 *ts) |
23970e38 MS |
190 | { |
191 | tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts); | |
1da177e4 LT |
192 | } |
193 | ||
8e19608e | 194 | static cycle_t read_tod_clock(struct clocksource *cs) |
dc64bef5 | 195 | { |
1aae0560 | 196 | return get_tod_clock(); |
dc64bef5 MS |
197 | } |
198 | ||
199 | static struct clocksource clocksource_tod = { | |
200 | .name = "tod", | |
d2cb0e6e | 201 | .rating = 400, |
dc64bef5 MS |
202 | .read = read_tod_clock, |
203 | .mask = -1ULL, | |
204 | .mult = 1000, | |
205 | .shift = 12, | |
cc02d809 | 206 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
207 | }; |
208 | ||
f1b82746 MS |
209 | struct clocksource * __init clocksource_default_clock(void) |
210 | { | |
211 | return &clocksource_tod; | |
212 | } | |
dc64bef5 | 213 | |
79c74ecb | 214 | void update_vsyscall(struct timekeeper *tk) |
b020632e | 215 | { |
79c74ecb MS |
216 | u64 nsecps; |
217 | ||
876e7881 | 218 | if (tk->tkr_mono.clock != &clocksource_tod) |
b020632e MS |
219 | return; |
220 | ||
221 | /* Make userspace gettimeofday spin until we're done. */ | |
222 | ++vdso_data->tb_update_count; | |
223 | smp_wmb(); | |
876e7881 | 224 | vdso_data->xtime_tod_stamp = tk->tkr_mono.cycle_last; |
79c74ecb | 225 | vdso_data->xtime_clock_sec = tk->xtime_sec; |
876e7881 | 226 | vdso_data->xtime_clock_nsec = tk->tkr_mono.xtime_nsec; |
79c74ecb MS |
227 | vdso_data->wtom_clock_sec = |
228 | tk->xtime_sec + tk->wall_to_monotonic.tv_sec; | |
876e7881 PZ |
229 | vdso_data->wtom_clock_nsec = tk->tkr_mono.xtime_nsec + |
230 | + ((u64) tk->wall_to_monotonic.tv_nsec << tk->tkr_mono.shift); | |
231 | nsecps = (u64) NSEC_PER_SEC << tk->tkr_mono.shift; | |
79c74ecb MS |
232 | while (vdso_data->wtom_clock_nsec >= nsecps) { |
233 | vdso_data->wtom_clock_nsec -= nsecps; | |
234 | vdso_data->wtom_clock_sec++; | |
235 | } | |
b7eacb59 MS |
236 | |
237 | vdso_data->xtime_coarse_sec = tk->xtime_sec; | |
238 | vdso_data->xtime_coarse_nsec = | |
876e7881 | 239 | (long)(tk->tkr_mono.xtime_nsec >> tk->tkr_mono.shift); |
b7eacb59 MS |
240 | vdso_data->wtom_coarse_sec = |
241 | vdso_data->xtime_coarse_sec + tk->wall_to_monotonic.tv_sec; | |
242 | vdso_data->wtom_coarse_nsec = | |
243 | vdso_data->xtime_coarse_nsec + tk->wall_to_monotonic.tv_nsec; | |
244 | while (vdso_data->wtom_coarse_nsec >= NSEC_PER_SEC) { | |
245 | vdso_data->wtom_coarse_nsec -= NSEC_PER_SEC; | |
246 | vdso_data->wtom_coarse_sec++; | |
247 | } | |
248 | ||
876e7881 PZ |
249 | vdso_data->tk_mult = tk->tkr_mono.mult; |
250 | vdso_data->tk_shift = tk->tkr_mono.shift; | |
b020632e MS |
251 | smp_wmb(); |
252 | ++vdso_data->tb_update_count; | |
253 | } | |
254 | ||
255 | extern struct timezone sys_tz; | |
256 | ||
257 | void update_vsyscall_tz(void) | |
258 | { | |
259 | /* Make userspace gettimeofday spin until we're done. */ | |
260 | ++vdso_data->tb_update_count; | |
261 | smp_wmb(); | |
262 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; | |
263 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
264 | smp_wmb(); | |
265 | ++vdso_data->tb_update_count; | |
266 | } | |
267 | ||
1da177e4 LT |
268 | /* |
269 | * Initialize the TOD clock and the CPU timer of | |
270 | * the boot cpu. | |
271 | */ | |
272 | void __init time_init(void) | |
273 | { | |
b6112ccb MS |
274 | /* Reset time synchronization interfaces. */ |
275 | etr_reset(); | |
276 | stp_reset(); | |
1da177e4 | 277 | |
1da177e4 | 278 | /* request the clock comparator external interrupt */ |
1dad093b TH |
279 | if (register_external_irq(EXT_IRQ_CLK_COMP, clock_comparator_interrupt)) |
280 | panic("Couldn't request external interrupt 0x1004"); | |
1da177e4 | 281 | |
d2fec595 | 282 | /* request the timing alert external interrupt */ |
1dad093b | 283 | if (register_external_irq(EXT_IRQ_TIMING_ALERT, timing_alert_interrupt)) |
d54853ef MS |
284 | panic("Couldn't request external interrupt 0x1406"); |
285 | ||
f8935983 | 286 | if (__clocksource_register(&clocksource_tod) != 0) |
ab96e798 MS |
287 | panic("Could not register TOD clock source"); |
288 | ||
d54853ef MS |
289 | /* Enable TOD clock interrupts on the boot cpu. */ |
290 | init_cpu_timer(); | |
ab96e798 | 291 | |
c185b783 | 292 | /* Enable cpu timer interrupts on the boot cpu. */ |
1da177e4 | 293 | vtime_init(); |
d54853ef MS |
294 | } |
295 | ||
d2fec595 MS |
296 | /* |
297 | * The time is "clock". old is what we think the time is. | |
298 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
299 | * "delay" is an approximation how long the synchronization took. If | |
300 | * the time correction is positive, then "delay" is subtracted from | |
301 | * the time difference and only the remaining part is passed to ntp. | |
302 | */ | |
303 | static unsigned long long adjust_time(unsigned long long old, | |
304 | unsigned long long clock, | |
305 | unsigned long long delay) | |
306 | { | |
307 | unsigned long long delta, ticks; | |
308 | struct timex adjust; | |
309 | ||
310 | if (clock > old) { | |
311 | /* It is later than we thought. */ | |
312 | delta = ticks = clock - old; | |
313 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
314 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
315 | adjust.offset = ticks * (1000000 / HZ); | |
316 | } else { | |
317 | /* It is earlier than we thought. */ | |
318 | delta = ticks = old - clock; | |
319 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
320 | delta = -delta; | |
321 | adjust.offset = -ticks * (1000000 / HZ); | |
322 | } | |
8107d829 | 323 | sched_clock_base_cc += delta; |
d2fec595 | 324 | if (adjust.offset != 0) { |
feab6501 MS |
325 | pr_notice("The ETR interface has adjusted the clock " |
326 | "by %li microseconds\n", adjust.offset); | |
d2fec595 MS |
327 | adjust.modes = ADJ_OFFSET_SINGLESHOT; |
328 | do_adjtimex(&adjust); | |
329 | } | |
330 | return delta; | |
331 | } | |
332 | ||
333 | static DEFINE_PER_CPU(atomic_t, clock_sync_word); | |
8283cb43 | 334 | static DEFINE_MUTEX(clock_sync_mutex); |
d2fec595 MS |
335 | static unsigned long clock_sync_flags; |
336 | ||
337 | #define CLOCK_SYNC_HAS_ETR 0 | |
338 | #define CLOCK_SYNC_HAS_STP 1 | |
339 | #define CLOCK_SYNC_ETR 2 | |
340 | #define CLOCK_SYNC_STP 3 | |
341 | ||
342 | /* | |
343 | * The synchronous get_clock function. It will write the current clock | |
344 | * value to the clock pointer and return 0 if the clock is in sync with | |
345 | * the external time source. If the clock mode is local it will return | |
a8f6db4d | 346 | * -EOPNOTSUPP and -EAGAIN if the clock is not in sync with the external |
d2fec595 MS |
347 | * reference. |
348 | */ | |
349 | int get_sync_clock(unsigned long long *clock) | |
350 | { | |
351 | atomic_t *sw_ptr; | |
352 | unsigned int sw0, sw1; | |
353 | ||
354 | sw_ptr = &get_cpu_var(clock_sync_word); | |
355 | sw0 = atomic_read(sw_ptr); | |
1aae0560 | 356 | *clock = get_tod_clock(); |
d2fec595 | 357 | sw1 = atomic_read(sw_ptr); |
bd119ee2 | 358 | put_cpu_var(clock_sync_word); |
d2fec595 MS |
359 | if (sw0 == sw1 && (sw0 & 0x80000000U)) |
360 | /* Success: time is in sync. */ | |
361 | return 0; | |
362 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) && | |
363 | !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
a8f6db4d | 364 | return -EOPNOTSUPP; |
d2fec595 MS |
365 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) && |
366 | !test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
367 | return -EACCES; | |
368 | return -EAGAIN; | |
369 | } | |
370 | EXPORT_SYMBOL(get_sync_clock); | |
371 | ||
372 | /* | |
373 | * Make get_sync_clock return -EAGAIN. | |
374 | */ | |
375 | static void disable_sync_clock(void *dummy) | |
376 | { | |
eb7e7d76 | 377 | atomic_t *sw_ptr = this_cpu_ptr(&clock_sync_word); |
d2fec595 MS |
378 | /* |
379 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
380 | * fail until the sync bit is turned back on. In addition | |
381 | * increase the "sequence" counter to avoid the race of an | |
382 | * etr event and the complete recovery against get_sync_clock. | |
383 | */ | |
384 | atomic_clear_mask(0x80000000, sw_ptr); | |
385 | atomic_inc(sw_ptr); | |
386 | } | |
387 | ||
388 | /* | |
389 | * Make get_sync_clock return 0 again. | |
390 | * Needs to be called from a context disabled for preemption. | |
391 | */ | |
392 | static void enable_sync_clock(void) | |
393 | { | |
eb7e7d76 | 394 | atomic_t *sw_ptr = this_cpu_ptr(&clock_sync_word); |
d2fec595 MS |
395 | atomic_set_mask(0x80000000, sw_ptr); |
396 | } | |
397 | ||
8283cb43 MS |
398 | /* |
399 | * Function to check if the clock is in sync. | |
400 | */ | |
401 | static inline int check_sync_clock(void) | |
402 | { | |
403 | atomic_t *sw_ptr; | |
404 | int rc; | |
405 | ||
406 | sw_ptr = &get_cpu_var(clock_sync_word); | |
407 | rc = (atomic_read(sw_ptr) & 0x80000000U) != 0; | |
bd119ee2 | 408 | put_cpu_var(clock_sync_word); |
8283cb43 MS |
409 | return rc; |
410 | } | |
411 | ||
750887de HC |
412 | /* Single threaded workqueue used for etr and stp sync events */ |
413 | static struct workqueue_struct *time_sync_wq; | |
414 | ||
415 | static void __init time_init_wq(void) | |
416 | { | |
179cb81a HC |
417 | if (time_sync_wq) |
418 | return; | |
419 | time_sync_wq = create_singlethread_workqueue("timesync"); | |
750887de HC |
420 | } |
421 | ||
d54853ef MS |
422 | /* |
423 | * External Time Reference (ETR) code. | |
424 | */ | |
425 | static int etr_port0_online; | |
426 | static int etr_port1_online; | |
d2fec595 | 427 | static int etr_steai_available; |
d54853ef MS |
428 | |
429 | static int __init early_parse_etr(char *p) | |
430 | { | |
431 | if (strncmp(p, "off", 3) == 0) | |
432 | etr_port0_online = etr_port1_online = 0; | |
433 | else if (strncmp(p, "port0", 5) == 0) | |
434 | etr_port0_online = 1; | |
435 | else if (strncmp(p, "port1", 5) == 0) | |
436 | etr_port1_online = 1; | |
437 | else if (strncmp(p, "on", 2) == 0) | |
438 | etr_port0_online = etr_port1_online = 1; | |
439 | return 0; | |
440 | } | |
441 | early_param("etr", early_parse_etr); | |
442 | ||
443 | enum etr_event { | |
444 | ETR_EVENT_PORT0_CHANGE, | |
445 | ETR_EVENT_PORT1_CHANGE, | |
446 | ETR_EVENT_PORT_ALERT, | |
447 | ETR_EVENT_SYNC_CHECK, | |
448 | ETR_EVENT_SWITCH_LOCAL, | |
449 | ETR_EVENT_UPDATE, | |
450 | }; | |
451 | ||
d54853ef MS |
452 | /* |
453 | * Valid bit combinations of the eacr register are (x = don't care): | |
454 | * e0 e1 dp p0 p1 ea es sl | |
455 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
456 | * 0 0 x 0 1 1 0 0 port 1 online | |
457 | * 0 0 x 1 0 1 0 0 port 0 online | |
458 | * 0 0 x 1 1 1 0 0 both ports online | |
459 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
460 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
461 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
462 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
463 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
464 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
465 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
466 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
467 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
468 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
469 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
470 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
471 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
472 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
473 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
474 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
475 | */ | |
476 | static struct etr_eacr etr_eacr; | |
477 | static u64 etr_tolec; /* time of last eacr update */ | |
d54853ef MS |
478 | static struct etr_aib etr_port0; |
479 | static int etr_port0_uptodate; | |
480 | static struct etr_aib etr_port1; | |
481 | static int etr_port1_uptodate; | |
482 | static unsigned long etr_events; | |
483 | static struct timer_list etr_timer; | |
d54853ef MS |
484 | |
485 | static void etr_timeout(unsigned long dummy); | |
ecdcc023 | 486 | static void etr_work_fn(struct work_struct *work); |
0b3016b7 | 487 | static DEFINE_MUTEX(etr_work_mutex); |
ecdcc023 | 488 | static DECLARE_WORK(etr_work, etr_work_fn); |
d54853ef | 489 | |
d54853ef MS |
490 | /* |
491 | * Reset ETR attachment. | |
492 | */ | |
493 | static void etr_reset(void) | |
494 | { | |
495 | etr_eacr = (struct etr_eacr) { | |
496 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
497 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
498 | .es = 0, .sl = 0 }; | |
d2fec595 | 499 | if (etr_setr(&etr_eacr) == 0) { |
1aae0560 | 500 | etr_tolec = get_tod_clock(); |
d2fec595 | 501 | set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags); |
8283cb43 MS |
502 | if (etr_port0_online && etr_port1_online) |
503 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d2fec595 | 504 | } else if (etr_port0_online || etr_port1_online) { |
feab6501 MS |
505 | pr_warning("The real or virtual hardware system does " |
506 | "not provide an ETR interface\n"); | |
d2fec595 | 507 | etr_port0_online = etr_port1_online = 0; |
d54853ef MS |
508 | } |
509 | } | |
510 | ||
ecdcc023 | 511 | static int __init etr_init(void) |
d54853ef MS |
512 | { |
513 | struct etr_aib aib; | |
514 | ||
d2fec595 | 515 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
ecdcc023 | 516 | return 0; |
750887de | 517 | time_init_wq(); |
d54853ef MS |
518 | /* Check if this machine has the steai instruction. */ |
519 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
d2fec595 | 520 | etr_steai_available = 1; |
d54853ef | 521 | setup_timer(&etr_timer, etr_timeout, 0UL); |
d54853ef MS |
522 | if (etr_port0_online) { |
523 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 524 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
525 | } |
526 | if (etr_port1_online) { | |
527 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 528 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 529 | } |
ecdcc023 | 530 | return 0; |
d54853ef MS |
531 | } |
532 | ||
ecdcc023 MS |
533 | arch_initcall(etr_init); |
534 | ||
d54853ef MS |
535 | /* |
536 | * Two sorts of ETR machine checks. The architecture reads: | |
537 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
538 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
539 | * disabled interruption request is indicated and is cleared". | |
540 | * Which means that we can get etr_switch_to_local events from the machine | |
541 | * check handler although the interruption condition is disabled. Lovely.. | |
542 | */ | |
543 | ||
544 | /* | |
545 | * Switch to local machine check. This is called when the last usable | |
546 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
547 | */ | |
548 | void etr_switch_to_local(void) | |
549 | { | |
550 | if (!etr_eacr.sl) | |
551 | return; | |
8283cb43 | 552 | disable_sync_clock(NULL); |
33fea794 MS |
553 | if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) { |
554 | etr_eacr.es = etr_eacr.sl = 0; | |
555 | etr_setr(&etr_eacr); | |
556 | queue_work(time_sync_wq, &etr_work); | |
557 | } | |
d54853ef MS |
558 | } |
559 | ||
560 | /* | |
561 | * ETR sync check machine check. This is called when the ETR OTE and the | |
562 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
563 | * After a ETR sync check the clock is not in sync. The machine check | |
564 | * is broadcasted to all cpus at the same time. | |
565 | */ | |
566 | void etr_sync_check(void) | |
567 | { | |
568 | if (!etr_eacr.es) | |
569 | return; | |
8283cb43 | 570 | disable_sync_clock(NULL); |
33fea794 MS |
571 | if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) { |
572 | etr_eacr.es = 0; | |
573 | etr_setr(&etr_eacr); | |
574 | queue_work(time_sync_wq, &etr_work); | |
575 | } | |
d54853ef MS |
576 | } |
577 | ||
578 | /* | |
d2fec595 | 579 | * ETR timing alert. There are two causes: |
d54853ef MS |
580 | * 1) port state change, check the usability of the port |
581 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
582 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
583 | * or ETR-data word 4 (edf4) has changed. | |
584 | */ | |
d2fec595 | 585 | static void etr_timing_alert(struct etr_irq_parm *intparm) |
d54853ef | 586 | { |
d54853ef MS |
587 | if (intparm->pc0) |
588 | /* ETR port 0 state change. */ | |
589 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
590 | if (intparm->pc1) | |
591 | /* ETR port 1 state change. */ | |
592 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
593 | if (intparm->eai) | |
594 | /* | |
595 | * ETR port alert on either port 0, 1 or both. | |
596 | * Both ports are not up-to-date now. | |
597 | */ | |
598 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
750887de | 599 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
600 | } |
601 | ||
602 | static void etr_timeout(unsigned long dummy) | |
603 | { | |
604 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
750887de | 605 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
606 | } |
607 | ||
608 | /* | |
609 | * Check if the etr mode is pss. | |
610 | */ | |
611 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
612 | { | |
613 | return eacr.es && !eacr.sl; | |
614 | } | |
615 | ||
616 | /* | |
617 | * Check if the etr mode is etr. | |
618 | */ | |
619 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
620 | { | |
621 | return eacr.es && eacr.sl; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Check if the port can be used for TOD synchronization. | |
626 | * For PPS mode the port has to receive OTEs. For ETR mode | |
627 | * the port has to receive OTEs, the ETR stepping bit has to | |
628 | * be zero and the validity bits for data frame 1, 2, and 3 | |
629 | * have to be 1. | |
630 | */ | |
631 | static int etr_port_valid(struct etr_aib *aib, int port) | |
632 | { | |
633 | unsigned int psc; | |
634 | ||
635 | /* Check that this port is receiving OTEs. */ | |
636 | if (aib->tsp == 0) | |
637 | return 0; | |
638 | ||
639 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
640 | if (psc == etr_lpsc_pps_mode) | |
641 | return 1; | |
642 | if (psc == etr_lpsc_operational_step) | |
643 | return !aib->esw.y && aib->slsw.v1 && | |
644 | aib->slsw.v2 && aib->slsw.v3; | |
645 | return 0; | |
646 | } | |
647 | ||
648 | /* | |
649 | * Check if two ports are on the same network. | |
650 | */ | |
651 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
652 | { | |
653 | // FIXME: any other fields we have to compare? | |
654 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
655 | } | |
656 | ||
657 | /* | |
658 | * Wrapper for etr_stei that converts physical port states | |
659 | * to logical port states to be consistent with the output | |
660 | * of stetr (see etr_psc vs. etr_lpsc). | |
661 | */ | |
662 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
663 | { | |
664 | BUG_ON(etr_steai(aib, func) != 0); | |
665 | /* Convert port state to logical port state. */ | |
666 | if (aib->esw.psc0 == 1) | |
667 | aib->esw.psc0 = 2; | |
668 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
669 | aib->esw.psc0 = 1; | |
670 | if (aib->esw.psc1 == 1) | |
671 | aib->esw.psc1 = 2; | |
672 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
673 | aib->esw.psc1 = 1; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Check if the aib a2 is still connected to the same attachment as | |
678 | * aib a1, the etv values differ by one and a2 is valid. | |
679 | */ | |
680 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
681 | { | |
682 | int state_a1, state_a2; | |
683 | ||
684 | /* Paranoia check: e0/e1 should better be the same. */ | |
685 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
686 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
687 | return 0; | |
688 | ||
689 | /* Still connected to the same etr ? */ | |
690 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
691 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
692 | if (state_a1 == etr_lpsc_operational_step) { | |
693 | if (state_a2 != etr_lpsc_operational_step || | |
694 | a1->edf1.net_id != a2->edf1.net_id || | |
695 | a1->edf1.etr_id != a2->edf1.etr_id || | |
696 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
697 | return 0; | |
698 | } else if (state_a2 != etr_lpsc_pps_mode) | |
699 | return 0; | |
700 | ||
701 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
702 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
703 | return 0; | |
704 | ||
705 | if (!etr_port_valid(a2, p)) | |
706 | return 0; | |
707 | ||
708 | return 1; | |
709 | } | |
710 | ||
d2fec595 | 711 | struct clock_sync_data { |
750887de | 712 | atomic_t cpus; |
5a62b192 HC |
713 | int in_sync; |
714 | unsigned long long fixup_cc; | |
750887de HC |
715 | int etr_port; |
716 | struct etr_aib *etr_aib; | |
d2fec595 | 717 | }; |
5a62b192 | 718 | |
750887de | 719 | static void clock_sync_cpu(struct clock_sync_data *sync) |
d54853ef | 720 | { |
750887de | 721 | atomic_dec(&sync->cpus); |
d2fec595 | 722 | enable_sync_clock(); |
d54853ef MS |
723 | /* |
724 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
725 | * is called on all other cpus while the TOD clocks is stopped. | |
726 | * __udelay will stop the cpu on an enabled wait psw until the | |
727 | * TOD is running again. | |
728 | */ | |
d2fec595 | 729 | while (sync->in_sync == 0) { |
d54853ef | 730 | __udelay(1); |
6c732de2 HC |
731 | /* |
732 | * A different cpu changes *in_sync. Therefore use | |
733 | * barrier() to force memory access. | |
734 | */ | |
735 | barrier(); | |
736 | } | |
d2fec595 | 737 | if (sync->in_sync != 1) |
d54853ef | 738 | /* Didn't work. Clear per-cpu in sync bit again. */ |
d2fec595 | 739 | disable_sync_clock(NULL); |
d54853ef MS |
740 | /* |
741 | * This round of TOD syncing is done. Set the clock comparator | |
742 | * to the next tick and let the processor continue. | |
743 | */ | |
d2fec595 | 744 | fixup_clock_comparator(sync->fixup_cc); |
d54853ef MS |
745 | } |
746 | ||
d54853ef | 747 | /* |
25985edc | 748 | * Sync the TOD clock using the port referred to by aibp. This port |
d54853ef MS |
749 | * has to be enabled and the other port has to be disabled. The |
750 | * last eacr update has to be more than 1.6 seconds in the past. | |
751 | */ | |
750887de | 752 | static int etr_sync_clock(void *data) |
d54853ef | 753 | { |
750887de | 754 | static int first; |
5a62b192 | 755 | unsigned long long clock, old_clock, delay, delta; |
750887de HC |
756 | struct clock_sync_data *etr_sync; |
757 | struct etr_aib *sync_port, *aib; | |
758 | int port; | |
d54853ef MS |
759 | int rc; |
760 | ||
750887de | 761 | etr_sync = data; |
d54853ef | 762 | |
750887de HC |
763 | if (xchg(&first, 1) == 1) { |
764 | /* Slave */ | |
765 | clock_sync_cpu(etr_sync); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | /* Wait until all other cpus entered the sync function. */ | |
770 | while (atomic_read(&etr_sync->cpus) != 0) | |
771 | cpu_relax(); | |
772 | ||
773 | port = etr_sync->etr_port; | |
774 | aib = etr_sync->etr_aib; | |
775 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
d2fec595 | 776 | enable_sync_clock(); |
d54853ef MS |
777 | |
778 | /* Set clock to next OTE. */ | |
779 | __ctl_set_bit(14, 21); | |
780 | __ctl_set_bit(0, 29); | |
781 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
1aae0560 HC |
782 | old_clock = get_tod_clock(); |
783 | if (set_tod_clock(clock) == 0) { | |
d54853ef MS |
784 | __udelay(1); /* Wait for the clock to start. */ |
785 | __ctl_clear_bit(0, 29); | |
786 | __ctl_clear_bit(14, 21); | |
787 | etr_stetr(aib); | |
788 | /* Adjust Linux timing variables. */ | |
789 | delay = (unsigned long long) | |
790 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
d2fec595 | 791 | delta = adjust_time(old_clock, clock, delay); |
750887de | 792 | etr_sync->fixup_cc = delta; |
5a62b192 | 793 | fixup_clock_comparator(delta); |
d54853ef MS |
794 | /* Verify that the clock is properly set. */ |
795 | if (!etr_aib_follows(sync_port, aib, port)) { | |
796 | /* Didn't work. */ | |
d2fec595 | 797 | disable_sync_clock(NULL); |
750887de | 798 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
799 | rc = -EAGAIN; |
800 | } else { | |
750887de | 801 | etr_sync->in_sync = 1; |
d54853ef MS |
802 | rc = 0; |
803 | } | |
804 | } else { | |
805 | /* Could not set the clock ?!? */ | |
806 | __ctl_clear_bit(0, 29); | |
807 | __ctl_clear_bit(14, 21); | |
d2fec595 | 808 | disable_sync_clock(NULL); |
750887de | 809 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
810 | rc = -EAGAIN; |
811 | } | |
750887de HC |
812 | xchg(&first, 0); |
813 | return rc; | |
814 | } | |
815 | ||
816 | static int etr_sync_clock_stop(struct etr_aib *aib, int port) | |
817 | { | |
818 | struct clock_sync_data etr_sync; | |
819 | struct etr_aib *sync_port; | |
820 | int follows; | |
821 | int rc; | |
822 | ||
823 | /* Check if the current aib is adjacent to the sync port aib. */ | |
824 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
825 | follows = etr_aib_follows(sync_port, aib, port); | |
826 | memcpy(sync_port, aib, sizeof(*aib)); | |
827 | if (!follows) | |
828 | return -EAGAIN; | |
829 | memset(&etr_sync, 0, sizeof(etr_sync)); | |
830 | etr_sync.etr_aib = aib; | |
831 | etr_sync.etr_port = port; | |
832 | get_online_cpus(); | |
833 | atomic_set(&etr_sync.cpus, num_online_cpus() - 1); | |
0f1959f5 | 834 | rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask); |
750887de | 835 | put_online_cpus(); |
d54853ef MS |
836 | return rc; |
837 | } | |
838 | ||
839 | /* | |
840 | * Handle the immediate effects of the different events. | |
841 | * The port change event is used for online/offline changes. | |
842 | */ | |
843 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
844 | { | |
845 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
846 | eacr.es = 0; | |
847 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
848 | eacr.es = eacr.sl = 0; | |
849 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
850 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
851 | ||
852 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
853 | if (eacr.e0) | |
854 | /* | |
855 | * Port change of an enabled port. We have to | |
856 | * assume that this can have caused an stepping | |
857 | * port switch. | |
858 | */ | |
1aae0560 | 859 | etr_tolec = get_tod_clock(); |
d54853ef MS |
860 | eacr.p0 = etr_port0_online; |
861 | if (!eacr.p0) | |
862 | eacr.e0 = 0; | |
863 | etr_port0_uptodate = 0; | |
864 | } | |
865 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
866 | if (eacr.e1) | |
867 | /* | |
868 | * Port change of an enabled port. We have to | |
869 | * assume that this can have caused an stepping | |
870 | * port switch. | |
871 | */ | |
1aae0560 | 872 | etr_tolec = get_tod_clock(); |
d54853ef MS |
873 | eacr.p1 = etr_port1_online; |
874 | if (!eacr.p1) | |
875 | eacr.e1 = 0; | |
876 | etr_port1_uptodate = 0; | |
877 | } | |
878 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
879 | return eacr; | |
880 | } | |
881 | ||
882 | /* | |
883 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
884 | * one of the ports needs an update. | |
885 | */ | |
886 | static void etr_set_tolec_timeout(unsigned long long now) | |
887 | { | |
888 | unsigned long micros; | |
889 | ||
890 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
891 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
892 | return; | |
893 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
894 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
895 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
896 | } | |
897 | ||
898 | /* | |
899 | * Set up a time that expires after 1/2 second. | |
900 | */ | |
901 | static void etr_set_sync_timeout(void) | |
902 | { | |
903 | mod_timer(&etr_timer, jiffies + HZ/2); | |
904 | } | |
905 | ||
906 | /* | |
907 | * Update the aib information for one or both ports. | |
908 | */ | |
909 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
910 | struct etr_eacr eacr) | |
911 | { | |
912 | /* With both ports disabled the aib information is useless. */ | |
913 | if (!eacr.e0 && !eacr.e1) | |
914 | return eacr; | |
915 | ||
ecdcc023 | 916 | /* Update port0 or port1 with aib stored in etr_work_fn. */ |
d54853ef MS |
917 | if (aib->esw.q == 0) { |
918 | /* Information for port 0 stored. */ | |
919 | if (eacr.p0 && !etr_port0_uptodate) { | |
920 | etr_port0 = *aib; | |
921 | if (etr_port0_online) | |
922 | etr_port0_uptodate = 1; | |
923 | } | |
924 | } else { | |
925 | /* Information for port 1 stored. */ | |
926 | if (eacr.p1 && !etr_port1_uptodate) { | |
927 | etr_port1 = *aib; | |
928 | if (etr_port0_online) | |
929 | etr_port1_uptodate = 1; | |
930 | } | |
931 | } | |
932 | ||
933 | /* | |
934 | * Do not try to get the alternate port aib if the clock | |
935 | * is not in sync yet. | |
936 | */ | |
33fea794 | 937 | if (!eacr.es || !check_sync_clock()) |
d54853ef MS |
938 | return eacr; |
939 | ||
940 | /* | |
941 | * If steai is available we can get the information about | |
942 | * the other port immediately. If only stetr is available the | |
943 | * data-port bit toggle has to be used. | |
944 | */ | |
d2fec595 | 945 | if (etr_steai_available) { |
d54853ef MS |
946 | if (eacr.p0 && !etr_port0_uptodate) { |
947 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
948 | etr_port0_uptodate = 1; | |
949 | } | |
950 | if (eacr.p1 && !etr_port1_uptodate) { | |
951 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
952 | etr_port1_uptodate = 1; | |
953 | } | |
954 | } else { | |
955 | /* | |
956 | * One port was updated above, if the other | |
957 | * port is not uptodate toggle dp bit. | |
958 | */ | |
959 | if ((eacr.p0 && !etr_port0_uptodate) || | |
960 | (eacr.p1 && !etr_port1_uptodate)) | |
961 | eacr.dp ^= 1; | |
962 | else | |
963 | eacr.dp = 0; | |
964 | } | |
965 | return eacr; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Write new etr control register if it differs from the current one. | |
970 | * Return 1 if etr_tolec has been updated as well. | |
971 | */ | |
972 | static void etr_update_eacr(struct etr_eacr eacr) | |
973 | { | |
974 | int dp_changed; | |
975 | ||
976 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
977 | /* No change, return. */ | |
978 | return; | |
979 | /* | |
980 | * The disable of an active port of the change of the data port | |
981 | * bit can/will cause a change in the data port. | |
982 | */ | |
983 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
984 | (etr_eacr.dp ^ eacr.dp) != 0; | |
985 | etr_eacr = eacr; | |
986 | etr_setr(&etr_eacr); | |
987 | if (dp_changed) | |
1aae0560 | 988 | etr_tolec = get_tod_clock(); |
d54853ef MS |
989 | } |
990 | ||
991 | /* | |
750887de | 992 | * ETR work. In this function you'll find the main logic. In |
d54853ef MS |
993 | * particular this is the only function that calls etr_update_eacr(), |
994 | * it "controls" the etr control register. | |
995 | */ | |
ecdcc023 | 996 | static void etr_work_fn(struct work_struct *work) |
d54853ef MS |
997 | { |
998 | unsigned long long now; | |
999 | struct etr_eacr eacr; | |
1000 | struct etr_aib aib; | |
1001 | int sync_port; | |
1002 | ||
0b3016b7 MS |
1003 | /* prevent multiple execution. */ |
1004 | mutex_lock(&etr_work_mutex); | |
1005 | ||
d54853ef MS |
1006 | /* Create working copy of etr_eacr. */ |
1007 | eacr = etr_eacr; | |
1008 | ||
1009 | /* Check for the different events and their immediate effects. */ | |
1010 | eacr = etr_handle_events(eacr); | |
1011 | ||
1012 | /* Check if ETR is supposed to be active. */ | |
1013 | eacr.ea = eacr.p0 || eacr.p1; | |
1014 | if (!eacr.ea) { | |
1015 | /* Both ports offline. Reset everything. */ | |
1016 | eacr.dp = eacr.es = eacr.sl = 0; | |
1a781a77 | 1017 | on_each_cpu(disable_sync_clock, NULL, 1); |
d54853ef MS |
1018 | del_timer_sync(&etr_timer); |
1019 | etr_update_eacr(eacr); | |
0b3016b7 | 1020 | goto out_unlock; |
d54853ef MS |
1021 | } |
1022 | ||
1023 | /* Store aib to get the current ETR status word. */ | |
1024 | BUG_ON(etr_stetr(&aib) != 0); | |
1025 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
1aae0560 | 1026 | now = get_tod_clock(); |
d54853ef MS |
1027 | |
1028 | /* | |
1029 | * Update the port information if the last stepping port change | |
1030 | * or data port change is older than 1.6 seconds. | |
1031 | */ | |
1032 | if (now >= etr_tolec + (1600000 << 12)) | |
1033 | eacr = etr_handle_update(&aib, eacr); | |
1034 | ||
1035 | /* | |
25985edc | 1036 | * Select ports to enable. The preferred synchronization mode is PPS. |
d54853ef MS |
1037 | * If a port can be enabled depends on a number of things: |
1038 | * 1) The port needs to be online and uptodate. A port is not | |
1039 | * disabled just because it is not uptodate, but it is only | |
1040 | * enabled if it is uptodate. | |
1041 | * 2) The port needs to have the same mode (pps / etr). | |
1042 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1043 | * 4) To enable the second port the clock needs to be in sync. | |
1044 | * 5) If both ports are useable and are ETR ports, the network id | |
1045 | * has to be the same. | |
1046 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1047 | */ | |
1048 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1049 | eacr.sl = 0; | |
1050 | eacr.e0 = 1; | |
1051 | if (!etr_mode_is_pps(etr_eacr)) | |
1052 | eacr.es = 0; | |
1053 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1054 | eacr.e1 = 0; | |
1055 | // FIXME: uptodate checks ? | |
1056 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1057 | eacr.e1 = 1; | |
1058 | sync_port = (etr_port0_uptodate && | |
1059 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1060 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { |
1061 | eacr.sl = 0; | |
1062 | eacr.e0 = 0; | |
1063 | eacr.e1 = 1; | |
1064 | if (!etr_mode_is_pps(etr_eacr)) | |
1065 | eacr.es = 0; | |
1066 | sync_port = (etr_port1_uptodate && | |
1067 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1068 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { |
1069 | eacr.sl = 1; | |
1070 | eacr.e0 = 1; | |
1071 | if (!etr_mode_is_etr(etr_eacr)) | |
1072 | eacr.es = 0; | |
1073 | if (!eacr.es || !eacr.p1 || | |
1074 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1075 | eacr.e1 = 0; | |
1076 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1077 | etr_compare_network(&etr_port0, &etr_port1)) | |
1078 | eacr.e1 = 1; | |
1079 | sync_port = (etr_port0_uptodate && | |
1080 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1081 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { |
1082 | eacr.sl = 1; | |
1083 | eacr.e0 = 0; | |
1084 | eacr.e1 = 1; | |
1085 | if (!etr_mode_is_etr(etr_eacr)) | |
1086 | eacr.es = 0; | |
1087 | sync_port = (etr_port1_uptodate && | |
1088 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1089 | } else { |
1090 | /* Both ports not usable. */ | |
1091 | eacr.es = eacr.sl = 0; | |
1092 | sync_port = -1; | |
d54853ef MS |
1093 | } |
1094 | ||
1095 | /* | |
1096 | * If the clock is in sync just update the eacr and return. | |
1097 | * If there is no valid sync port wait for a port update. | |
1098 | */ | |
33fea794 | 1099 | if ((eacr.es && check_sync_clock()) || sync_port < 0) { |
d54853ef MS |
1100 | etr_update_eacr(eacr); |
1101 | etr_set_tolec_timeout(now); | |
0b3016b7 | 1102 | goto out_unlock; |
d54853ef MS |
1103 | } |
1104 | ||
1105 | /* | |
1106 | * Prepare control register for clock syncing | |
1107 | * (reset data port bit, set sync check control. | |
1108 | */ | |
1109 | eacr.dp = 0; | |
1110 | eacr.es = 1; | |
1111 | ||
1112 | /* | |
1113 | * Update eacr and try to synchronize the clock. If the update | |
1114 | * of eacr caused a stepping port switch (or if we have to | |
25985edc | 1115 | * assume that a stepping port switch has occurred) or the |
d54853ef MS |
1116 | * clock syncing failed, reset the sync check control bit |
1117 | * and set up a timer to try again after 0.5 seconds | |
1118 | */ | |
1119 | etr_update_eacr(eacr); | |
1120 | if (now < etr_tolec + (1600000 << 12) || | |
750887de | 1121 | etr_sync_clock_stop(&aib, sync_port) != 0) { |
d54853ef MS |
1122 | /* Sync failed. Try again in 1/2 second. */ |
1123 | eacr.es = 0; | |
1124 | etr_update_eacr(eacr); | |
1125 | etr_set_sync_timeout(); | |
1126 | } else | |
1127 | etr_set_tolec_timeout(now); | |
0b3016b7 MS |
1128 | out_unlock: |
1129 | mutex_unlock(&etr_work_mutex); | |
d54853ef MS |
1130 | } |
1131 | ||
1132 | /* | |
1133 | * Sysfs interface functions | |
1134 | */ | |
3fbacffb KS |
1135 | static struct bus_type etr_subsys = { |
1136 | .name = "etr", | |
1137 | .dev_name = "etr", | |
d54853ef MS |
1138 | }; |
1139 | ||
3fbacffb | 1140 | static struct device etr_port0_dev = { |
d54853ef | 1141 | .id = 0, |
3fbacffb | 1142 | .bus = &etr_subsys, |
d54853ef MS |
1143 | }; |
1144 | ||
3fbacffb | 1145 | static struct device etr_port1_dev = { |
d54853ef | 1146 | .id = 1, |
3fbacffb | 1147 | .bus = &etr_subsys, |
d54853ef MS |
1148 | }; |
1149 | ||
1150 | /* | |
3fbacffb | 1151 | * ETR subsys attributes |
d54853ef | 1152 | */ |
3fbacffb KS |
1153 | static ssize_t etr_stepping_port_show(struct device *dev, |
1154 | struct device_attribute *attr, | |
c9be0a36 | 1155 | char *buf) |
d54853ef MS |
1156 | { |
1157 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1158 | } | |
1159 | ||
3fbacffb | 1160 | static DEVICE_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); |
d54853ef | 1161 | |
3fbacffb KS |
1162 | static ssize_t etr_stepping_mode_show(struct device *dev, |
1163 | struct device_attribute *attr, | |
c9be0a36 | 1164 | char *buf) |
d54853ef MS |
1165 | { |
1166 | char *mode_str; | |
1167 | ||
1168 | if (etr_mode_is_pps(etr_eacr)) | |
1169 | mode_str = "pps"; | |
1170 | else if (etr_mode_is_etr(etr_eacr)) | |
1171 | mode_str = "etr"; | |
1172 | else | |
1173 | mode_str = "local"; | |
1174 | return sprintf(buf, "%s\n", mode_str); | |
1175 | } | |
1176 | ||
3fbacffb | 1177 | static DEVICE_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); |
d54853ef MS |
1178 | |
1179 | /* | |
1180 | * ETR port attributes | |
1181 | */ | |
3fbacffb | 1182 | static inline struct etr_aib *etr_aib_from_dev(struct device *dev) |
d54853ef MS |
1183 | { |
1184 | if (dev == &etr_port0_dev) | |
1185 | return etr_port0_online ? &etr_port0 : NULL; | |
1186 | else | |
1187 | return etr_port1_online ? &etr_port1 : NULL; | |
1188 | } | |
1189 | ||
3fbacffb KS |
1190 | static ssize_t etr_online_show(struct device *dev, |
1191 | struct device_attribute *attr, | |
4a0b2b4d | 1192 | char *buf) |
d54853ef MS |
1193 | { |
1194 | unsigned int online; | |
1195 | ||
1196 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1197 | return sprintf(buf, "%i\n", online); | |
1198 | } | |
1199 | ||
3fbacffb KS |
1200 | static ssize_t etr_online_store(struct device *dev, |
1201 | struct device_attribute *attr, | |
4a0b2b4d | 1202 | const char *buf, size_t count) |
d54853ef MS |
1203 | { |
1204 | unsigned int value; | |
1205 | ||
1206 | value = simple_strtoul(buf, NULL, 0); | |
1207 | if (value != 0 && value != 1) | |
1208 | return -EINVAL; | |
d2fec595 MS |
1209 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
1210 | return -EOPNOTSUPP; | |
8283cb43 | 1211 | mutex_lock(&clock_sync_mutex); |
d54853ef MS |
1212 | if (dev == &etr_port0_dev) { |
1213 | if (etr_port0_online == value) | |
8283cb43 | 1214 | goto out; /* Nothing to do. */ |
d54853ef | 1215 | etr_port0_online = value; |
8283cb43 MS |
1216 | if (etr_port0_online && etr_port1_online) |
1217 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1218 | else | |
1219 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1220 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); |
750887de | 1221 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1222 | } else { |
1223 | if (etr_port1_online == value) | |
8283cb43 | 1224 | goto out; /* Nothing to do. */ |
d54853ef | 1225 | etr_port1_online = value; |
8283cb43 MS |
1226 | if (etr_port0_online && etr_port1_online) |
1227 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1228 | else | |
1229 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1230 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); |
750887de | 1231 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 1232 | } |
8283cb43 MS |
1233 | out: |
1234 | mutex_unlock(&clock_sync_mutex); | |
d54853ef MS |
1235 | return count; |
1236 | } | |
1237 | ||
3fbacffb | 1238 | static DEVICE_ATTR(online, 0600, etr_online_show, etr_online_store); |
d54853ef | 1239 | |
3fbacffb KS |
1240 | static ssize_t etr_stepping_control_show(struct device *dev, |
1241 | struct device_attribute *attr, | |
4a0b2b4d | 1242 | char *buf) |
d54853ef MS |
1243 | { |
1244 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1245 | etr_eacr.e0 : etr_eacr.e1); | |
1246 | } | |
1247 | ||
3fbacffb | 1248 | static DEVICE_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); |
d54853ef | 1249 | |
3fbacffb KS |
1250 | static ssize_t etr_mode_code_show(struct device *dev, |
1251 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1252 | { |
1253 | if (!etr_port0_online && !etr_port1_online) | |
1254 | /* Status word is not uptodate if both ports are offline. */ | |
1255 | return -ENODATA; | |
1256 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1257 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1258 | } | |
1259 | ||
3fbacffb | 1260 | static DEVICE_ATTR(state_code, 0400, etr_mode_code_show, NULL); |
d54853ef | 1261 | |
3fbacffb KS |
1262 | static ssize_t etr_untuned_show(struct device *dev, |
1263 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1264 | { |
1265 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1266 | ||
1267 | if (!aib || !aib->slsw.v1) | |
1268 | return -ENODATA; | |
1269 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1270 | } | |
1271 | ||
3fbacffb | 1272 | static DEVICE_ATTR(untuned, 0400, etr_untuned_show, NULL); |
d54853ef | 1273 | |
3fbacffb KS |
1274 | static ssize_t etr_network_id_show(struct device *dev, |
1275 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1276 | { |
1277 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1278 | ||
1279 | if (!aib || !aib->slsw.v1) | |
1280 | return -ENODATA; | |
1281 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1282 | } | |
1283 | ||
3fbacffb | 1284 | static DEVICE_ATTR(network, 0400, etr_network_id_show, NULL); |
d54853ef | 1285 | |
3fbacffb KS |
1286 | static ssize_t etr_id_show(struct device *dev, |
1287 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1288 | { |
1289 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1290 | ||
1291 | if (!aib || !aib->slsw.v1) | |
1292 | return -ENODATA; | |
1293 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1294 | } | |
1295 | ||
3fbacffb | 1296 | static DEVICE_ATTR(id, 0400, etr_id_show, NULL); |
d54853ef | 1297 | |
3fbacffb KS |
1298 | static ssize_t etr_port_number_show(struct device *dev, |
1299 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1300 | { |
1301 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1302 | ||
1303 | if (!aib || !aib->slsw.v1) | |
1304 | return -ENODATA; | |
1305 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1306 | } | |
1307 | ||
3fbacffb | 1308 | static DEVICE_ATTR(port, 0400, etr_port_number_show, NULL); |
d54853ef | 1309 | |
3fbacffb KS |
1310 | static ssize_t etr_coupled_show(struct device *dev, |
1311 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1312 | { |
1313 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1314 | ||
1315 | if (!aib || !aib->slsw.v3) | |
1316 | return -ENODATA; | |
1317 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1318 | } | |
1319 | ||
3fbacffb | 1320 | static DEVICE_ATTR(coupled, 0400, etr_coupled_show, NULL); |
d54853ef | 1321 | |
3fbacffb KS |
1322 | static ssize_t etr_local_time_show(struct device *dev, |
1323 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1324 | { |
1325 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1326 | ||
1327 | if (!aib || !aib->slsw.v3) | |
1328 | return -ENODATA; | |
1329 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1330 | } | |
1331 | ||
3fbacffb | 1332 | static DEVICE_ATTR(local_time, 0400, etr_local_time_show, NULL); |
d54853ef | 1333 | |
3fbacffb KS |
1334 | static ssize_t etr_utc_offset_show(struct device *dev, |
1335 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1336 | { |
1337 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1338 | ||
1339 | if (!aib || !aib->slsw.v3) | |
1340 | return -ENODATA; | |
1341 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1342 | } | |
1343 | ||
3fbacffb | 1344 | static DEVICE_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); |
d54853ef | 1345 | |
3fbacffb KS |
1346 | static struct device_attribute *etr_port_attributes[] = { |
1347 | &dev_attr_online, | |
1348 | &dev_attr_stepping_control, | |
1349 | &dev_attr_state_code, | |
1350 | &dev_attr_untuned, | |
1351 | &dev_attr_network, | |
1352 | &dev_attr_id, | |
1353 | &dev_attr_port, | |
1354 | &dev_attr_coupled, | |
1355 | &dev_attr_local_time, | |
1356 | &dev_attr_utc_offset, | |
d54853ef MS |
1357 | NULL |
1358 | }; | |
1359 | ||
3fbacffb | 1360 | static int __init etr_register_port(struct device *dev) |
d54853ef | 1361 | { |
3fbacffb | 1362 | struct device_attribute **attr; |
d54853ef MS |
1363 | int rc; |
1364 | ||
3fbacffb | 1365 | rc = device_register(dev); |
d54853ef MS |
1366 | if (rc) |
1367 | goto out; | |
1368 | for (attr = etr_port_attributes; *attr; attr++) { | |
3fbacffb | 1369 | rc = device_create_file(dev, *attr); |
d54853ef MS |
1370 | if (rc) |
1371 | goto out_unreg; | |
1372 | } | |
1373 | return 0; | |
1374 | out_unreg: | |
1375 | for (; attr >= etr_port_attributes; attr--) | |
3fbacffb KS |
1376 | device_remove_file(dev, *attr); |
1377 | device_unregister(dev); | |
d54853ef MS |
1378 | out: |
1379 | return rc; | |
1380 | } | |
1381 | ||
3fbacffb | 1382 | static void __init etr_unregister_port(struct device *dev) |
d54853ef | 1383 | { |
3fbacffb | 1384 | struct device_attribute **attr; |
d54853ef MS |
1385 | |
1386 | for (attr = etr_port_attributes; *attr; attr++) | |
3fbacffb KS |
1387 | device_remove_file(dev, *attr); |
1388 | device_unregister(dev); | |
d54853ef MS |
1389 | } |
1390 | ||
1391 | static int __init etr_init_sysfs(void) | |
1392 | { | |
1393 | int rc; | |
1394 | ||
3fbacffb | 1395 | rc = subsys_system_register(&etr_subsys, NULL); |
d54853ef MS |
1396 | if (rc) |
1397 | goto out; | |
3fbacffb | 1398 | rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_port); |
d54853ef | 1399 | if (rc) |
3fbacffb KS |
1400 | goto out_unreg_subsys; |
1401 | rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_mode); | |
d54853ef MS |
1402 | if (rc) |
1403 | goto out_remove_stepping_port; | |
1404 | rc = etr_register_port(&etr_port0_dev); | |
1405 | if (rc) | |
1406 | goto out_remove_stepping_mode; | |
1407 | rc = etr_register_port(&etr_port1_dev); | |
1408 | if (rc) | |
1409 | goto out_remove_port0; | |
1410 | return 0; | |
1411 | ||
1412 | out_remove_port0: | |
1413 | etr_unregister_port(&etr_port0_dev); | |
1414 | out_remove_stepping_mode: | |
3fbacffb | 1415 | device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_mode); |
d54853ef | 1416 | out_remove_stepping_port: |
3fbacffb KS |
1417 | device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_port); |
1418 | out_unreg_subsys: | |
1419 | bus_unregister(&etr_subsys); | |
d54853ef MS |
1420 | out: |
1421 | return rc; | |
1da177e4 LT |
1422 | } |
1423 | ||
d54853ef | 1424 | device_initcall(etr_init_sysfs); |
d2fec595 MS |
1425 | |
1426 | /* | |
1427 | * Server Time Protocol (STP) code. | |
1428 | */ | |
1429 | static int stp_online; | |
1430 | static struct stp_sstpi stp_info; | |
1431 | static void *stp_page; | |
1432 | ||
1433 | static void stp_work_fn(struct work_struct *work); | |
0b3016b7 | 1434 | static DEFINE_MUTEX(stp_work_mutex); |
d2fec595 | 1435 | static DECLARE_WORK(stp_work, stp_work_fn); |
04362301 | 1436 | static struct timer_list stp_timer; |
d2fec595 MS |
1437 | |
1438 | static int __init early_parse_stp(char *p) | |
1439 | { | |
1440 | if (strncmp(p, "off", 3) == 0) | |
1441 | stp_online = 0; | |
1442 | else if (strncmp(p, "on", 2) == 0) | |
1443 | stp_online = 1; | |
1444 | return 0; | |
1445 | } | |
1446 | early_param("stp", early_parse_stp); | |
1447 | ||
1448 | /* | |
1449 | * Reset STP attachment. | |
1450 | */ | |
8f847003 | 1451 | static void __init stp_reset(void) |
d2fec595 MS |
1452 | { |
1453 | int rc; | |
1454 | ||
d7d1104f | 1455 | stp_page = (void *) get_zeroed_page(GFP_ATOMIC); |
d2fec595 | 1456 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); |
4a672cfa | 1457 | if (rc == 0) |
d2fec595 MS |
1458 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
1459 | else if (stp_online) { | |
feab6501 MS |
1460 | pr_warning("The real or virtual hardware system does " |
1461 | "not provide an STP interface\n"); | |
d7d1104f | 1462 | free_page((unsigned long) stp_page); |
d2fec595 MS |
1463 | stp_page = NULL; |
1464 | stp_online = 0; | |
1465 | } | |
1466 | } | |
1467 | ||
04362301 MS |
1468 | static void stp_timeout(unsigned long dummy) |
1469 | { | |
1470 | queue_work(time_sync_wq, &stp_work); | |
1471 | } | |
1472 | ||
d2fec595 MS |
1473 | static int __init stp_init(void) |
1474 | { | |
750887de HC |
1475 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) |
1476 | return 0; | |
04362301 | 1477 | setup_timer(&stp_timer, stp_timeout, 0UL); |
750887de HC |
1478 | time_init_wq(); |
1479 | if (!stp_online) | |
1480 | return 0; | |
1481 | queue_work(time_sync_wq, &stp_work); | |
d2fec595 MS |
1482 | return 0; |
1483 | } | |
1484 | ||
1485 | arch_initcall(stp_init); | |
1486 | ||
1487 | /* | |
1488 | * STP timing alert. There are three causes: | |
1489 | * 1) timing status change | |
1490 | * 2) link availability change | |
1491 | * 3) time control parameter change | |
1492 | * In all three cases we are only interested in the clock source state. | |
1493 | * If a STP clock source is now available use it. | |
1494 | */ | |
1495 | static void stp_timing_alert(struct stp_irq_parm *intparm) | |
1496 | { | |
1497 | if (intparm->tsc || intparm->lac || intparm->tcpc) | |
750887de | 1498 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1499 | } |
1500 | ||
1501 | /* | |
1502 | * STP sync check machine check. This is called when the timing state | |
1503 | * changes from the synchronized state to the unsynchronized state. | |
1504 | * After a STP sync check the clock is not in sync. The machine check | |
1505 | * is broadcasted to all cpus at the same time. | |
1506 | */ | |
1507 | void stp_sync_check(void) | |
1508 | { | |
d2fec595 | 1509 | disable_sync_clock(NULL); |
750887de | 1510 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1511 | } |
1512 | ||
1513 | /* | |
1514 | * STP island condition machine check. This is called when an attached | |
1515 | * server attempts to communicate over an STP link and the servers | |
1516 | * have matching CTN ids and have a valid stratum-1 configuration | |
1517 | * but the configurations do not match. | |
1518 | */ | |
1519 | void stp_island_check(void) | |
1520 | { | |
d2fec595 | 1521 | disable_sync_clock(NULL); |
750887de | 1522 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1523 | } |
1524 | ||
750887de HC |
1525 | |
1526 | static int stp_sync_clock(void *data) | |
d2fec595 | 1527 | { |
750887de | 1528 | static int first; |
d2fec595 | 1529 | unsigned long long old_clock, delta; |
750887de | 1530 | struct clock_sync_data *stp_sync; |
d2fec595 MS |
1531 | int rc; |
1532 | ||
750887de | 1533 | stp_sync = data; |
d2fec595 | 1534 | |
750887de HC |
1535 | if (xchg(&first, 1) == 1) { |
1536 | /* Slave */ | |
1537 | clock_sync_cpu(stp_sync); | |
1538 | return 0; | |
1539 | } | |
d2fec595 | 1540 | |
750887de HC |
1541 | /* Wait until all other cpus entered the sync function. */ |
1542 | while (atomic_read(&stp_sync->cpus) != 0) | |
1543 | cpu_relax(); | |
d2fec595 | 1544 | |
d2fec595 MS |
1545 | enable_sync_clock(); |
1546 | ||
d2fec595 MS |
1547 | rc = 0; |
1548 | if (stp_info.todoff[0] || stp_info.todoff[1] || | |
1549 | stp_info.todoff[2] || stp_info.todoff[3] || | |
1550 | stp_info.tmd != 2) { | |
1aae0560 | 1551 | old_clock = get_tod_clock(); |
d2fec595 MS |
1552 | rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0); |
1553 | if (rc == 0) { | |
1aae0560 | 1554 | delta = adjust_time(old_clock, get_tod_clock(), 0); |
d2fec595 MS |
1555 | fixup_clock_comparator(delta); |
1556 | rc = chsc_sstpi(stp_page, &stp_info, | |
1557 | sizeof(struct stp_sstpi)); | |
1558 | if (rc == 0 && stp_info.tmd != 2) | |
1559 | rc = -EAGAIN; | |
1560 | } | |
1561 | } | |
1562 | if (rc) { | |
1563 | disable_sync_clock(NULL); | |
750887de | 1564 | stp_sync->in_sync = -EAGAIN; |
d2fec595 | 1565 | } else |
750887de HC |
1566 | stp_sync->in_sync = 1; |
1567 | xchg(&first, 0); | |
1568 | return 0; | |
1569 | } | |
d2fec595 | 1570 | |
750887de HC |
1571 | /* |
1572 | * STP work. Check for the STP state and take over the clock | |
1573 | * synchronization if the STP clock source is usable. | |
1574 | */ | |
1575 | static void stp_work_fn(struct work_struct *work) | |
1576 | { | |
1577 | struct clock_sync_data stp_sync; | |
1578 | int rc; | |
1579 | ||
0b3016b7 MS |
1580 | /* prevent multiple execution. */ |
1581 | mutex_lock(&stp_work_mutex); | |
1582 | ||
750887de HC |
1583 | if (!stp_online) { |
1584 | chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
04362301 | 1585 | del_timer_sync(&stp_timer); |
0b3016b7 | 1586 | goto out_unlock; |
750887de HC |
1587 | } |
1588 | ||
1589 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0); | |
1590 | if (rc) | |
0b3016b7 | 1591 | goto out_unlock; |
750887de HC |
1592 | |
1593 | rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi)); | |
1594 | if (rc || stp_info.c == 0) | |
0b3016b7 | 1595 | goto out_unlock; |
750887de | 1596 | |
8283cb43 MS |
1597 | /* Skip synchronization if the clock is already in sync. */ |
1598 | if (check_sync_clock()) | |
1599 | goto out_unlock; | |
1600 | ||
750887de HC |
1601 | memset(&stp_sync, 0, sizeof(stp_sync)); |
1602 | get_online_cpus(); | |
1603 | atomic_set(&stp_sync.cpus, num_online_cpus() - 1); | |
0f1959f5 | 1604 | stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask); |
750887de | 1605 | put_online_cpus(); |
0b3016b7 | 1606 | |
04362301 MS |
1607 | if (!check_sync_clock()) |
1608 | /* | |
1609 | * There is a usable clock but the synchonization failed. | |
1610 | * Retry after a second. | |
1611 | */ | |
1612 | mod_timer(&stp_timer, jiffies + HZ); | |
1613 | ||
0b3016b7 MS |
1614 | out_unlock: |
1615 | mutex_unlock(&stp_work_mutex); | |
d2fec595 MS |
1616 | } |
1617 | ||
1618 | /* | |
3fbacffb | 1619 | * STP subsys sysfs interface functions |
d2fec595 | 1620 | */ |
3fbacffb KS |
1621 | static struct bus_type stp_subsys = { |
1622 | .name = "stp", | |
1623 | .dev_name = "stp", | |
d2fec595 MS |
1624 | }; |
1625 | ||
3fbacffb KS |
1626 | static ssize_t stp_ctn_id_show(struct device *dev, |
1627 | struct device_attribute *attr, | |
c9be0a36 | 1628 | char *buf) |
d2fec595 MS |
1629 | { |
1630 | if (!stp_online) | |
1631 | return -ENODATA; | |
1632 | return sprintf(buf, "%016llx\n", | |
1633 | *(unsigned long long *) stp_info.ctnid); | |
1634 | } | |
1635 | ||
3fbacffb | 1636 | static DEVICE_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); |
d2fec595 | 1637 | |
3fbacffb KS |
1638 | static ssize_t stp_ctn_type_show(struct device *dev, |
1639 | struct device_attribute *attr, | |
c9be0a36 | 1640 | char *buf) |
d2fec595 MS |
1641 | { |
1642 | if (!stp_online) | |
1643 | return -ENODATA; | |
1644 | return sprintf(buf, "%i\n", stp_info.ctn); | |
1645 | } | |
1646 | ||
3fbacffb | 1647 | static DEVICE_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); |
d2fec595 | 1648 | |
3fbacffb KS |
1649 | static ssize_t stp_dst_offset_show(struct device *dev, |
1650 | struct device_attribute *attr, | |
c9be0a36 | 1651 | char *buf) |
d2fec595 MS |
1652 | { |
1653 | if (!stp_online || !(stp_info.vbits & 0x2000)) | |
1654 | return -ENODATA; | |
1655 | return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto); | |
1656 | } | |
1657 | ||
3fbacffb | 1658 | static DEVICE_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); |
d2fec595 | 1659 | |
3fbacffb KS |
1660 | static ssize_t stp_leap_seconds_show(struct device *dev, |
1661 | struct device_attribute *attr, | |
c9be0a36 | 1662 | char *buf) |
d2fec595 MS |
1663 | { |
1664 | if (!stp_online || !(stp_info.vbits & 0x8000)) | |
1665 | return -ENODATA; | |
1666 | return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps); | |
1667 | } | |
1668 | ||
3fbacffb | 1669 | static DEVICE_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); |
d2fec595 | 1670 | |
3fbacffb KS |
1671 | static ssize_t stp_stratum_show(struct device *dev, |
1672 | struct device_attribute *attr, | |
c9be0a36 | 1673 | char *buf) |
d2fec595 MS |
1674 | { |
1675 | if (!stp_online) | |
1676 | return -ENODATA; | |
1677 | return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum); | |
1678 | } | |
1679 | ||
3fbacffb | 1680 | static DEVICE_ATTR(stratum, 0400, stp_stratum_show, NULL); |
d2fec595 | 1681 | |
3fbacffb KS |
1682 | static ssize_t stp_time_offset_show(struct device *dev, |
1683 | struct device_attribute *attr, | |
c9be0a36 | 1684 | char *buf) |
d2fec595 MS |
1685 | { |
1686 | if (!stp_online || !(stp_info.vbits & 0x0800)) | |
1687 | return -ENODATA; | |
1688 | return sprintf(buf, "%i\n", (int) stp_info.tto); | |
1689 | } | |
1690 | ||
3fbacffb | 1691 | static DEVICE_ATTR(time_offset, 0400, stp_time_offset_show, NULL); |
d2fec595 | 1692 | |
3fbacffb KS |
1693 | static ssize_t stp_time_zone_offset_show(struct device *dev, |
1694 | struct device_attribute *attr, | |
c9be0a36 | 1695 | char *buf) |
d2fec595 MS |
1696 | { |
1697 | if (!stp_online || !(stp_info.vbits & 0x4000)) | |
1698 | return -ENODATA; | |
1699 | return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo); | |
1700 | } | |
1701 | ||
3fbacffb | 1702 | static DEVICE_ATTR(time_zone_offset, 0400, |
d2fec595 MS |
1703 | stp_time_zone_offset_show, NULL); |
1704 | ||
3fbacffb KS |
1705 | static ssize_t stp_timing_mode_show(struct device *dev, |
1706 | struct device_attribute *attr, | |
c9be0a36 | 1707 | char *buf) |
d2fec595 MS |
1708 | { |
1709 | if (!stp_online) | |
1710 | return -ENODATA; | |
1711 | return sprintf(buf, "%i\n", stp_info.tmd); | |
1712 | } | |
1713 | ||
3fbacffb | 1714 | static DEVICE_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); |
d2fec595 | 1715 | |
3fbacffb KS |
1716 | static ssize_t stp_timing_state_show(struct device *dev, |
1717 | struct device_attribute *attr, | |
c9be0a36 | 1718 | char *buf) |
d2fec595 MS |
1719 | { |
1720 | if (!stp_online) | |
1721 | return -ENODATA; | |
1722 | return sprintf(buf, "%i\n", stp_info.tst); | |
1723 | } | |
1724 | ||
3fbacffb | 1725 | static DEVICE_ATTR(timing_state, 0400, stp_timing_state_show, NULL); |
d2fec595 | 1726 | |
3fbacffb KS |
1727 | static ssize_t stp_online_show(struct device *dev, |
1728 | struct device_attribute *attr, | |
c9be0a36 | 1729 | char *buf) |
d2fec595 MS |
1730 | { |
1731 | return sprintf(buf, "%i\n", stp_online); | |
1732 | } | |
1733 | ||
3fbacffb KS |
1734 | static ssize_t stp_online_store(struct device *dev, |
1735 | struct device_attribute *attr, | |
d2fec595 MS |
1736 | const char *buf, size_t count) |
1737 | { | |
1738 | unsigned int value; | |
1739 | ||
1740 | value = simple_strtoul(buf, NULL, 0); | |
1741 | if (value != 0 && value != 1) | |
1742 | return -EINVAL; | |
1743 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
1744 | return -EOPNOTSUPP; | |
8283cb43 | 1745 | mutex_lock(&clock_sync_mutex); |
d2fec595 | 1746 | stp_online = value; |
8283cb43 MS |
1747 | if (stp_online) |
1748 | set_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
1749 | else | |
1750 | clear_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
750887de | 1751 | queue_work(time_sync_wq, &stp_work); |
8283cb43 | 1752 | mutex_unlock(&clock_sync_mutex); |
d2fec595 MS |
1753 | return count; |
1754 | } | |
1755 | ||
1756 | /* | |
3fbacffb KS |
1757 | * Can't use DEVICE_ATTR because the attribute should be named |
1758 | * stp/online but dev_attr_online already exists in this file .. | |
d2fec595 | 1759 | */ |
3fbacffb | 1760 | static struct device_attribute dev_attr_stp_online = { |
d2fec595 MS |
1761 | .attr = { .name = "online", .mode = 0600 }, |
1762 | .show = stp_online_show, | |
1763 | .store = stp_online_store, | |
1764 | }; | |
1765 | ||
3fbacffb KS |
1766 | static struct device_attribute *stp_attributes[] = { |
1767 | &dev_attr_ctn_id, | |
1768 | &dev_attr_ctn_type, | |
1769 | &dev_attr_dst_offset, | |
1770 | &dev_attr_leap_seconds, | |
1771 | &dev_attr_stp_online, | |
1772 | &dev_attr_stratum, | |
1773 | &dev_attr_time_offset, | |
1774 | &dev_attr_time_zone_offset, | |
1775 | &dev_attr_timing_mode, | |
1776 | &dev_attr_timing_state, | |
d2fec595 MS |
1777 | NULL |
1778 | }; | |
1779 | ||
1780 | static int __init stp_init_sysfs(void) | |
1781 | { | |
3fbacffb | 1782 | struct device_attribute **attr; |
d2fec595 MS |
1783 | int rc; |
1784 | ||
3fbacffb | 1785 | rc = subsys_system_register(&stp_subsys, NULL); |
d2fec595 MS |
1786 | if (rc) |
1787 | goto out; | |
1788 | for (attr = stp_attributes; *attr; attr++) { | |
3fbacffb | 1789 | rc = device_create_file(stp_subsys.dev_root, *attr); |
d2fec595 MS |
1790 | if (rc) |
1791 | goto out_unreg; | |
1792 | } | |
1793 | return 0; | |
1794 | out_unreg: | |
1795 | for (; attr >= stp_attributes; attr--) | |
3fbacffb KS |
1796 | device_remove_file(stp_subsys.dev_root, *attr); |
1797 | bus_unregister(&stp_subsys); | |
d2fec595 MS |
1798 | out: |
1799 | return rc; | |
1800 | } | |
1801 | ||
1802 | device_initcall(stp_init_sysfs); |