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[S390] cleanup lowcore access from program checks
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CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
feab6501
MS
15#define KMSG_COMPONENT "time"
16#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
17
1da177e4
LT
18#include <linux/errno.h>
19#include <linux/module.h>
20#include <linux/sched.h>
21#include <linux/kernel.h>
22#include <linux/param.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/interrupt.h>
750887de
HC
26#include <linux/cpu.h>
27#include <linux/stop_machine.h>
1da177e4 28#include <linux/time.h>
3367b994 29#include <linux/sysdev.h>
1da177e4
LT
30#include <linux/delay.h>
31#include <linux/init.h>
32#include <linux/smp.h>
33#include <linux/types.h>
34#include <linux/profile.h>
35#include <linux/timex.h>
36#include <linux/notifier.h>
dc64bef5 37#include <linux/clocksource.h>
5a62b192 38#include <linux/clockchips.h>
5a0e3ad6 39#include <linux/gfp.h>
1da177e4
LT
40#include <asm/uaccess.h>
41#include <asm/delay.h>
42#include <asm/s390_ext.h>
43#include <asm/div64.h>
b020632e 44#include <asm/vdso.h>
1da177e4 45#include <asm/irq.h>
5a489b98 46#include <asm/irq_regs.h>
1da177e4 47#include <asm/timer.h>
d54853ef 48#include <asm/etr.h>
a806170e 49#include <asm/cio.h>
1da177e4
LT
50
51/* change this if you have some constant time drift */
52#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
53#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
54
b6112ccb 55u64 sched_clock_base_cc = -1; /* Force to data section. */
05e7ff7d 56EXPORT_SYMBOL_GPL(sched_clock_base_cc);
b6112ccb 57
5a62b192 58static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 59
1da177e4
LT
60/*
61 * Scheduler clock - returns current time in nanosec units.
62 */
88dbd203 63unsigned long long notrace sched_clock(void)
1da177e4 64{
05e7ff7d 65 return (get_clock_monotonic() * 125) >> 9;
1da177e4
LT
66}
67
32f65f27
JG
68/*
69 * Monotonic_clock - returns # of nanoseconds passed since time_init()
70 */
71unsigned long long monotonic_clock(void)
72{
73 return sched_clock();
74}
75EXPORT_SYMBOL(monotonic_clock);
76
b1e2ba8d 77void tod_to_timeval(__u64 todval, struct timespec *xt)
1da177e4
LT
78{
79 unsigned long long sec;
80
81 sec = todval >> 12;
82 do_div(sec, 1000000);
b1e2ba8d 83 xt->tv_sec = sec;
1da177e4 84 todval -= (sec * 1000000) << 12;
b1e2ba8d 85 xt->tv_nsec = ((todval * 1000) >> 12);
1da177e4 86}
b592e89a 87EXPORT_SYMBOL(tod_to_timeval);
1da177e4 88
5a62b192 89void clock_comparator_work(void)
1da177e4 90{
5a62b192 91 struct clock_event_device *cd;
1da177e4 92
5a62b192
HC
93 S390_lowcore.clock_comparator = -1ULL;
94 set_clock_comparator(S390_lowcore.clock_comparator);
95 cd = &__get_cpu_var(comparators);
96 cd->event_handler(cd);
1da177e4
LT
97}
98
1da177e4 99/*
5a62b192 100 * Fixup the clock comparator.
1da177e4 101 */
5a62b192 102static void fixup_clock_comparator(unsigned long long delta)
1da177e4 103{
5a62b192
HC
104 /* If nobody is waiting there's nothing to fix. */
105 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 106 return;
5a62b192
HC
107 S390_lowcore.clock_comparator += delta;
108 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
109}
110
5a62b192
HC
111static int s390_next_event(unsigned long delta,
112 struct clock_event_device *evt)
1da177e4 113{
5a62b192
HC
114 S390_lowcore.clock_comparator = get_clock() + delta;
115 set_clock_comparator(S390_lowcore.clock_comparator);
116 return 0;
1da177e4
LT
117}
118
5a62b192
HC
119static void s390_set_mode(enum clock_event_mode mode,
120 struct clock_event_device *evt)
1da177e4 121{
d54853ef
MS
122}
123
124/*
125 * Set up lowcore and control register of the current cpu to
126 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
127 */
128void init_cpu_timer(void)
129{
5a62b192
HC
130 struct clock_event_device *cd;
131 int cpu;
132
133 S390_lowcore.clock_comparator = -1ULL;
134 set_clock_comparator(S390_lowcore.clock_comparator);
135
136 cpu = smp_processor_id();
137 cd = &per_cpu(comparators, cpu);
138 cd->name = "comparator";
139 cd->features = CLOCK_EVT_FEAT_ONESHOT;
140 cd->mult = 16777;
141 cd->shift = 12;
142 cd->min_delta_ns = 1;
143 cd->max_delta_ns = LONG_MAX;
144 cd->rating = 400;
320ab2b0 145 cd->cpumask = cpumask_of(cpu);
5a62b192
HC
146 cd->set_next_event = s390_next_event;
147 cd->set_mode = s390_set_mode;
148
149 clockevents_register_device(cd);
d54853ef
MS
150
151 /* Enable clock comparator timer interrupt. */
152 __ctl_set_bit(0,11);
153
d2fec595 154 /* Always allow the timing alert external interrupt. */
d54853ef
MS
155 __ctl_set_bit(0, 4);
156}
157
158static void clock_comparator_interrupt(__u16 code)
159{
d3d238c7
HC
160 if (S390_lowcore.clock_comparator == -1ULL)
161 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
162}
163
d2fec595
MS
164static void etr_timing_alert(struct etr_irq_parm *);
165static void stp_timing_alert(struct stp_irq_parm *);
166
167static void timing_alert_interrupt(__u16 code)
168{
169 if (S390_lowcore.ext_params & 0x00c40000)
170 etr_timing_alert((struct etr_irq_parm *)
171 &S390_lowcore.ext_params);
172 if (S390_lowcore.ext_params & 0x00038000)
173 stp_timing_alert((struct stp_irq_parm *)
174 &S390_lowcore.ext_params);
175}
176
d54853ef 177static void etr_reset(void);
d2fec595 178static void stp_reset(void);
d54853ef 179
d4f587c6 180void read_persistent_clock(struct timespec *ts)
d54853ef 181{
d4f587c6 182 tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, ts);
1da177e4 183}
d54853ef 184
23970e38
MS
185void read_boot_clock(struct timespec *ts)
186{
187 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts);
1da177e4
LT
188}
189
8e19608e 190static cycle_t read_tod_clock(struct clocksource *cs)
dc64bef5
MS
191{
192 return get_clock();
193}
194
195static struct clocksource clocksource_tod = {
196 .name = "tod",
d2cb0e6e 197 .rating = 400,
dc64bef5
MS
198 .read = read_tod_clock,
199 .mask = -1ULL,
200 .mult = 1000,
201 .shift = 12,
cc02d809 202 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
203};
204
f1b82746
MS
205struct clocksource * __init clocksource_default_clock(void)
206{
207 return &clocksource_tod;
208}
dc64bef5 209
7615856e
JS
210void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
211 struct clocksource *clock, u32 mult)
b020632e
MS
212{
213 if (clock != &clocksource_tod)
214 return;
215
216 /* Make userspace gettimeofday spin until we're done. */
217 ++vdso_data->tb_update_count;
218 smp_wmb();
219 vdso_data->xtime_tod_stamp = clock->cycle_last;
b1e2ba8d
JS
220 vdso_data->xtime_clock_sec = wall_time->tv_sec;
221 vdso_data->xtime_clock_nsec = wall_time->tv_nsec;
7615856e
JS
222 vdso_data->wtom_clock_sec = wtm->tv_sec;
223 vdso_data->wtom_clock_nsec = wtm->tv_nsec;
157a1a27 224 vdso_data->ntp_mult = mult;
b020632e
MS
225 smp_wmb();
226 ++vdso_data->tb_update_count;
227}
228
229extern struct timezone sys_tz;
230
231void update_vsyscall_tz(void)
232{
233 /* Make userspace gettimeofday spin until we're done. */
234 ++vdso_data->tb_update_count;
235 smp_wmb();
236 vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
237 vdso_data->tz_dsttime = sys_tz.tz_dsttime;
238 smp_wmb();
239 ++vdso_data->tb_update_count;
240}
241
1da177e4
LT
242/*
243 * Initialize the TOD clock and the CPU timer of
244 * the boot cpu.
245 */
246void __init time_init(void)
247{
b6112ccb
MS
248 /* Reset time synchronization interfaces. */
249 etr_reset();
250 stp_reset();
1da177e4 251
1da177e4 252 /* request the clock comparator external interrupt */
d7d1104f 253 if (register_external_interrupt(0x1004, clock_comparator_interrupt))
1da177e4
LT
254 panic("Couldn't request external interrupt 0x1004");
255
d2fec595 256 /* request the timing alert external interrupt */
d7d1104f 257 if (register_external_interrupt(0x1406, timing_alert_interrupt))
d54853ef
MS
258 panic("Couldn't request external interrupt 0x1406");
259
ab96e798
MS
260 if (clocksource_register(&clocksource_tod) != 0)
261 panic("Could not register TOD clock source");
262
d54853ef
MS
263 /* Enable TOD clock interrupts on the boot cpu. */
264 init_cpu_timer();
ab96e798 265
c185b783 266 /* Enable cpu timer interrupts on the boot cpu. */
1da177e4 267 vtime_init();
d54853ef
MS
268}
269
d2fec595
MS
270/*
271 * The time is "clock". old is what we think the time is.
272 * Adjust the value by a multiple of jiffies and add the delta to ntp.
273 * "delay" is an approximation how long the synchronization took. If
274 * the time correction is positive, then "delay" is subtracted from
275 * the time difference and only the remaining part is passed to ntp.
276 */
277static unsigned long long adjust_time(unsigned long long old,
278 unsigned long long clock,
279 unsigned long long delay)
280{
281 unsigned long long delta, ticks;
282 struct timex adjust;
283
284 if (clock > old) {
285 /* It is later than we thought. */
286 delta = ticks = clock - old;
287 delta = ticks = (delta < delay) ? 0 : delta - delay;
288 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
289 adjust.offset = ticks * (1000000 / HZ);
290 } else {
291 /* It is earlier than we thought. */
292 delta = ticks = old - clock;
293 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
294 delta = -delta;
295 adjust.offset = -ticks * (1000000 / HZ);
296 }
8107d829 297 sched_clock_base_cc += delta;
d2fec595 298 if (adjust.offset != 0) {
feab6501
MS
299 pr_notice("The ETR interface has adjusted the clock "
300 "by %li microseconds\n", adjust.offset);
d2fec595
MS
301 adjust.modes = ADJ_OFFSET_SINGLESHOT;
302 do_adjtimex(&adjust);
303 }
304 return delta;
305}
306
307static DEFINE_PER_CPU(atomic_t, clock_sync_word);
8283cb43 308static DEFINE_MUTEX(clock_sync_mutex);
d2fec595
MS
309static unsigned long clock_sync_flags;
310
311#define CLOCK_SYNC_HAS_ETR 0
312#define CLOCK_SYNC_HAS_STP 1
313#define CLOCK_SYNC_ETR 2
314#define CLOCK_SYNC_STP 3
315
316/*
317 * The synchronous get_clock function. It will write the current clock
318 * value to the clock pointer and return 0 if the clock is in sync with
319 * the external time source. If the clock mode is local it will return
320 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
321 * reference.
322 */
323int get_sync_clock(unsigned long long *clock)
324{
325 atomic_t *sw_ptr;
326 unsigned int sw0, sw1;
327
328 sw_ptr = &get_cpu_var(clock_sync_word);
329 sw0 = atomic_read(sw_ptr);
330 *clock = get_clock();
331 sw1 = atomic_read(sw_ptr);
bd119ee2 332 put_cpu_var(clock_sync_word);
d2fec595
MS
333 if (sw0 == sw1 && (sw0 & 0x80000000U))
334 /* Success: time is in sync. */
335 return 0;
336 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
337 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
338 return -ENOSYS;
339 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
340 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
341 return -EACCES;
342 return -EAGAIN;
343}
344EXPORT_SYMBOL(get_sync_clock);
345
346/*
347 * Make get_sync_clock return -EAGAIN.
348 */
349static void disable_sync_clock(void *dummy)
350{
351 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
352 /*
353 * Clear the in-sync bit 2^31. All get_sync_clock calls will
354 * fail until the sync bit is turned back on. In addition
355 * increase the "sequence" counter to avoid the race of an
356 * etr event and the complete recovery against get_sync_clock.
357 */
358 atomic_clear_mask(0x80000000, sw_ptr);
359 atomic_inc(sw_ptr);
360}
361
362/*
363 * Make get_sync_clock return 0 again.
364 * Needs to be called from a context disabled for preemption.
365 */
366static void enable_sync_clock(void)
367{
368 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
369 atomic_set_mask(0x80000000, sw_ptr);
370}
371
8283cb43
MS
372/*
373 * Function to check if the clock is in sync.
374 */
375static inline int check_sync_clock(void)
376{
377 atomic_t *sw_ptr;
378 int rc;
379
380 sw_ptr = &get_cpu_var(clock_sync_word);
381 rc = (atomic_read(sw_ptr) & 0x80000000U) != 0;
bd119ee2 382 put_cpu_var(clock_sync_word);
8283cb43
MS
383 return rc;
384}
385
750887de
HC
386/* Single threaded workqueue used for etr and stp sync events */
387static struct workqueue_struct *time_sync_wq;
388
389static void __init time_init_wq(void)
390{
179cb81a
HC
391 if (time_sync_wq)
392 return;
393 time_sync_wq = create_singlethread_workqueue("timesync");
750887de
HC
394}
395
d54853ef
MS
396/*
397 * External Time Reference (ETR) code.
398 */
399static int etr_port0_online;
400static int etr_port1_online;
d2fec595 401static int etr_steai_available;
d54853ef
MS
402
403static int __init early_parse_etr(char *p)
404{
405 if (strncmp(p, "off", 3) == 0)
406 etr_port0_online = etr_port1_online = 0;
407 else if (strncmp(p, "port0", 5) == 0)
408 etr_port0_online = 1;
409 else if (strncmp(p, "port1", 5) == 0)
410 etr_port1_online = 1;
411 else if (strncmp(p, "on", 2) == 0)
412 etr_port0_online = etr_port1_online = 1;
413 return 0;
414}
415early_param("etr", early_parse_etr);
416
417enum etr_event {
418 ETR_EVENT_PORT0_CHANGE,
419 ETR_EVENT_PORT1_CHANGE,
420 ETR_EVENT_PORT_ALERT,
421 ETR_EVENT_SYNC_CHECK,
422 ETR_EVENT_SWITCH_LOCAL,
423 ETR_EVENT_UPDATE,
424};
425
d54853ef
MS
426/*
427 * Valid bit combinations of the eacr register are (x = don't care):
428 * e0 e1 dp p0 p1 ea es sl
429 * 0 0 x 0 0 0 0 0 initial, disabled state
430 * 0 0 x 0 1 1 0 0 port 1 online
431 * 0 0 x 1 0 1 0 0 port 0 online
432 * 0 0 x 1 1 1 0 0 both ports online
433 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
434 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
435 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
436 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
437 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
438 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
439 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
440 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
441 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
442 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
443 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
444 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
445 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
446 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
447 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
448 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
449 */
450static struct etr_eacr etr_eacr;
451static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
452static struct etr_aib etr_port0;
453static int etr_port0_uptodate;
454static struct etr_aib etr_port1;
455static int etr_port1_uptodate;
456static unsigned long etr_events;
457static struct timer_list etr_timer;
d54853ef
MS
458
459static void etr_timeout(unsigned long dummy);
ecdcc023 460static void etr_work_fn(struct work_struct *work);
0b3016b7 461static DEFINE_MUTEX(etr_work_mutex);
ecdcc023 462static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 463
d54853ef
MS
464/*
465 * Reset ETR attachment.
466 */
467static void etr_reset(void)
468{
469 etr_eacr = (struct etr_eacr) {
470 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
471 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
472 .es = 0, .sl = 0 };
d2fec595 473 if (etr_setr(&etr_eacr) == 0) {
d54853ef 474 etr_tolec = get_clock();
d2fec595 475 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
8283cb43
MS
476 if (etr_port0_online && etr_port1_online)
477 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d2fec595 478 } else if (etr_port0_online || etr_port1_online) {
feab6501
MS
479 pr_warning("The real or virtual hardware system does "
480 "not provide an ETR interface\n");
d2fec595 481 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
482 }
483}
484
ecdcc023 485static int __init etr_init(void)
d54853ef
MS
486{
487 struct etr_aib aib;
488
d2fec595 489 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 490 return 0;
750887de 491 time_init_wq();
d54853ef
MS
492 /* Check if this machine has the steai instruction. */
493 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 494 etr_steai_available = 1;
d54853ef 495 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
496 if (etr_port0_online) {
497 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 498 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
499 }
500 if (etr_port1_online) {
501 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 502 queue_work(time_sync_wq, &etr_work);
d54853ef 503 }
ecdcc023 504 return 0;
d54853ef
MS
505}
506
ecdcc023
MS
507arch_initcall(etr_init);
508
d54853ef
MS
509/*
510 * Two sorts of ETR machine checks. The architecture reads:
511 * "When a machine-check niterruption occurs and if a switch-to-local or
512 * ETR-sync-check interrupt request is pending but disabled, this pending
513 * disabled interruption request is indicated and is cleared".
514 * Which means that we can get etr_switch_to_local events from the machine
515 * check handler although the interruption condition is disabled. Lovely..
516 */
517
518/*
519 * Switch to local machine check. This is called when the last usable
520 * ETR port goes inactive. After switch to local the clock is not in sync.
521 */
522void etr_switch_to_local(void)
523{
524 if (!etr_eacr.sl)
525 return;
8283cb43 526 disable_sync_clock(NULL);
33fea794
MS
527 if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) {
528 etr_eacr.es = etr_eacr.sl = 0;
529 etr_setr(&etr_eacr);
530 queue_work(time_sync_wq, &etr_work);
531 }
d54853ef
MS
532}
533
534/*
535 * ETR sync check machine check. This is called when the ETR OTE and the
536 * local clock OTE are farther apart than the ETR sync check tolerance.
537 * After a ETR sync check the clock is not in sync. The machine check
538 * is broadcasted to all cpus at the same time.
539 */
540void etr_sync_check(void)
541{
542 if (!etr_eacr.es)
543 return;
8283cb43 544 disable_sync_clock(NULL);
33fea794
MS
545 if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) {
546 etr_eacr.es = 0;
547 etr_setr(&etr_eacr);
548 queue_work(time_sync_wq, &etr_work);
549 }
d54853ef
MS
550}
551
552/*
d2fec595 553 * ETR timing alert. There are two causes:
d54853ef
MS
554 * 1) port state change, check the usability of the port
555 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
556 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
557 * or ETR-data word 4 (edf4) has changed.
558 */
d2fec595 559static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 560{
d54853ef
MS
561 if (intparm->pc0)
562 /* ETR port 0 state change. */
563 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
564 if (intparm->pc1)
565 /* ETR port 1 state change. */
566 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
567 if (intparm->eai)
568 /*
569 * ETR port alert on either port 0, 1 or both.
570 * Both ports are not up-to-date now.
571 */
572 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
750887de 573 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
574}
575
576static void etr_timeout(unsigned long dummy)
577{
578 set_bit(ETR_EVENT_UPDATE, &etr_events);
750887de 579 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
580}
581
582/*
583 * Check if the etr mode is pss.
584 */
585static inline int etr_mode_is_pps(struct etr_eacr eacr)
586{
587 return eacr.es && !eacr.sl;
588}
589
590/*
591 * Check if the etr mode is etr.
592 */
593static inline int etr_mode_is_etr(struct etr_eacr eacr)
594{
595 return eacr.es && eacr.sl;
596}
597
598/*
599 * Check if the port can be used for TOD synchronization.
600 * For PPS mode the port has to receive OTEs. For ETR mode
601 * the port has to receive OTEs, the ETR stepping bit has to
602 * be zero and the validity bits for data frame 1, 2, and 3
603 * have to be 1.
604 */
605static int etr_port_valid(struct etr_aib *aib, int port)
606{
607 unsigned int psc;
608
609 /* Check that this port is receiving OTEs. */
610 if (aib->tsp == 0)
611 return 0;
612
613 psc = port ? aib->esw.psc1 : aib->esw.psc0;
614 if (psc == etr_lpsc_pps_mode)
615 return 1;
616 if (psc == etr_lpsc_operational_step)
617 return !aib->esw.y && aib->slsw.v1 &&
618 aib->slsw.v2 && aib->slsw.v3;
619 return 0;
620}
621
622/*
623 * Check if two ports are on the same network.
624 */
625static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
626{
627 // FIXME: any other fields we have to compare?
628 return aib1->edf1.net_id == aib2->edf1.net_id;
629}
630
631/*
632 * Wrapper for etr_stei that converts physical port states
633 * to logical port states to be consistent with the output
634 * of stetr (see etr_psc vs. etr_lpsc).
635 */
636static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
637{
638 BUG_ON(etr_steai(aib, func) != 0);
639 /* Convert port state to logical port state. */
640 if (aib->esw.psc0 == 1)
641 aib->esw.psc0 = 2;
642 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
643 aib->esw.psc0 = 1;
644 if (aib->esw.psc1 == 1)
645 aib->esw.psc1 = 2;
646 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
647 aib->esw.psc1 = 1;
648}
649
650/*
651 * Check if the aib a2 is still connected to the same attachment as
652 * aib a1, the etv values differ by one and a2 is valid.
653 */
654static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
655{
656 int state_a1, state_a2;
657
658 /* Paranoia check: e0/e1 should better be the same. */
659 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
660 a1->esw.eacr.e1 != a2->esw.eacr.e1)
661 return 0;
662
663 /* Still connected to the same etr ? */
664 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
665 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
666 if (state_a1 == etr_lpsc_operational_step) {
667 if (state_a2 != etr_lpsc_operational_step ||
668 a1->edf1.net_id != a2->edf1.net_id ||
669 a1->edf1.etr_id != a2->edf1.etr_id ||
670 a1->edf1.etr_pn != a2->edf1.etr_pn)
671 return 0;
672 } else if (state_a2 != etr_lpsc_pps_mode)
673 return 0;
674
675 /* The ETV value of a2 needs to be ETV of a1 + 1. */
676 if (a1->edf2.etv + 1 != a2->edf2.etv)
677 return 0;
678
679 if (!etr_port_valid(a2, p))
680 return 0;
681
682 return 1;
683}
684
d2fec595 685struct clock_sync_data {
750887de 686 atomic_t cpus;
5a62b192
HC
687 int in_sync;
688 unsigned long long fixup_cc;
750887de
HC
689 int etr_port;
690 struct etr_aib *etr_aib;
d2fec595 691};
5a62b192 692
750887de 693static void clock_sync_cpu(struct clock_sync_data *sync)
d54853ef 694{
750887de 695 atomic_dec(&sync->cpus);
d2fec595 696 enable_sync_clock();
d54853ef
MS
697 /*
698 * This looks like a busy wait loop but it isn't. etr_sync_cpus
699 * is called on all other cpus while the TOD clocks is stopped.
700 * __udelay will stop the cpu on an enabled wait psw until the
701 * TOD is running again.
702 */
d2fec595 703 while (sync->in_sync == 0) {
d54853ef 704 __udelay(1);
6c732de2
HC
705 /*
706 * A different cpu changes *in_sync. Therefore use
707 * barrier() to force memory access.
708 */
709 barrier();
710 }
d2fec595 711 if (sync->in_sync != 1)
d54853ef 712 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 713 disable_sync_clock(NULL);
d54853ef
MS
714 /*
715 * This round of TOD syncing is done. Set the clock comparator
716 * to the next tick and let the processor continue.
717 */
d2fec595 718 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
719}
720
d54853ef
MS
721/*
722 * Sync the TOD clock using the port refered to by aibp. This port
723 * has to be enabled and the other port has to be disabled. The
724 * last eacr update has to be more than 1.6 seconds in the past.
725 */
750887de 726static int etr_sync_clock(void *data)
d54853ef 727{
750887de 728 static int first;
5a62b192 729 unsigned long long clock, old_clock, delay, delta;
750887de
HC
730 struct clock_sync_data *etr_sync;
731 struct etr_aib *sync_port, *aib;
732 int port;
d54853ef
MS
733 int rc;
734
750887de 735 etr_sync = data;
d54853ef 736
750887de
HC
737 if (xchg(&first, 1) == 1) {
738 /* Slave */
739 clock_sync_cpu(etr_sync);
740 return 0;
741 }
742
743 /* Wait until all other cpus entered the sync function. */
744 while (atomic_read(&etr_sync->cpus) != 0)
745 cpu_relax();
746
747 port = etr_sync->etr_port;
748 aib = etr_sync->etr_aib;
749 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
d2fec595 750 enable_sync_clock();
d54853ef
MS
751
752 /* Set clock to next OTE. */
753 __ctl_set_bit(14, 21);
754 __ctl_set_bit(0, 29);
755 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 756 old_clock = get_clock();
d54853ef
MS
757 if (set_clock(clock) == 0) {
758 __udelay(1); /* Wait for the clock to start. */
759 __ctl_clear_bit(0, 29);
760 __ctl_clear_bit(14, 21);
761 etr_stetr(aib);
762 /* Adjust Linux timing variables. */
763 delay = (unsigned long long)
764 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 765 delta = adjust_time(old_clock, clock, delay);
750887de 766 etr_sync->fixup_cc = delta;
5a62b192 767 fixup_clock_comparator(delta);
d54853ef
MS
768 /* Verify that the clock is properly set. */
769 if (!etr_aib_follows(sync_port, aib, port)) {
770 /* Didn't work. */
d2fec595 771 disable_sync_clock(NULL);
750887de 772 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
773 rc = -EAGAIN;
774 } else {
750887de 775 etr_sync->in_sync = 1;
d54853ef
MS
776 rc = 0;
777 }
778 } else {
779 /* Could not set the clock ?!? */
780 __ctl_clear_bit(0, 29);
781 __ctl_clear_bit(14, 21);
d2fec595 782 disable_sync_clock(NULL);
750887de 783 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
784 rc = -EAGAIN;
785 }
750887de
HC
786 xchg(&first, 0);
787 return rc;
788}
789
790static int etr_sync_clock_stop(struct etr_aib *aib, int port)
791{
792 struct clock_sync_data etr_sync;
793 struct etr_aib *sync_port;
794 int follows;
795 int rc;
796
797 /* Check if the current aib is adjacent to the sync port aib. */
798 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
799 follows = etr_aib_follows(sync_port, aib, port);
800 memcpy(sync_port, aib, sizeof(*aib));
801 if (!follows)
802 return -EAGAIN;
803 memset(&etr_sync, 0, sizeof(etr_sync));
804 etr_sync.etr_aib = aib;
805 etr_sync.etr_port = port;
806 get_online_cpus();
807 atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
808 rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map);
809 put_online_cpus();
d54853ef
MS
810 return rc;
811}
812
813/*
814 * Handle the immediate effects of the different events.
815 * The port change event is used for online/offline changes.
816 */
817static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
818{
819 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
820 eacr.es = 0;
821 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
822 eacr.es = eacr.sl = 0;
823 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
824 etr_port0_uptodate = etr_port1_uptodate = 0;
825
826 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
827 if (eacr.e0)
828 /*
829 * Port change of an enabled port. We have to
830 * assume that this can have caused an stepping
831 * port switch.
832 */
833 etr_tolec = get_clock();
834 eacr.p0 = etr_port0_online;
835 if (!eacr.p0)
836 eacr.e0 = 0;
837 etr_port0_uptodate = 0;
838 }
839 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
840 if (eacr.e1)
841 /*
842 * Port change of an enabled port. We have to
843 * assume that this can have caused an stepping
844 * port switch.
845 */
846 etr_tolec = get_clock();
847 eacr.p1 = etr_port1_online;
848 if (!eacr.p1)
849 eacr.e1 = 0;
850 etr_port1_uptodate = 0;
851 }
852 clear_bit(ETR_EVENT_UPDATE, &etr_events);
853 return eacr;
854}
855
856/*
857 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
858 * one of the ports needs an update.
859 */
860static void etr_set_tolec_timeout(unsigned long long now)
861{
862 unsigned long micros;
863
864 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
865 (!etr_eacr.p1 || etr_port1_uptodate))
866 return;
867 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
868 micros = (micros > 1600000) ? 0 : 1600000 - micros;
869 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
870}
871
872/*
873 * Set up a time that expires after 1/2 second.
874 */
875static void etr_set_sync_timeout(void)
876{
877 mod_timer(&etr_timer, jiffies + HZ/2);
878}
879
880/*
881 * Update the aib information for one or both ports.
882 */
883static struct etr_eacr etr_handle_update(struct etr_aib *aib,
884 struct etr_eacr eacr)
885{
886 /* With both ports disabled the aib information is useless. */
887 if (!eacr.e0 && !eacr.e1)
888 return eacr;
889
ecdcc023 890 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
891 if (aib->esw.q == 0) {
892 /* Information for port 0 stored. */
893 if (eacr.p0 && !etr_port0_uptodate) {
894 etr_port0 = *aib;
895 if (etr_port0_online)
896 etr_port0_uptodate = 1;
897 }
898 } else {
899 /* Information for port 1 stored. */
900 if (eacr.p1 && !etr_port1_uptodate) {
901 etr_port1 = *aib;
902 if (etr_port0_online)
903 etr_port1_uptodate = 1;
904 }
905 }
906
907 /*
908 * Do not try to get the alternate port aib if the clock
909 * is not in sync yet.
910 */
33fea794 911 if (!eacr.es || !check_sync_clock())
d54853ef
MS
912 return eacr;
913
914 /*
915 * If steai is available we can get the information about
916 * the other port immediately. If only stetr is available the
917 * data-port bit toggle has to be used.
918 */
d2fec595 919 if (etr_steai_available) {
d54853ef
MS
920 if (eacr.p0 && !etr_port0_uptodate) {
921 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
922 etr_port0_uptodate = 1;
923 }
924 if (eacr.p1 && !etr_port1_uptodate) {
925 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
926 etr_port1_uptodate = 1;
927 }
928 } else {
929 /*
930 * One port was updated above, if the other
931 * port is not uptodate toggle dp bit.
932 */
933 if ((eacr.p0 && !etr_port0_uptodate) ||
934 (eacr.p1 && !etr_port1_uptodate))
935 eacr.dp ^= 1;
936 else
937 eacr.dp = 0;
938 }
939 return eacr;
940}
941
942/*
943 * Write new etr control register if it differs from the current one.
944 * Return 1 if etr_tolec has been updated as well.
945 */
946static void etr_update_eacr(struct etr_eacr eacr)
947{
948 int dp_changed;
949
950 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
951 /* No change, return. */
952 return;
953 /*
954 * The disable of an active port of the change of the data port
955 * bit can/will cause a change in the data port.
956 */
957 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
958 (etr_eacr.dp ^ eacr.dp) != 0;
959 etr_eacr = eacr;
960 etr_setr(&etr_eacr);
961 if (dp_changed)
962 etr_tolec = get_clock();
963}
964
965/*
750887de 966 * ETR work. In this function you'll find the main logic. In
d54853ef
MS
967 * particular this is the only function that calls etr_update_eacr(),
968 * it "controls" the etr control register.
969 */
ecdcc023 970static void etr_work_fn(struct work_struct *work)
d54853ef
MS
971{
972 unsigned long long now;
973 struct etr_eacr eacr;
974 struct etr_aib aib;
975 int sync_port;
976
0b3016b7
MS
977 /* prevent multiple execution. */
978 mutex_lock(&etr_work_mutex);
979
d54853ef
MS
980 /* Create working copy of etr_eacr. */
981 eacr = etr_eacr;
982
983 /* Check for the different events and their immediate effects. */
984 eacr = etr_handle_events(eacr);
985
986 /* Check if ETR is supposed to be active. */
987 eacr.ea = eacr.p0 || eacr.p1;
988 if (!eacr.ea) {
989 /* Both ports offline. Reset everything. */
990 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 991 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
992 del_timer_sync(&etr_timer);
993 etr_update_eacr(eacr);
0b3016b7 994 goto out_unlock;
d54853ef
MS
995 }
996
997 /* Store aib to get the current ETR status word. */
998 BUG_ON(etr_stetr(&aib) != 0);
999 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
1000 now = get_clock();
1001
1002 /*
1003 * Update the port information if the last stepping port change
1004 * or data port change is older than 1.6 seconds.
1005 */
1006 if (now >= etr_tolec + (1600000 << 12))
1007 eacr = etr_handle_update(&aib, eacr);
1008
1009 /*
1010 * Select ports to enable. The prefered synchronization mode is PPS.
1011 * If a port can be enabled depends on a number of things:
1012 * 1) The port needs to be online and uptodate. A port is not
1013 * disabled just because it is not uptodate, but it is only
1014 * enabled if it is uptodate.
1015 * 2) The port needs to have the same mode (pps / etr).
1016 * 3) The port needs to be usable -> etr_port_valid() == 1
1017 * 4) To enable the second port the clock needs to be in sync.
1018 * 5) If both ports are useable and are ETR ports, the network id
1019 * has to be the same.
1020 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1021 */
1022 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
1023 eacr.sl = 0;
1024 eacr.e0 = 1;
1025 if (!etr_mode_is_pps(etr_eacr))
1026 eacr.es = 0;
1027 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
1028 eacr.e1 = 0;
1029 // FIXME: uptodate checks ?
1030 else if (etr_port0_uptodate && etr_port1_uptodate)
1031 eacr.e1 = 1;
1032 sync_port = (etr_port0_uptodate &&
1033 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1034 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
1035 eacr.sl = 0;
1036 eacr.e0 = 0;
1037 eacr.e1 = 1;
1038 if (!etr_mode_is_pps(etr_eacr))
1039 eacr.es = 0;
1040 sync_port = (etr_port1_uptodate &&
1041 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1042 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
1043 eacr.sl = 1;
1044 eacr.e0 = 1;
1045 if (!etr_mode_is_etr(etr_eacr))
1046 eacr.es = 0;
1047 if (!eacr.es || !eacr.p1 ||
1048 aib.esw.psc1 != etr_lpsc_operational_alt)
1049 eacr.e1 = 0;
1050 else if (etr_port0_uptodate && etr_port1_uptodate &&
1051 etr_compare_network(&etr_port0, &etr_port1))
1052 eacr.e1 = 1;
1053 sync_port = (etr_port0_uptodate &&
1054 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1055 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
1056 eacr.sl = 1;
1057 eacr.e0 = 0;
1058 eacr.e1 = 1;
1059 if (!etr_mode_is_etr(etr_eacr))
1060 eacr.es = 0;
1061 sync_port = (etr_port1_uptodate &&
1062 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1063 } else {
1064 /* Both ports not usable. */
1065 eacr.es = eacr.sl = 0;
1066 sync_port = -1;
d54853ef
MS
1067 }
1068
1069 /*
1070 * If the clock is in sync just update the eacr and return.
1071 * If there is no valid sync port wait for a port update.
1072 */
33fea794 1073 if ((eacr.es && check_sync_clock()) || sync_port < 0) {
d54853ef
MS
1074 etr_update_eacr(eacr);
1075 etr_set_tolec_timeout(now);
0b3016b7 1076 goto out_unlock;
d54853ef
MS
1077 }
1078
1079 /*
1080 * Prepare control register for clock syncing
1081 * (reset data port bit, set sync check control.
1082 */
1083 eacr.dp = 0;
1084 eacr.es = 1;
1085
1086 /*
1087 * Update eacr and try to synchronize the clock. If the update
1088 * of eacr caused a stepping port switch (or if we have to
1089 * assume that a stepping port switch has occured) or the
1090 * clock syncing failed, reset the sync check control bit
1091 * and set up a timer to try again after 0.5 seconds
1092 */
1093 etr_update_eacr(eacr);
1094 if (now < etr_tolec + (1600000 << 12) ||
750887de 1095 etr_sync_clock_stop(&aib, sync_port) != 0) {
d54853ef
MS
1096 /* Sync failed. Try again in 1/2 second. */
1097 eacr.es = 0;
1098 etr_update_eacr(eacr);
1099 etr_set_sync_timeout();
1100 } else
1101 etr_set_tolec_timeout(now);
0b3016b7
MS
1102out_unlock:
1103 mutex_unlock(&etr_work_mutex);
d54853ef
MS
1104}
1105
1106/*
1107 * Sysfs interface functions
1108 */
1109static struct sysdev_class etr_sysclass = {
af5ca3f4 1110 .name = "etr",
d54853ef
MS
1111};
1112
1113static struct sys_device etr_port0_dev = {
1114 .id = 0,
1115 .cls = &etr_sysclass,
1116};
1117
1118static struct sys_device etr_port1_dev = {
1119 .id = 1,
1120 .cls = &etr_sysclass,
1121};
1122
1123/*
1124 * ETR class attributes
1125 */
c9be0a36
AK
1126static ssize_t etr_stepping_port_show(struct sysdev_class *class,
1127 struct sysdev_class_attribute *attr,
1128 char *buf)
d54853ef
MS
1129{
1130 return sprintf(buf, "%i\n", etr_port0.esw.p);
1131}
1132
1133static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1134
c9be0a36
AK
1135static ssize_t etr_stepping_mode_show(struct sysdev_class *class,
1136 struct sysdev_class_attribute *attr,
1137 char *buf)
d54853ef
MS
1138{
1139 char *mode_str;
1140
1141 if (etr_mode_is_pps(etr_eacr))
1142 mode_str = "pps";
1143 else if (etr_mode_is_etr(etr_eacr))
1144 mode_str = "etr";
1145 else
1146 mode_str = "local";
1147 return sprintf(buf, "%s\n", mode_str);
1148}
1149
1150static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1151
1152/*
1153 * ETR port attributes
1154 */
1155static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1156{
1157 if (dev == &etr_port0_dev)
1158 return etr_port0_online ? &etr_port0 : NULL;
1159 else
1160 return etr_port1_online ? &etr_port1 : NULL;
1161}
1162
4a0b2b4d
AK
1163static ssize_t etr_online_show(struct sys_device *dev,
1164 struct sysdev_attribute *attr,
1165 char *buf)
d54853ef
MS
1166{
1167 unsigned int online;
1168
1169 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1170 return sprintf(buf, "%i\n", online);
1171}
1172
1173static ssize_t etr_online_store(struct sys_device *dev,
4a0b2b4d
AK
1174 struct sysdev_attribute *attr,
1175 const char *buf, size_t count)
d54853ef
MS
1176{
1177 unsigned int value;
1178
1179 value = simple_strtoul(buf, NULL, 0);
1180 if (value != 0 && value != 1)
1181 return -EINVAL;
d2fec595
MS
1182 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1183 return -EOPNOTSUPP;
8283cb43 1184 mutex_lock(&clock_sync_mutex);
d54853ef
MS
1185 if (dev == &etr_port0_dev) {
1186 if (etr_port0_online == value)
8283cb43 1187 goto out; /* Nothing to do. */
d54853ef 1188 etr_port0_online = value;
8283cb43
MS
1189 if (etr_port0_online && etr_port1_online)
1190 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1191 else
1192 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1193 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 1194 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1195 } else {
1196 if (etr_port1_online == value)
8283cb43 1197 goto out; /* Nothing to do. */
d54853ef 1198 etr_port1_online = value;
8283cb43
MS
1199 if (etr_port0_online && etr_port1_online)
1200 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
1201 else
1202 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1203 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 1204 queue_work(time_sync_wq, &etr_work);
d54853ef 1205 }
8283cb43
MS
1206out:
1207 mutex_unlock(&clock_sync_mutex);
d54853ef
MS
1208 return count;
1209}
1210
1211static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1212
4a0b2b4d
AK
1213static ssize_t etr_stepping_control_show(struct sys_device *dev,
1214 struct sysdev_attribute *attr,
1215 char *buf)
d54853ef
MS
1216{
1217 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1218 etr_eacr.e0 : etr_eacr.e1);
1219}
1220
1221static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1222
4a0b2b4d
AK
1223static ssize_t etr_mode_code_show(struct sys_device *dev,
1224 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1225{
1226 if (!etr_port0_online && !etr_port1_online)
1227 /* Status word is not uptodate if both ports are offline. */
1228 return -ENODATA;
1229 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1230 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1231}
1232
1233static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1234
4a0b2b4d
AK
1235static ssize_t etr_untuned_show(struct sys_device *dev,
1236 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1237{
1238 struct etr_aib *aib = etr_aib_from_dev(dev);
1239
1240 if (!aib || !aib->slsw.v1)
1241 return -ENODATA;
1242 return sprintf(buf, "%i\n", aib->edf1.u);
1243}
1244
1245static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1246
4a0b2b4d
AK
1247static ssize_t etr_network_id_show(struct sys_device *dev,
1248 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1249{
1250 struct etr_aib *aib = etr_aib_from_dev(dev);
1251
1252 if (!aib || !aib->slsw.v1)
1253 return -ENODATA;
1254 return sprintf(buf, "%i\n", aib->edf1.net_id);
1255}
1256
1257static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1258
4a0b2b4d
AK
1259static ssize_t etr_id_show(struct sys_device *dev,
1260 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1261{
1262 struct etr_aib *aib = etr_aib_from_dev(dev);
1263
1264 if (!aib || !aib->slsw.v1)
1265 return -ENODATA;
1266 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1267}
1268
1269static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1270
4a0b2b4d
AK
1271static ssize_t etr_port_number_show(struct sys_device *dev,
1272 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1273{
1274 struct etr_aib *aib = etr_aib_from_dev(dev);
1275
1276 if (!aib || !aib->slsw.v1)
1277 return -ENODATA;
1278 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1279}
1280
1281static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1282
4a0b2b4d
AK
1283static ssize_t etr_coupled_show(struct sys_device *dev,
1284 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1285{
1286 struct etr_aib *aib = etr_aib_from_dev(dev);
1287
1288 if (!aib || !aib->slsw.v3)
1289 return -ENODATA;
1290 return sprintf(buf, "%i\n", aib->edf3.c);
1291}
1292
1293static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1294
4a0b2b4d
AK
1295static ssize_t etr_local_time_show(struct sys_device *dev,
1296 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1297{
1298 struct etr_aib *aib = etr_aib_from_dev(dev);
1299
1300 if (!aib || !aib->slsw.v3)
1301 return -ENODATA;
1302 return sprintf(buf, "%i\n", aib->edf3.blto);
1303}
1304
1305static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1306
4a0b2b4d
AK
1307static ssize_t etr_utc_offset_show(struct sys_device *dev,
1308 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1309{
1310 struct etr_aib *aib = etr_aib_from_dev(dev);
1311
1312 if (!aib || !aib->slsw.v3)
1313 return -ENODATA;
1314 return sprintf(buf, "%i\n", aib->edf3.buo);
1315}
1316
1317static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1318
1319static struct sysdev_attribute *etr_port_attributes[] = {
1320 &attr_online,
1321 &attr_stepping_control,
1322 &attr_state_code,
1323 &attr_untuned,
1324 &attr_network,
1325 &attr_id,
1326 &attr_port,
1327 &attr_coupled,
1328 &attr_local_time,
1329 &attr_utc_offset,
1330 NULL
1331};
1332
1333static int __init etr_register_port(struct sys_device *dev)
1334{
1335 struct sysdev_attribute **attr;
1336 int rc;
1337
1338 rc = sysdev_register(dev);
1339 if (rc)
1340 goto out;
1341 for (attr = etr_port_attributes; *attr; attr++) {
1342 rc = sysdev_create_file(dev, *attr);
1343 if (rc)
1344 goto out_unreg;
1345 }
1346 return 0;
1347out_unreg:
1348 for (; attr >= etr_port_attributes; attr--)
1349 sysdev_remove_file(dev, *attr);
1350 sysdev_unregister(dev);
1351out:
1352 return rc;
1353}
1354
1355static void __init etr_unregister_port(struct sys_device *dev)
1356{
1357 struct sysdev_attribute **attr;
1358
1359 for (attr = etr_port_attributes; *attr; attr++)
1360 sysdev_remove_file(dev, *attr);
1361 sysdev_unregister(dev);
1362}
1363
1364static int __init etr_init_sysfs(void)
1365{
1366 int rc;
1367
1368 rc = sysdev_class_register(&etr_sysclass);
1369 if (rc)
1370 goto out;
1371 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1372 if (rc)
1373 goto out_unreg_class;
1374 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1375 if (rc)
1376 goto out_remove_stepping_port;
1377 rc = etr_register_port(&etr_port0_dev);
1378 if (rc)
1379 goto out_remove_stepping_mode;
1380 rc = etr_register_port(&etr_port1_dev);
1381 if (rc)
1382 goto out_remove_port0;
1383 return 0;
1384
1385out_remove_port0:
1386 etr_unregister_port(&etr_port0_dev);
1387out_remove_stepping_mode:
1388 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1389out_remove_stepping_port:
1390 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1391out_unreg_class:
1392 sysdev_class_unregister(&etr_sysclass);
1393out:
1394 return rc;
1da177e4
LT
1395}
1396
d54853ef 1397device_initcall(etr_init_sysfs);
d2fec595
MS
1398
1399/*
1400 * Server Time Protocol (STP) code.
1401 */
1402static int stp_online;
1403static struct stp_sstpi stp_info;
1404static void *stp_page;
1405
1406static void stp_work_fn(struct work_struct *work);
0b3016b7 1407static DEFINE_MUTEX(stp_work_mutex);
d2fec595 1408static DECLARE_WORK(stp_work, stp_work_fn);
04362301 1409static struct timer_list stp_timer;
d2fec595
MS
1410
1411static int __init early_parse_stp(char *p)
1412{
1413 if (strncmp(p, "off", 3) == 0)
1414 stp_online = 0;
1415 else if (strncmp(p, "on", 2) == 0)
1416 stp_online = 1;
1417 return 0;
1418}
1419early_param("stp", early_parse_stp);
1420
1421/*
1422 * Reset STP attachment.
1423 */
8f847003 1424static void __init stp_reset(void)
d2fec595
MS
1425{
1426 int rc;
1427
d7d1104f 1428 stp_page = (void *) get_zeroed_page(GFP_ATOMIC);
d2fec595 1429 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1430 if (rc == 0)
d2fec595
MS
1431 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1432 else if (stp_online) {
feab6501
MS
1433 pr_warning("The real or virtual hardware system does "
1434 "not provide an STP interface\n");
d7d1104f 1435 free_page((unsigned long) stp_page);
d2fec595
MS
1436 stp_page = NULL;
1437 stp_online = 0;
1438 }
1439}
1440
04362301
MS
1441static void stp_timeout(unsigned long dummy)
1442{
1443 queue_work(time_sync_wq, &stp_work);
1444}
1445
d2fec595
MS
1446static int __init stp_init(void)
1447{
750887de
HC
1448 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1449 return 0;
04362301 1450 setup_timer(&stp_timer, stp_timeout, 0UL);
750887de
HC
1451 time_init_wq();
1452 if (!stp_online)
1453 return 0;
1454 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1455 return 0;
1456}
1457
1458arch_initcall(stp_init);
1459
1460/*
1461 * STP timing alert. There are three causes:
1462 * 1) timing status change
1463 * 2) link availability change
1464 * 3) time control parameter change
1465 * In all three cases we are only interested in the clock source state.
1466 * If a STP clock source is now available use it.
1467 */
1468static void stp_timing_alert(struct stp_irq_parm *intparm)
1469{
1470 if (intparm->tsc || intparm->lac || intparm->tcpc)
750887de 1471 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1472}
1473
1474/*
1475 * STP sync check machine check. This is called when the timing state
1476 * changes from the synchronized state to the unsynchronized state.
1477 * After a STP sync check the clock is not in sync. The machine check
1478 * is broadcasted to all cpus at the same time.
1479 */
1480void stp_sync_check(void)
1481{
d2fec595 1482 disable_sync_clock(NULL);
750887de 1483 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1484}
1485
1486/*
1487 * STP island condition machine check. This is called when an attached
1488 * server attempts to communicate over an STP link and the servers
1489 * have matching CTN ids and have a valid stratum-1 configuration
1490 * but the configurations do not match.
1491 */
1492void stp_island_check(void)
1493{
d2fec595 1494 disable_sync_clock(NULL);
750887de 1495 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1496}
1497
750887de
HC
1498
1499static int stp_sync_clock(void *data)
d2fec595 1500{
750887de 1501 static int first;
d2fec595 1502 unsigned long long old_clock, delta;
750887de 1503 struct clock_sync_data *stp_sync;
d2fec595
MS
1504 int rc;
1505
750887de 1506 stp_sync = data;
d2fec595 1507
750887de
HC
1508 if (xchg(&first, 1) == 1) {
1509 /* Slave */
1510 clock_sync_cpu(stp_sync);
1511 return 0;
1512 }
d2fec595 1513
750887de
HC
1514 /* Wait until all other cpus entered the sync function. */
1515 while (atomic_read(&stp_sync->cpus) != 0)
1516 cpu_relax();
d2fec595 1517
d2fec595
MS
1518 enable_sync_clock();
1519
d2fec595
MS
1520 rc = 0;
1521 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1522 stp_info.todoff[2] || stp_info.todoff[3] ||
1523 stp_info.tmd != 2) {
1524 old_clock = get_clock();
1525 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1526 if (rc == 0) {
1527 delta = adjust_time(old_clock, get_clock(), 0);
1528 fixup_clock_comparator(delta);
1529 rc = chsc_sstpi(stp_page, &stp_info,
1530 sizeof(struct stp_sstpi));
1531 if (rc == 0 && stp_info.tmd != 2)
1532 rc = -EAGAIN;
1533 }
1534 }
1535 if (rc) {
1536 disable_sync_clock(NULL);
750887de 1537 stp_sync->in_sync = -EAGAIN;
d2fec595 1538 } else
750887de
HC
1539 stp_sync->in_sync = 1;
1540 xchg(&first, 0);
1541 return 0;
1542}
d2fec595 1543
750887de
HC
1544/*
1545 * STP work. Check for the STP state and take over the clock
1546 * synchronization if the STP clock source is usable.
1547 */
1548static void stp_work_fn(struct work_struct *work)
1549{
1550 struct clock_sync_data stp_sync;
1551 int rc;
1552
0b3016b7
MS
1553 /* prevent multiple execution. */
1554 mutex_lock(&stp_work_mutex);
1555
750887de
HC
1556 if (!stp_online) {
1557 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
04362301 1558 del_timer_sync(&stp_timer);
0b3016b7 1559 goto out_unlock;
750887de
HC
1560 }
1561
1562 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1563 if (rc)
0b3016b7 1564 goto out_unlock;
750887de
HC
1565
1566 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1567 if (rc || stp_info.c == 0)
0b3016b7 1568 goto out_unlock;
750887de 1569
8283cb43
MS
1570 /* Skip synchronization if the clock is already in sync. */
1571 if (check_sync_clock())
1572 goto out_unlock;
1573
750887de
HC
1574 memset(&stp_sync, 0, sizeof(stp_sync));
1575 get_online_cpus();
1576 atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
1577 stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map);
1578 put_online_cpus();
0b3016b7 1579
04362301
MS
1580 if (!check_sync_clock())
1581 /*
1582 * There is a usable clock but the synchonization failed.
1583 * Retry after a second.
1584 */
1585 mod_timer(&stp_timer, jiffies + HZ);
1586
0b3016b7
MS
1587out_unlock:
1588 mutex_unlock(&stp_work_mutex);
d2fec595
MS
1589}
1590
1591/*
1592 * STP class sysfs interface functions
1593 */
1594static struct sysdev_class stp_sysclass = {
1595 .name = "stp",
1596};
1597
c9be0a36
AK
1598static ssize_t stp_ctn_id_show(struct sysdev_class *class,
1599 struct sysdev_class_attribute *attr,
1600 char *buf)
d2fec595
MS
1601{
1602 if (!stp_online)
1603 return -ENODATA;
1604 return sprintf(buf, "%016llx\n",
1605 *(unsigned long long *) stp_info.ctnid);
1606}
1607
1608static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1609
c9be0a36
AK
1610static ssize_t stp_ctn_type_show(struct sysdev_class *class,
1611 struct sysdev_class_attribute *attr,
1612 char *buf)
d2fec595
MS
1613{
1614 if (!stp_online)
1615 return -ENODATA;
1616 return sprintf(buf, "%i\n", stp_info.ctn);
1617}
1618
1619static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1620
c9be0a36
AK
1621static ssize_t stp_dst_offset_show(struct sysdev_class *class,
1622 struct sysdev_class_attribute *attr,
1623 char *buf)
d2fec595
MS
1624{
1625 if (!stp_online || !(stp_info.vbits & 0x2000))
1626 return -ENODATA;
1627 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1628}
1629
1630static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1631
c9be0a36
AK
1632static ssize_t stp_leap_seconds_show(struct sysdev_class *class,
1633 struct sysdev_class_attribute *attr,
1634 char *buf)
d2fec595
MS
1635{
1636 if (!stp_online || !(stp_info.vbits & 0x8000))
1637 return -ENODATA;
1638 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1639}
1640
1641static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1642
c9be0a36
AK
1643static ssize_t stp_stratum_show(struct sysdev_class *class,
1644 struct sysdev_class_attribute *attr,
1645 char *buf)
d2fec595
MS
1646{
1647 if (!stp_online)
1648 return -ENODATA;
1649 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1650}
1651
1652static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1653
c9be0a36
AK
1654static ssize_t stp_time_offset_show(struct sysdev_class *class,
1655 struct sysdev_class_attribute *attr,
1656 char *buf)
d2fec595
MS
1657{
1658 if (!stp_online || !(stp_info.vbits & 0x0800))
1659 return -ENODATA;
1660 return sprintf(buf, "%i\n", (int) stp_info.tto);
1661}
1662
1663static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1664
c9be0a36
AK
1665static ssize_t stp_time_zone_offset_show(struct sysdev_class *class,
1666 struct sysdev_class_attribute *attr,
1667 char *buf)
d2fec595
MS
1668{
1669 if (!stp_online || !(stp_info.vbits & 0x4000))
1670 return -ENODATA;
1671 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1672}
1673
1674static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1675 stp_time_zone_offset_show, NULL);
1676
c9be0a36
AK
1677static ssize_t stp_timing_mode_show(struct sysdev_class *class,
1678 struct sysdev_class_attribute *attr,
1679 char *buf)
d2fec595
MS
1680{
1681 if (!stp_online)
1682 return -ENODATA;
1683 return sprintf(buf, "%i\n", stp_info.tmd);
1684}
1685
1686static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1687
c9be0a36
AK
1688static ssize_t stp_timing_state_show(struct sysdev_class *class,
1689 struct sysdev_class_attribute *attr,
1690 char *buf)
d2fec595
MS
1691{
1692 if (!stp_online)
1693 return -ENODATA;
1694 return sprintf(buf, "%i\n", stp_info.tst);
1695}
1696
1697static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1698
c9be0a36
AK
1699static ssize_t stp_online_show(struct sysdev_class *class,
1700 struct sysdev_class_attribute *attr,
1701 char *buf)
d2fec595
MS
1702{
1703 return sprintf(buf, "%i\n", stp_online);
1704}
1705
1706static ssize_t stp_online_store(struct sysdev_class *class,
c9be0a36 1707 struct sysdev_class_attribute *attr,
d2fec595
MS
1708 const char *buf, size_t count)
1709{
1710 unsigned int value;
1711
1712 value = simple_strtoul(buf, NULL, 0);
1713 if (value != 0 && value != 1)
1714 return -EINVAL;
1715 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1716 return -EOPNOTSUPP;
8283cb43 1717 mutex_lock(&clock_sync_mutex);
d2fec595 1718 stp_online = value;
8283cb43
MS
1719 if (stp_online)
1720 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1721 else
1722 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
750887de 1723 queue_work(time_sync_wq, &stp_work);
8283cb43 1724 mutex_unlock(&clock_sync_mutex);
d2fec595
MS
1725 return count;
1726}
1727
1728/*
1729 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1730 * stp/online but attr_online already exists in this file ..
1731 */
1732static struct sysdev_class_attribute attr_stp_online = {
1733 .attr = { .name = "online", .mode = 0600 },
1734 .show = stp_online_show,
1735 .store = stp_online_store,
1736};
1737
1738static struct sysdev_class_attribute *stp_attributes[] = {
1739 &attr_ctn_id,
1740 &attr_ctn_type,
1741 &attr_dst_offset,
1742 &attr_leap_seconds,
1743 &attr_stp_online,
1744 &attr_stratum,
1745 &attr_time_offset,
1746 &attr_time_zone_offset,
1747 &attr_timing_mode,
1748 &attr_timing_state,
1749 NULL
1750};
1751
1752static int __init stp_init_sysfs(void)
1753{
1754 struct sysdev_class_attribute **attr;
1755 int rc;
1756
1757 rc = sysdev_class_register(&stp_sysclass);
1758 if (rc)
1759 goto out;
1760 for (attr = stp_attributes; *attr; attr++) {
1761 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1762 if (rc)
1763 goto out_unreg;
1764 }
1765 return 0;
1766out_unreg:
1767 for (; attr >= stp_attributes; attr--)
1768 sysdev_class_remove_file(&stp_sysclass, *attr);
1769 sysdev_class_unregister(&stp_sysclass);
1770out:
1771 return rc;
1772}
1773
1774device_initcall(stp_init_sysfs);