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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/time.c | |
3 | * Time of day based timer functions. | |
4 | * | |
5 | * S390 version | |
6 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
7 | * Author(s): Hartmut Penner (hp@de.ibm.com), | |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
9 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
10 | * | |
11 | * Derived from "arch/i386/kernel/time.c" | |
12 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
13 | */ | |
14 | ||
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/param.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/time.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/smp.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/profile.h> | |
29 | #include <linux/timex.h> | |
30 | #include <linux/notifier.h> | |
dc64bef5 | 31 | #include <linux/clocksource.h> |
1da177e4 LT |
32 | |
33 | #include <asm/uaccess.h> | |
34 | #include <asm/delay.h> | |
35 | #include <asm/s390_ext.h> | |
36 | #include <asm/div64.h> | |
37 | #include <asm/irq.h> | |
5a489b98 | 38 | #include <asm/irq_regs.h> |
1da177e4 | 39 | #include <asm/timer.h> |
d54853ef | 40 | #include <asm/etr.h> |
1da177e4 LT |
41 | |
42 | /* change this if you have some constant time drift */ | |
43 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
44 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
45 | ||
d54853ef MS |
46 | /* The value of the TOD clock for 1.1.1970. */ |
47 | #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL | |
48 | ||
1da177e4 LT |
49 | /* |
50 | * Create a small time difference between the timer interrupts | |
51 | * on the different cpus to avoid lock contention. | |
52 | */ | |
53 | #define CPU_DEVIATION (smp_processor_id() << 12) | |
54 | ||
55 | #define TICK_SIZE tick | |
56 | ||
1da177e4 | 57 | static ext_int_info_t ext_int_info_cc; |
d54853ef | 58 | static ext_int_info_t ext_int_etr_cc; |
1da177e4 LT |
59 | static u64 init_timer_cc; |
60 | static u64 jiffies_timer_cc; | |
61 | static u64 xtime_cc; | |
62 | ||
1da177e4 LT |
63 | /* |
64 | * Scheduler clock - returns current time in nanosec units. | |
65 | */ | |
66 | unsigned long long sched_clock(void) | |
67 | { | |
9dbafa53 | 68 | return ((get_clock() - jiffies_timer_cc) * 125) >> 9; |
1da177e4 LT |
69 | } |
70 | ||
32f65f27 JG |
71 | /* |
72 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
73 | */ | |
74 | unsigned long long monotonic_clock(void) | |
75 | { | |
76 | return sched_clock(); | |
77 | } | |
78 | EXPORT_SYMBOL(monotonic_clock); | |
79 | ||
1da177e4 LT |
80 | void tod_to_timeval(__u64 todval, struct timespec *xtime) |
81 | { | |
82 | unsigned long long sec; | |
83 | ||
84 | sec = todval >> 12; | |
85 | do_div(sec, 1000000); | |
86 | xtime->tv_sec = sec; | |
87 | todval -= (sec * 1000000) << 12; | |
88 | xtime->tv_nsec = ((todval * 1000) >> 12); | |
89 | } | |
90 | ||
1da177e4 | 91 | #ifdef CONFIG_PROFILING |
5a489b98 | 92 | #define s390_do_profile() profile_tick(CPU_PROFILING) |
1da177e4 | 93 | #else |
5a489b98 | 94 | #define s390_do_profile() do { ; } while(0) |
1da177e4 LT |
95 | #endif /* CONFIG_PROFILING */ |
96 | ||
1da177e4 | 97 | /* |
d54853ef MS |
98 | * Advance the per cpu tick counter up to the time given with the |
99 | * "time" argument. The per cpu update consists of accounting | |
100 | * the virtual cpu time, calling update_process_times and calling | |
101 | * the profiling hook. If xtime is before time it is advanced as well. | |
1da177e4 | 102 | */ |
d54853ef | 103 | void account_ticks(u64 time) |
1da177e4 | 104 | { |
3171a030 | 105 | __u32 ticks; |
d54853ef | 106 | __u64 tmp; |
1da177e4 LT |
107 | |
108 | /* Calculate how many ticks have passed. */ | |
d54853ef | 109 | if (time < S390_lowcore.jiffy_timer) |
1da177e4 | 110 | return; |
d54853ef | 111 | tmp = time - S390_lowcore.jiffy_timer; |
1da177e4 LT |
112 | if (tmp >= 2*CLK_TICKS_PER_JIFFY) { /* more than two ticks ? */ |
113 | ticks = __div(tmp, CLK_TICKS_PER_JIFFY) + 1; | |
114 | S390_lowcore.jiffy_timer += | |
115 | CLK_TICKS_PER_JIFFY * (__u64) ticks; | |
116 | } else if (tmp >= CLK_TICKS_PER_JIFFY) { | |
117 | ticks = 2; | |
118 | S390_lowcore.jiffy_timer += 2*CLK_TICKS_PER_JIFFY; | |
119 | } else { | |
120 | ticks = 1; | |
121 | S390_lowcore.jiffy_timer += CLK_TICKS_PER_JIFFY; | |
122 | } | |
123 | ||
1da177e4 LT |
124 | #ifdef CONFIG_SMP |
125 | /* | |
126 | * Do not rely on the boot cpu to do the calls to do_timer. | |
127 | * Spread it over all cpus instead. | |
128 | */ | |
129 | write_seqlock(&xtime_lock); | |
130 | if (S390_lowcore.jiffy_timer > xtime_cc) { | |
3171a030 | 131 | __u32 xticks; |
1da177e4 LT |
132 | tmp = S390_lowcore.jiffy_timer - xtime_cc; |
133 | if (tmp >= 2*CLK_TICKS_PER_JIFFY) { | |
134 | xticks = __div(tmp, CLK_TICKS_PER_JIFFY); | |
135 | xtime_cc += (__u64) xticks * CLK_TICKS_PER_JIFFY; | |
136 | } else { | |
137 | xticks = 1; | |
138 | xtime_cc += CLK_TICKS_PER_JIFFY; | |
139 | } | |
3171a030 | 140 | do_timer(xticks); |
1da177e4 LT |
141 | } |
142 | write_sequnlock(&xtime_lock); | |
143 | #else | |
3171a030 | 144 | do_timer(ticks); |
1da177e4 LT |
145 | #endif |
146 | ||
147 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING | |
1f1c12af | 148 | account_tick_vtime(current); |
1da177e4 LT |
149 | #else |
150 | while (ticks--) | |
5a489b98 | 151 | update_process_times(user_mode(get_irq_regs())); |
1da177e4 LT |
152 | #endif |
153 | ||
5a489b98 | 154 | s390_do_profile(); |
1da177e4 LT |
155 | } |
156 | ||
157 | #ifdef CONFIG_NO_IDLE_HZ | |
158 | ||
159 | #ifdef CONFIG_NO_IDLE_HZ_INIT | |
160 | int sysctl_hz_timer = 0; | |
161 | #else | |
162 | int sysctl_hz_timer = 1; | |
163 | #endif | |
164 | ||
165 | /* | |
166 | * Stop the HZ tick on the current CPU. | |
167 | * Only cpu_idle may call this function. | |
168 | */ | |
4d284cac | 169 | static void stop_hz_timer(void) |
1da177e4 | 170 | { |
1b44e98d MS |
171 | unsigned long flags; |
172 | unsigned long seq, next; | |
4b7e0706 | 173 | __u64 timer, todval; |
5afdbd6e | 174 | int cpu = smp_processor_id(); |
1da177e4 LT |
175 | |
176 | if (sysctl_hz_timer != 0) | |
177 | return; | |
178 | ||
5afdbd6e | 179 | cpu_set(cpu, nohz_cpu_mask); |
1da177e4 LT |
180 | |
181 | /* | |
182 | * Leave the clock comparator set up for the next timer | |
183 | * tick if either rcu or a softirq is pending. | |
184 | */ | |
5afdbd6e HC |
185 | if (rcu_needs_cpu(cpu) || local_softirq_pending()) { |
186 | cpu_clear(cpu, nohz_cpu_mask); | |
1da177e4 LT |
187 | return; |
188 | } | |
189 | ||
190 | /* | |
191 | * This cpu is going really idle. Set up the clock comparator | |
192 | * for the next event. | |
193 | */ | |
1b44e98d MS |
194 | next = next_timer_interrupt(); |
195 | do { | |
196 | seq = read_seqbegin_irqsave(&xtime_lock, flags); | |
705af309 | 197 | timer = ((__u64) next) - ((__u64) jiffies) + jiffies_64; |
1b44e98d | 198 | } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); |
4b7e0706 MS |
199 | todval = -1ULL; |
200 | /* Be careful about overflows. */ | |
201 | if (timer < (-1ULL / CLK_TICKS_PER_JIFFY)) { | |
202 | timer = jiffies_timer_cc + timer * CLK_TICKS_PER_JIFFY; | |
203 | if (timer >= jiffies_timer_cc) | |
204 | todval = timer; | |
205 | } | |
d54853ef | 206 | set_clock_comparator(todval); |
1da177e4 LT |
207 | } |
208 | ||
209 | /* | |
210 | * Start the HZ tick on the current CPU. | |
211 | * Only cpu_idle may call this function. | |
212 | */ | |
4d284cac | 213 | static void start_hz_timer(void) |
1da177e4 | 214 | { |
5a489b98 HC |
215 | BUG_ON(!in_interrupt()); |
216 | ||
1da177e4 LT |
217 | if (!cpu_isset(smp_processor_id(), nohz_cpu_mask)) |
218 | return; | |
d54853ef MS |
219 | account_ticks(get_clock()); |
220 | set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); | |
1da177e4 LT |
221 | cpu_clear(smp_processor_id(), nohz_cpu_mask); |
222 | } | |
223 | ||
224 | static int nohz_idle_notify(struct notifier_block *self, | |
225 | unsigned long action, void *hcpu) | |
226 | { | |
227 | switch (action) { | |
228 | case CPU_IDLE: | |
229 | stop_hz_timer(); | |
230 | break; | |
231 | case CPU_NOT_IDLE: | |
232 | start_hz_timer(); | |
233 | break; | |
234 | } | |
235 | return NOTIFY_OK; | |
236 | } | |
237 | ||
238 | static struct notifier_block nohz_idle_nb = { | |
239 | .notifier_call = nohz_idle_notify, | |
240 | }; | |
241 | ||
2b67fc46 | 242 | static void __init nohz_init(void) |
1da177e4 LT |
243 | { |
244 | if (register_idle_notifier(&nohz_idle_nb)) | |
245 | panic("Couldn't register idle notifier"); | |
246 | } | |
247 | ||
248 | #endif | |
249 | ||
250 | /* | |
d54853ef MS |
251 | * Set up per cpu jiffy timer and set the clock comparator. |
252 | */ | |
253 | static void setup_jiffy_timer(void) | |
254 | { | |
255 | /* Set up clock comparator to next jiffy. */ | |
256 | S390_lowcore.jiffy_timer = | |
257 | jiffies_timer_cc + (jiffies_64 + 1) * CLK_TICKS_PER_JIFFY; | |
258 | set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); | |
259 | } | |
260 | ||
261 | /* | |
262 | * Set up lowcore and control register of the current cpu to | |
263 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
264 | */ |
265 | void init_cpu_timer(void) | |
266 | { | |
d54853ef MS |
267 | setup_jiffy_timer(); |
268 | ||
269 | /* Enable clock comparator timer interrupt. */ | |
270 | __ctl_set_bit(0,11); | |
271 | ||
272 | /* Always allow ETR external interrupts, even without an ETR. */ | |
273 | __ctl_set_bit(0, 4); | |
274 | } | |
275 | ||
276 | static void clock_comparator_interrupt(__u16 code) | |
277 | { | |
278 | /* set clock comparator for next tick */ | |
279 | set_clock_comparator(S390_lowcore.jiffy_timer + CPU_DEVIATION); | |
280 | } | |
281 | ||
282 | static void etr_reset(void); | |
283 | static void etr_init(void); | |
284 | static void etr_ext_handler(__u16); | |
285 | ||
286 | /* | |
287 | * Get the TOD clock running. | |
288 | */ | |
289 | static u64 __init reset_tod_clock(void) | |
290 | { | |
291 | u64 time; | |
292 | ||
293 | etr_reset(); | |
294 | if (store_clock(&time) == 0) | |
295 | return time; | |
296 | /* TOD clock not running. Set the clock to Unix Epoch. */ | |
297 | if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0) | |
298 | panic("TOD clock not operational."); | |
1da177e4 | 299 | |
d54853ef | 300 | return TOD_UNIX_EPOCH; |
1da177e4 LT |
301 | } |
302 | ||
dc64bef5 MS |
303 | static cycle_t read_tod_clock(void) |
304 | { | |
305 | return get_clock(); | |
306 | } | |
307 | ||
308 | static struct clocksource clocksource_tod = { | |
309 | .name = "tod", | |
310 | .rating = 100, | |
311 | .read = read_tod_clock, | |
312 | .mask = -1ULL, | |
313 | .mult = 1000, | |
314 | .shift = 12, | |
cc02d809 | 315 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
316 | }; |
317 | ||
318 | ||
1da177e4 LT |
319 | /* |
320 | * Initialize the TOD clock and the CPU timer of | |
321 | * the boot cpu. | |
322 | */ | |
323 | void __init time_init(void) | |
324 | { | |
d54853ef MS |
325 | init_timer_cc = reset_tod_clock(); |
326 | xtime_cc = init_timer_cc + CLK_TICKS_PER_JIFFY; | |
1da177e4 LT |
327 | jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY; |
328 | ||
329 | /* set xtime */ | |
d54853ef | 330 | tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime); |
1da177e4 LT |
331 | set_normalized_timespec(&wall_to_monotonic, |
332 | -xtime.tv_sec, -xtime.tv_nsec); | |
333 | ||
334 | /* request the clock comparator external interrupt */ | |
d54853ef MS |
335 | if (register_early_external_interrupt(0x1004, |
336 | clock_comparator_interrupt, | |
1da177e4 LT |
337 | &ext_int_info_cc) != 0) |
338 | panic("Couldn't request external interrupt 0x1004"); | |
339 | ||
dc64bef5 MS |
340 | if (clocksource_register(&clocksource_tod) != 0) |
341 | panic("Could not register TOD clock source"); | |
342 | ||
d54853ef MS |
343 | /* request the etr external interrupt */ |
344 | if (register_early_external_interrupt(0x1406, etr_ext_handler, | |
345 | &ext_int_etr_cc) != 0) | |
346 | panic("Couldn't request external interrupt 0x1406"); | |
347 | ||
348 | /* Enable TOD clock interrupts on the boot cpu. */ | |
349 | init_cpu_timer(); | |
1da177e4 LT |
350 | |
351 | #ifdef CONFIG_NO_IDLE_HZ | |
352 | nohz_init(); | |
353 | #endif | |
354 | ||
355 | #ifdef CONFIG_VIRT_TIMER | |
356 | vtime_init(); | |
357 | #endif | |
d54853ef MS |
358 | etr_init(); |
359 | } | |
360 | ||
361 | /* | |
362 | * External Time Reference (ETR) code. | |
363 | */ | |
364 | static int etr_port0_online; | |
365 | static int etr_port1_online; | |
366 | ||
367 | static int __init early_parse_etr(char *p) | |
368 | { | |
369 | if (strncmp(p, "off", 3) == 0) | |
370 | etr_port0_online = etr_port1_online = 0; | |
371 | else if (strncmp(p, "port0", 5) == 0) | |
372 | etr_port0_online = 1; | |
373 | else if (strncmp(p, "port1", 5) == 0) | |
374 | etr_port1_online = 1; | |
375 | else if (strncmp(p, "on", 2) == 0) | |
376 | etr_port0_online = etr_port1_online = 1; | |
377 | return 0; | |
378 | } | |
379 | early_param("etr", early_parse_etr); | |
380 | ||
381 | enum etr_event { | |
382 | ETR_EVENT_PORT0_CHANGE, | |
383 | ETR_EVENT_PORT1_CHANGE, | |
384 | ETR_EVENT_PORT_ALERT, | |
385 | ETR_EVENT_SYNC_CHECK, | |
386 | ETR_EVENT_SWITCH_LOCAL, | |
387 | ETR_EVENT_UPDATE, | |
388 | }; | |
389 | ||
390 | enum etr_flags { | |
391 | ETR_FLAG_ENOSYS, | |
392 | ETR_FLAG_EACCES, | |
393 | ETR_FLAG_STEAI, | |
394 | }; | |
395 | ||
396 | /* | |
397 | * Valid bit combinations of the eacr register are (x = don't care): | |
398 | * e0 e1 dp p0 p1 ea es sl | |
399 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
400 | * 0 0 x 0 1 1 0 0 port 1 online | |
401 | * 0 0 x 1 0 1 0 0 port 0 online | |
402 | * 0 0 x 1 1 1 0 0 both ports online | |
403 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
404 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
405 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
406 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
407 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
408 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
409 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
410 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
411 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
412 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
413 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
414 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
415 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
416 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
417 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
418 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
419 | */ | |
420 | static struct etr_eacr etr_eacr; | |
421 | static u64 etr_tolec; /* time of last eacr update */ | |
422 | static unsigned long etr_flags; | |
423 | static struct etr_aib etr_port0; | |
424 | static int etr_port0_uptodate; | |
425 | static struct etr_aib etr_port1; | |
426 | static int etr_port1_uptodate; | |
427 | static unsigned long etr_events; | |
428 | static struct timer_list etr_timer; | |
429 | static struct tasklet_struct etr_tasklet; | |
430 | static DEFINE_PER_CPU(atomic_t, etr_sync_word); | |
431 | ||
432 | static void etr_timeout(unsigned long dummy); | |
433 | static void etr_tasklet_fn(unsigned long dummy); | |
434 | ||
435 | /* | |
436 | * The etr get_clock function. It will write the current clock value | |
437 | * to the clock pointer and return 0 if the clock is in sync with the | |
438 | * external time source. If the clock mode is local it will return | |
439 | * -ENOSYS and -EAGAIN if the clock is not in sync with the external | |
440 | * reference. This function is what ETR is all about.. | |
441 | */ | |
442 | int get_sync_clock(unsigned long long *clock) | |
443 | { | |
444 | atomic_t *sw_ptr; | |
445 | unsigned int sw0, sw1; | |
446 | ||
447 | sw_ptr = &get_cpu_var(etr_sync_word); | |
448 | sw0 = atomic_read(sw_ptr); | |
449 | *clock = get_clock(); | |
450 | sw1 = atomic_read(sw_ptr); | |
451 | put_cpu_var(etr_sync_sync); | |
452 | if (sw0 == sw1 && (sw0 & 0x80000000U)) | |
453 | /* Success: time is in sync. */ | |
454 | return 0; | |
455 | if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) | |
456 | return -ENOSYS; | |
457 | if (test_bit(ETR_FLAG_EACCES, &etr_flags)) | |
458 | return -EACCES; | |
459 | return -EAGAIN; | |
460 | } | |
461 | EXPORT_SYMBOL(get_sync_clock); | |
462 | ||
463 | /* | |
464 | * Make get_sync_clock return -EAGAIN. | |
465 | */ | |
466 | static void etr_disable_sync_clock(void *dummy) | |
467 | { | |
468 | atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); | |
469 | /* | |
470 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
471 | * fail until the sync bit is turned back on. In addition | |
472 | * increase the "sequence" counter to avoid the race of an | |
473 | * etr event and the complete recovery against get_sync_clock. | |
474 | */ | |
475 | atomic_clear_mask(0x80000000, sw_ptr); | |
476 | atomic_inc(sw_ptr); | |
477 | } | |
478 | ||
479 | /* | |
480 | * Make get_sync_clock return 0 again. | |
481 | * Needs to be called from a context disabled for preemption. | |
482 | */ | |
483 | static void etr_enable_sync_clock(void) | |
484 | { | |
485 | atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word); | |
486 | atomic_set_mask(0x80000000, sw_ptr); | |
487 | } | |
488 | ||
489 | /* | |
490 | * Reset ETR attachment. | |
491 | */ | |
492 | static void etr_reset(void) | |
493 | { | |
494 | etr_eacr = (struct etr_eacr) { | |
495 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
496 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
497 | .es = 0, .sl = 0 }; | |
498 | if (etr_setr(&etr_eacr) == 0) | |
499 | etr_tolec = get_clock(); | |
500 | else { | |
501 | set_bit(ETR_FLAG_ENOSYS, &etr_flags); | |
502 | if (etr_port0_online || etr_port1_online) { | |
503 | printk(KERN_WARNING "Running on non ETR capable " | |
504 | "machine, only local mode available.\n"); | |
505 | etr_port0_online = etr_port1_online = 0; | |
506 | } | |
507 | } | |
508 | } | |
509 | ||
510 | static void etr_init(void) | |
511 | { | |
512 | struct etr_aib aib; | |
513 | ||
514 | if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) | |
515 | return; | |
516 | /* Check if this machine has the steai instruction. */ | |
517 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
518 | set_bit(ETR_FLAG_STEAI, &etr_flags); | |
519 | setup_timer(&etr_timer, etr_timeout, 0UL); | |
520 | tasklet_init(&etr_tasklet, etr_tasklet_fn, 0); | |
521 | if (!etr_port0_online && !etr_port1_online) | |
522 | set_bit(ETR_FLAG_EACCES, &etr_flags); | |
523 | if (etr_port0_online) { | |
524 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
525 | tasklet_hi_schedule(&etr_tasklet); | |
526 | } | |
527 | if (etr_port1_online) { | |
528 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
529 | tasklet_hi_schedule(&etr_tasklet); | |
530 | } | |
531 | } | |
532 | ||
533 | /* | |
534 | * Two sorts of ETR machine checks. The architecture reads: | |
535 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
536 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
537 | * disabled interruption request is indicated and is cleared". | |
538 | * Which means that we can get etr_switch_to_local events from the machine | |
539 | * check handler although the interruption condition is disabled. Lovely.. | |
540 | */ | |
541 | ||
542 | /* | |
543 | * Switch to local machine check. This is called when the last usable | |
544 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
545 | */ | |
546 | void etr_switch_to_local(void) | |
547 | { | |
548 | if (!etr_eacr.sl) | |
549 | return; | |
550 | etr_disable_sync_clock(NULL); | |
551 | set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); | |
552 | tasklet_hi_schedule(&etr_tasklet); | |
553 | } | |
554 | ||
555 | /* | |
556 | * ETR sync check machine check. This is called when the ETR OTE and the | |
557 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
558 | * After a ETR sync check the clock is not in sync. The machine check | |
559 | * is broadcasted to all cpus at the same time. | |
560 | */ | |
561 | void etr_sync_check(void) | |
562 | { | |
563 | if (!etr_eacr.es) | |
564 | return; | |
565 | etr_disable_sync_clock(NULL); | |
566 | set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); | |
567 | tasklet_hi_schedule(&etr_tasklet); | |
568 | } | |
569 | ||
570 | /* | |
571 | * ETR external interrupt. There are two causes: | |
572 | * 1) port state change, check the usability of the port | |
573 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
574 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
575 | * or ETR-data word 4 (edf4) has changed. | |
576 | */ | |
577 | static void etr_ext_handler(__u16 code) | |
578 | { | |
579 | struct etr_interruption_parameter *intparm = | |
580 | (struct etr_interruption_parameter *) &S390_lowcore.ext_params; | |
581 | ||
582 | if (intparm->pc0) | |
583 | /* ETR port 0 state change. */ | |
584 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
585 | if (intparm->pc1) | |
586 | /* ETR port 1 state change. */ | |
587 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
588 | if (intparm->eai) | |
589 | /* | |
590 | * ETR port alert on either port 0, 1 or both. | |
591 | * Both ports are not up-to-date now. | |
592 | */ | |
593 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
594 | tasklet_hi_schedule(&etr_tasklet); | |
595 | } | |
596 | ||
597 | static void etr_timeout(unsigned long dummy) | |
598 | { | |
599 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
600 | tasklet_hi_schedule(&etr_tasklet); | |
601 | } | |
602 | ||
603 | /* | |
604 | * Check if the etr mode is pss. | |
605 | */ | |
606 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
607 | { | |
608 | return eacr.es && !eacr.sl; | |
609 | } | |
610 | ||
611 | /* | |
612 | * Check if the etr mode is etr. | |
613 | */ | |
614 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
615 | { | |
616 | return eacr.es && eacr.sl; | |
617 | } | |
618 | ||
619 | /* | |
620 | * Check if the port can be used for TOD synchronization. | |
621 | * For PPS mode the port has to receive OTEs. For ETR mode | |
622 | * the port has to receive OTEs, the ETR stepping bit has to | |
623 | * be zero and the validity bits for data frame 1, 2, and 3 | |
624 | * have to be 1. | |
625 | */ | |
626 | static int etr_port_valid(struct etr_aib *aib, int port) | |
627 | { | |
628 | unsigned int psc; | |
629 | ||
630 | /* Check that this port is receiving OTEs. */ | |
631 | if (aib->tsp == 0) | |
632 | return 0; | |
633 | ||
634 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
635 | if (psc == etr_lpsc_pps_mode) | |
636 | return 1; | |
637 | if (psc == etr_lpsc_operational_step) | |
638 | return !aib->esw.y && aib->slsw.v1 && | |
639 | aib->slsw.v2 && aib->slsw.v3; | |
640 | return 0; | |
641 | } | |
642 | ||
643 | /* | |
644 | * Check if two ports are on the same network. | |
645 | */ | |
646 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
647 | { | |
648 | // FIXME: any other fields we have to compare? | |
649 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
650 | } | |
651 | ||
652 | /* | |
653 | * Wrapper for etr_stei that converts physical port states | |
654 | * to logical port states to be consistent with the output | |
655 | * of stetr (see etr_psc vs. etr_lpsc). | |
656 | */ | |
657 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
658 | { | |
659 | BUG_ON(etr_steai(aib, func) != 0); | |
660 | /* Convert port state to logical port state. */ | |
661 | if (aib->esw.psc0 == 1) | |
662 | aib->esw.psc0 = 2; | |
663 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
664 | aib->esw.psc0 = 1; | |
665 | if (aib->esw.psc1 == 1) | |
666 | aib->esw.psc1 = 2; | |
667 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
668 | aib->esw.psc1 = 1; | |
669 | } | |
670 | ||
671 | /* | |
672 | * Check if the aib a2 is still connected to the same attachment as | |
673 | * aib a1, the etv values differ by one and a2 is valid. | |
674 | */ | |
675 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
676 | { | |
677 | int state_a1, state_a2; | |
678 | ||
679 | /* Paranoia check: e0/e1 should better be the same. */ | |
680 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
681 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
682 | return 0; | |
683 | ||
684 | /* Still connected to the same etr ? */ | |
685 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
686 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
687 | if (state_a1 == etr_lpsc_operational_step) { | |
688 | if (state_a2 != etr_lpsc_operational_step || | |
689 | a1->edf1.net_id != a2->edf1.net_id || | |
690 | a1->edf1.etr_id != a2->edf1.etr_id || | |
691 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
692 | return 0; | |
693 | } else if (state_a2 != etr_lpsc_pps_mode) | |
694 | return 0; | |
695 | ||
696 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
697 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
698 | return 0; | |
699 | ||
700 | if (!etr_port_valid(a2, p)) | |
701 | return 0; | |
702 | ||
703 | return 1; | |
704 | } | |
705 | ||
706 | /* | |
707 | * The time is "clock". xtime is what we think the time is. | |
708 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
709 | * "delay" is an approximation how long the synchronization took. If | |
710 | * the time correction is positive, then "delay" is subtracted from | |
711 | * the time difference and only the remaining part is passed to ntp. | |
712 | */ | |
713 | static void etr_adjust_time(unsigned long long clock, unsigned long long delay) | |
714 | { | |
715 | unsigned long long delta, ticks; | |
716 | struct timex adjust; | |
717 | ||
718 | /* | |
719 | * We don't have to take the xtime lock because the cpu | |
720 | * executing etr_adjust_time is running disabled in | |
721 | * tasklet context and all other cpus are looping in | |
722 | * etr_sync_cpu_start. | |
723 | */ | |
724 | if (clock > xtime_cc) { | |
725 | /* It is later than we thought. */ | |
726 | delta = ticks = clock - xtime_cc; | |
727 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
728 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
729 | init_timer_cc = init_timer_cc + delta; | |
730 | jiffies_timer_cc = jiffies_timer_cc + delta; | |
731 | xtime_cc = xtime_cc + delta; | |
732 | adjust.offset = ticks * (1000000 / HZ); | |
733 | } else { | |
734 | /* It is earlier than we thought. */ | |
735 | delta = ticks = xtime_cc - clock; | |
736 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
737 | init_timer_cc = init_timer_cc - delta; | |
738 | jiffies_timer_cc = jiffies_timer_cc - delta; | |
739 | xtime_cc = xtime_cc - delta; | |
740 | adjust.offset = -ticks * (1000000 / HZ); | |
741 | } | |
742 | if (adjust.offset != 0) { | |
743 | printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n", | |
744 | adjust.offset); | |
745 | adjust.modes = ADJ_OFFSET_SINGLESHOT; | |
746 | do_adjtimex(&adjust); | |
747 | } | |
748 | } | |
749 | ||
6c732de2 | 750 | #ifdef CONFIG_SMP |
d54853ef MS |
751 | static void etr_sync_cpu_start(void *dummy) |
752 | { | |
753 | int *in_sync = dummy; | |
754 | ||
755 | etr_enable_sync_clock(); | |
756 | /* | |
757 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
758 | * is called on all other cpus while the TOD clocks is stopped. | |
759 | * __udelay will stop the cpu on an enabled wait psw until the | |
760 | * TOD is running again. | |
761 | */ | |
6c732de2 | 762 | while (*in_sync == 0) { |
d54853ef | 763 | __udelay(1); |
6c732de2 HC |
764 | /* |
765 | * A different cpu changes *in_sync. Therefore use | |
766 | * barrier() to force memory access. | |
767 | */ | |
768 | barrier(); | |
769 | } | |
d54853ef MS |
770 | if (*in_sync != 1) |
771 | /* Didn't work. Clear per-cpu in sync bit again. */ | |
772 | etr_disable_sync_clock(NULL); | |
773 | /* | |
774 | * This round of TOD syncing is done. Set the clock comparator | |
775 | * to the next tick and let the processor continue. | |
776 | */ | |
777 | setup_jiffy_timer(); | |
778 | } | |
779 | ||
780 | static void etr_sync_cpu_end(void *dummy) | |
781 | { | |
782 | } | |
6c732de2 | 783 | #endif /* CONFIG_SMP */ |
d54853ef MS |
784 | |
785 | /* | |
786 | * Sync the TOD clock using the port refered to by aibp. This port | |
787 | * has to be enabled and the other port has to be disabled. The | |
788 | * last eacr update has to be more than 1.6 seconds in the past. | |
789 | */ | |
790 | static int etr_sync_clock(struct etr_aib *aib, int port) | |
791 | { | |
792 | struct etr_aib *sync_port; | |
793 | unsigned long long clock, delay; | |
794 | int in_sync, follows; | |
795 | int rc; | |
796 | ||
797 | /* Check if the current aib is adjacent to the sync port aib. */ | |
798 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
799 | follows = etr_aib_follows(sync_port, aib, port); | |
800 | memcpy(sync_port, aib, sizeof(*aib)); | |
801 | if (!follows) | |
802 | return -EAGAIN; | |
803 | ||
804 | /* | |
805 | * Catch all other cpus and make them wait until we have | |
806 | * successfully synced the clock. smp_call_function will | |
807 | * return after all other cpus are in etr_sync_cpu_start. | |
808 | */ | |
809 | in_sync = 0; | |
810 | preempt_disable(); | |
811 | smp_call_function(etr_sync_cpu_start,&in_sync,0,0); | |
812 | local_irq_disable(); | |
813 | etr_enable_sync_clock(); | |
814 | ||
815 | /* Set clock to next OTE. */ | |
816 | __ctl_set_bit(14, 21); | |
817 | __ctl_set_bit(0, 29); | |
818 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
819 | if (set_clock(clock) == 0) { | |
820 | __udelay(1); /* Wait for the clock to start. */ | |
821 | __ctl_clear_bit(0, 29); | |
822 | __ctl_clear_bit(14, 21); | |
823 | etr_stetr(aib); | |
824 | /* Adjust Linux timing variables. */ | |
825 | delay = (unsigned long long) | |
826 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
827 | etr_adjust_time(clock, delay); | |
828 | setup_jiffy_timer(); | |
829 | /* Verify that the clock is properly set. */ | |
830 | if (!etr_aib_follows(sync_port, aib, port)) { | |
831 | /* Didn't work. */ | |
832 | etr_disable_sync_clock(NULL); | |
833 | in_sync = -EAGAIN; | |
834 | rc = -EAGAIN; | |
835 | } else { | |
836 | in_sync = 1; | |
837 | rc = 0; | |
838 | } | |
839 | } else { | |
840 | /* Could not set the clock ?!? */ | |
841 | __ctl_clear_bit(0, 29); | |
842 | __ctl_clear_bit(14, 21); | |
843 | etr_disable_sync_clock(NULL); | |
844 | in_sync = -EAGAIN; | |
845 | rc = -EAGAIN; | |
846 | } | |
847 | local_irq_enable(); | |
848 | smp_call_function(etr_sync_cpu_end,NULL,0,0); | |
849 | preempt_enable(); | |
850 | return rc; | |
851 | } | |
852 | ||
853 | /* | |
854 | * Handle the immediate effects of the different events. | |
855 | * The port change event is used for online/offline changes. | |
856 | */ | |
857 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
858 | { | |
859 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
860 | eacr.es = 0; | |
861 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
862 | eacr.es = eacr.sl = 0; | |
863 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
864 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
865 | ||
866 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
867 | if (eacr.e0) | |
868 | /* | |
869 | * Port change of an enabled port. We have to | |
870 | * assume that this can have caused an stepping | |
871 | * port switch. | |
872 | */ | |
873 | etr_tolec = get_clock(); | |
874 | eacr.p0 = etr_port0_online; | |
875 | if (!eacr.p0) | |
876 | eacr.e0 = 0; | |
877 | etr_port0_uptodate = 0; | |
878 | } | |
879 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
880 | if (eacr.e1) | |
881 | /* | |
882 | * Port change of an enabled port. We have to | |
883 | * assume that this can have caused an stepping | |
884 | * port switch. | |
885 | */ | |
886 | etr_tolec = get_clock(); | |
887 | eacr.p1 = etr_port1_online; | |
888 | if (!eacr.p1) | |
889 | eacr.e1 = 0; | |
890 | etr_port1_uptodate = 0; | |
891 | } | |
892 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
893 | return eacr; | |
894 | } | |
895 | ||
896 | /* | |
897 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
898 | * one of the ports needs an update. | |
899 | */ | |
900 | static void etr_set_tolec_timeout(unsigned long long now) | |
901 | { | |
902 | unsigned long micros; | |
903 | ||
904 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
905 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
906 | return; | |
907 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
908 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
909 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
910 | } | |
911 | ||
912 | /* | |
913 | * Set up a time that expires after 1/2 second. | |
914 | */ | |
915 | static void etr_set_sync_timeout(void) | |
916 | { | |
917 | mod_timer(&etr_timer, jiffies + HZ/2); | |
918 | } | |
919 | ||
920 | /* | |
921 | * Update the aib information for one or both ports. | |
922 | */ | |
923 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
924 | struct etr_eacr eacr) | |
925 | { | |
926 | /* With both ports disabled the aib information is useless. */ | |
927 | if (!eacr.e0 && !eacr.e1) | |
928 | return eacr; | |
929 | ||
930 | /* Update port0 or port1 with aib stored in etr_tasklet_fn. */ | |
931 | if (aib->esw.q == 0) { | |
932 | /* Information for port 0 stored. */ | |
933 | if (eacr.p0 && !etr_port0_uptodate) { | |
934 | etr_port0 = *aib; | |
935 | if (etr_port0_online) | |
936 | etr_port0_uptodate = 1; | |
937 | } | |
938 | } else { | |
939 | /* Information for port 1 stored. */ | |
940 | if (eacr.p1 && !etr_port1_uptodate) { | |
941 | etr_port1 = *aib; | |
942 | if (etr_port0_online) | |
943 | etr_port1_uptodate = 1; | |
944 | } | |
945 | } | |
946 | ||
947 | /* | |
948 | * Do not try to get the alternate port aib if the clock | |
949 | * is not in sync yet. | |
950 | */ | |
951 | if (!eacr.es) | |
952 | return eacr; | |
953 | ||
954 | /* | |
955 | * If steai is available we can get the information about | |
956 | * the other port immediately. If only stetr is available the | |
957 | * data-port bit toggle has to be used. | |
958 | */ | |
959 | if (test_bit(ETR_FLAG_STEAI, &etr_flags)) { | |
960 | if (eacr.p0 && !etr_port0_uptodate) { | |
961 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
962 | etr_port0_uptodate = 1; | |
963 | } | |
964 | if (eacr.p1 && !etr_port1_uptodate) { | |
965 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
966 | etr_port1_uptodate = 1; | |
967 | } | |
968 | } else { | |
969 | /* | |
970 | * One port was updated above, if the other | |
971 | * port is not uptodate toggle dp bit. | |
972 | */ | |
973 | if ((eacr.p0 && !etr_port0_uptodate) || | |
974 | (eacr.p1 && !etr_port1_uptodate)) | |
975 | eacr.dp ^= 1; | |
976 | else | |
977 | eacr.dp = 0; | |
978 | } | |
979 | return eacr; | |
980 | } | |
981 | ||
982 | /* | |
983 | * Write new etr control register if it differs from the current one. | |
984 | * Return 1 if etr_tolec has been updated as well. | |
985 | */ | |
986 | static void etr_update_eacr(struct etr_eacr eacr) | |
987 | { | |
988 | int dp_changed; | |
989 | ||
990 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
991 | /* No change, return. */ | |
992 | return; | |
993 | /* | |
994 | * The disable of an active port of the change of the data port | |
995 | * bit can/will cause a change in the data port. | |
996 | */ | |
997 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
998 | (etr_eacr.dp ^ eacr.dp) != 0; | |
999 | etr_eacr = eacr; | |
1000 | etr_setr(&etr_eacr); | |
1001 | if (dp_changed) | |
1002 | etr_tolec = get_clock(); | |
1003 | } | |
1004 | ||
1005 | /* | |
1006 | * ETR tasklet. In this function you'll find the main logic. In | |
1007 | * particular this is the only function that calls etr_update_eacr(), | |
1008 | * it "controls" the etr control register. | |
1009 | */ | |
1010 | static void etr_tasklet_fn(unsigned long dummy) | |
1011 | { | |
1012 | unsigned long long now; | |
1013 | struct etr_eacr eacr; | |
1014 | struct etr_aib aib; | |
1015 | int sync_port; | |
1016 | ||
1017 | /* Create working copy of etr_eacr. */ | |
1018 | eacr = etr_eacr; | |
1019 | ||
1020 | /* Check for the different events and their immediate effects. */ | |
1021 | eacr = etr_handle_events(eacr); | |
1022 | ||
1023 | /* Check if ETR is supposed to be active. */ | |
1024 | eacr.ea = eacr.p0 || eacr.p1; | |
1025 | if (!eacr.ea) { | |
1026 | /* Both ports offline. Reset everything. */ | |
1027 | eacr.dp = eacr.es = eacr.sl = 0; | |
1028 | on_each_cpu(etr_disable_sync_clock, NULL, 0, 1); | |
1029 | del_timer_sync(&etr_timer); | |
1030 | etr_update_eacr(eacr); | |
1031 | set_bit(ETR_FLAG_EACCES, &etr_flags); | |
1032 | return; | |
1033 | } | |
1034 | ||
1035 | /* Store aib to get the current ETR status word. */ | |
1036 | BUG_ON(etr_stetr(&aib) != 0); | |
1037 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
1038 | now = get_clock(); | |
1039 | ||
1040 | /* | |
1041 | * Update the port information if the last stepping port change | |
1042 | * or data port change is older than 1.6 seconds. | |
1043 | */ | |
1044 | if (now >= etr_tolec + (1600000 << 12)) | |
1045 | eacr = etr_handle_update(&aib, eacr); | |
1046 | ||
1047 | /* | |
1048 | * Select ports to enable. The prefered synchronization mode is PPS. | |
1049 | * If a port can be enabled depends on a number of things: | |
1050 | * 1) The port needs to be online and uptodate. A port is not | |
1051 | * disabled just because it is not uptodate, but it is only | |
1052 | * enabled if it is uptodate. | |
1053 | * 2) The port needs to have the same mode (pps / etr). | |
1054 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1055 | * 4) To enable the second port the clock needs to be in sync. | |
1056 | * 5) If both ports are useable and are ETR ports, the network id | |
1057 | * has to be the same. | |
1058 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1059 | */ | |
1060 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1061 | eacr.sl = 0; | |
1062 | eacr.e0 = 1; | |
1063 | if (!etr_mode_is_pps(etr_eacr)) | |
1064 | eacr.es = 0; | |
1065 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1066 | eacr.e1 = 0; | |
1067 | // FIXME: uptodate checks ? | |
1068 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1069 | eacr.e1 = 1; | |
1070 | sync_port = (etr_port0_uptodate && | |
1071 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
1072 | clear_bit(ETR_FLAG_EACCES, &etr_flags); | |
1073 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { | |
1074 | eacr.sl = 0; | |
1075 | eacr.e0 = 0; | |
1076 | eacr.e1 = 1; | |
1077 | if (!etr_mode_is_pps(etr_eacr)) | |
1078 | eacr.es = 0; | |
1079 | sync_port = (etr_port1_uptodate && | |
1080 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
1081 | clear_bit(ETR_FLAG_EACCES, &etr_flags); | |
1082 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { | |
1083 | eacr.sl = 1; | |
1084 | eacr.e0 = 1; | |
1085 | if (!etr_mode_is_etr(etr_eacr)) | |
1086 | eacr.es = 0; | |
1087 | if (!eacr.es || !eacr.p1 || | |
1088 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1089 | eacr.e1 = 0; | |
1090 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1091 | etr_compare_network(&etr_port0, &etr_port1)) | |
1092 | eacr.e1 = 1; | |
1093 | sync_port = (etr_port0_uptodate && | |
1094 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
1095 | clear_bit(ETR_FLAG_EACCES, &etr_flags); | |
1096 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { | |
1097 | eacr.sl = 1; | |
1098 | eacr.e0 = 0; | |
1099 | eacr.e1 = 1; | |
1100 | if (!etr_mode_is_etr(etr_eacr)) | |
1101 | eacr.es = 0; | |
1102 | sync_port = (etr_port1_uptodate && | |
1103 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
1104 | clear_bit(ETR_FLAG_EACCES, &etr_flags); | |
1105 | } else { | |
1106 | /* Both ports not usable. */ | |
1107 | eacr.es = eacr.sl = 0; | |
1108 | sync_port = -1; | |
1109 | set_bit(ETR_FLAG_EACCES, &etr_flags); | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * If the clock is in sync just update the eacr and return. | |
1114 | * If there is no valid sync port wait for a port update. | |
1115 | */ | |
1116 | if (eacr.es || sync_port < 0) { | |
1117 | etr_update_eacr(eacr); | |
1118 | etr_set_tolec_timeout(now); | |
1119 | return; | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * Prepare control register for clock syncing | |
1124 | * (reset data port bit, set sync check control. | |
1125 | */ | |
1126 | eacr.dp = 0; | |
1127 | eacr.es = 1; | |
1128 | ||
1129 | /* | |
1130 | * Update eacr and try to synchronize the clock. If the update | |
1131 | * of eacr caused a stepping port switch (or if we have to | |
1132 | * assume that a stepping port switch has occured) or the | |
1133 | * clock syncing failed, reset the sync check control bit | |
1134 | * and set up a timer to try again after 0.5 seconds | |
1135 | */ | |
1136 | etr_update_eacr(eacr); | |
1137 | if (now < etr_tolec + (1600000 << 12) || | |
1138 | etr_sync_clock(&aib, sync_port) != 0) { | |
1139 | /* Sync failed. Try again in 1/2 second. */ | |
1140 | eacr.es = 0; | |
1141 | etr_update_eacr(eacr); | |
1142 | etr_set_sync_timeout(); | |
1143 | } else | |
1144 | etr_set_tolec_timeout(now); | |
1145 | } | |
1146 | ||
1147 | /* | |
1148 | * Sysfs interface functions | |
1149 | */ | |
1150 | static struct sysdev_class etr_sysclass = { | |
1151 | set_kset_name("etr") | |
1152 | }; | |
1153 | ||
1154 | static struct sys_device etr_port0_dev = { | |
1155 | .id = 0, | |
1156 | .cls = &etr_sysclass, | |
1157 | }; | |
1158 | ||
1159 | static struct sys_device etr_port1_dev = { | |
1160 | .id = 1, | |
1161 | .cls = &etr_sysclass, | |
1162 | }; | |
1163 | ||
1164 | /* | |
1165 | * ETR class attributes | |
1166 | */ | |
1167 | static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) | |
1168 | { | |
1169 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1170 | } | |
1171 | ||
1172 | static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); | |
1173 | ||
1174 | static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) | |
1175 | { | |
1176 | char *mode_str; | |
1177 | ||
1178 | if (etr_mode_is_pps(etr_eacr)) | |
1179 | mode_str = "pps"; | |
1180 | else if (etr_mode_is_etr(etr_eacr)) | |
1181 | mode_str = "etr"; | |
1182 | else | |
1183 | mode_str = "local"; | |
1184 | return sprintf(buf, "%s\n", mode_str); | |
1185 | } | |
1186 | ||
1187 | static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); | |
1188 | ||
1189 | /* | |
1190 | * ETR port attributes | |
1191 | */ | |
1192 | static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) | |
1193 | { | |
1194 | if (dev == &etr_port0_dev) | |
1195 | return etr_port0_online ? &etr_port0 : NULL; | |
1196 | else | |
1197 | return etr_port1_online ? &etr_port1 : NULL; | |
1198 | } | |
1199 | ||
1200 | static ssize_t etr_online_show(struct sys_device *dev, char *buf) | |
1201 | { | |
1202 | unsigned int online; | |
1203 | ||
1204 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1205 | return sprintf(buf, "%i\n", online); | |
1206 | } | |
1207 | ||
1208 | static ssize_t etr_online_store(struct sys_device *dev, | |
1209 | const char *buf, size_t count) | |
1210 | { | |
1211 | unsigned int value; | |
1212 | ||
1213 | value = simple_strtoul(buf, NULL, 0); | |
1214 | if (value != 0 && value != 1) | |
1215 | return -EINVAL; | |
1216 | if (test_bit(ETR_FLAG_ENOSYS, &etr_flags)) | |
1217 | return -ENOSYS; | |
1218 | if (dev == &etr_port0_dev) { | |
1219 | if (etr_port0_online == value) | |
1220 | return count; /* Nothing to do. */ | |
1221 | etr_port0_online = value; | |
1222 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
1223 | tasklet_hi_schedule(&etr_tasklet); | |
1224 | } else { | |
1225 | if (etr_port1_online == value) | |
1226 | return count; /* Nothing to do. */ | |
1227 | etr_port1_online = value; | |
1228 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
1229 | tasklet_hi_schedule(&etr_tasklet); | |
1230 | } | |
1231 | return count; | |
1232 | } | |
1233 | ||
1234 | static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); | |
1235 | ||
1236 | static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf) | |
1237 | { | |
1238 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1239 | etr_eacr.e0 : etr_eacr.e1); | |
1240 | } | |
1241 | ||
1242 | static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); | |
1243 | ||
1244 | static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf) | |
1245 | { | |
1246 | if (!etr_port0_online && !etr_port1_online) | |
1247 | /* Status word is not uptodate if both ports are offline. */ | |
1248 | return -ENODATA; | |
1249 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1250 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1251 | } | |
1252 | ||
1253 | static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); | |
1254 | ||
1255 | static ssize_t etr_untuned_show(struct sys_device *dev, char *buf) | |
1256 | { | |
1257 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1258 | ||
1259 | if (!aib || !aib->slsw.v1) | |
1260 | return -ENODATA; | |
1261 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1262 | } | |
1263 | ||
1264 | static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); | |
1265 | ||
1266 | static ssize_t etr_network_id_show(struct sys_device *dev, char *buf) | |
1267 | { | |
1268 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1269 | ||
1270 | if (!aib || !aib->slsw.v1) | |
1271 | return -ENODATA; | |
1272 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1273 | } | |
1274 | ||
1275 | static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); | |
1276 | ||
1277 | static ssize_t etr_id_show(struct sys_device *dev, char *buf) | |
1278 | { | |
1279 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1280 | ||
1281 | if (!aib || !aib->slsw.v1) | |
1282 | return -ENODATA; | |
1283 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1284 | } | |
1285 | ||
1286 | static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); | |
1287 | ||
1288 | static ssize_t etr_port_number_show(struct sys_device *dev, char *buf) | |
1289 | { | |
1290 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1291 | ||
1292 | if (!aib || !aib->slsw.v1) | |
1293 | return -ENODATA; | |
1294 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1295 | } | |
1296 | ||
1297 | static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); | |
1298 | ||
1299 | static ssize_t etr_coupled_show(struct sys_device *dev, char *buf) | |
1300 | { | |
1301 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1302 | ||
1303 | if (!aib || !aib->slsw.v3) | |
1304 | return -ENODATA; | |
1305 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1306 | } | |
1307 | ||
1308 | static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); | |
1309 | ||
1310 | static ssize_t etr_local_time_show(struct sys_device *dev, char *buf) | |
1311 | { | |
1312 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1313 | ||
1314 | if (!aib || !aib->slsw.v3) | |
1315 | return -ENODATA; | |
1316 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1317 | } | |
1318 | ||
1319 | static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); | |
1320 | ||
1321 | static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf) | |
1322 | { | |
1323 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1324 | ||
1325 | if (!aib || !aib->slsw.v3) | |
1326 | return -ENODATA; | |
1327 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1328 | } | |
1329 | ||
1330 | static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); | |
1331 | ||
1332 | static struct sysdev_attribute *etr_port_attributes[] = { | |
1333 | &attr_online, | |
1334 | &attr_stepping_control, | |
1335 | &attr_state_code, | |
1336 | &attr_untuned, | |
1337 | &attr_network, | |
1338 | &attr_id, | |
1339 | &attr_port, | |
1340 | &attr_coupled, | |
1341 | &attr_local_time, | |
1342 | &attr_utc_offset, | |
1343 | NULL | |
1344 | }; | |
1345 | ||
1346 | static int __init etr_register_port(struct sys_device *dev) | |
1347 | { | |
1348 | struct sysdev_attribute **attr; | |
1349 | int rc; | |
1350 | ||
1351 | rc = sysdev_register(dev); | |
1352 | if (rc) | |
1353 | goto out; | |
1354 | for (attr = etr_port_attributes; *attr; attr++) { | |
1355 | rc = sysdev_create_file(dev, *attr); | |
1356 | if (rc) | |
1357 | goto out_unreg; | |
1358 | } | |
1359 | return 0; | |
1360 | out_unreg: | |
1361 | for (; attr >= etr_port_attributes; attr--) | |
1362 | sysdev_remove_file(dev, *attr); | |
1363 | sysdev_unregister(dev); | |
1364 | out: | |
1365 | return rc; | |
1366 | } | |
1367 | ||
1368 | static void __init etr_unregister_port(struct sys_device *dev) | |
1369 | { | |
1370 | struct sysdev_attribute **attr; | |
1371 | ||
1372 | for (attr = etr_port_attributes; *attr; attr++) | |
1373 | sysdev_remove_file(dev, *attr); | |
1374 | sysdev_unregister(dev); | |
1375 | } | |
1376 | ||
1377 | static int __init etr_init_sysfs(void) | |
1378 | { | |
1379 | int rc; | |
1380 | ||
1381 | rc = sysdev_class_register(&etr_sysclass); | |
1382 | if (rc) | |
1383 | goto out; | |
1384 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); | |
1385 | if (rc) | |
1386 | goto out_unreg_class; | |
1387 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); | |
1388 | if (rc) | |
1389 | goto out_remove_stepping_port; | |
1390 | rc = etr_register_port(&etr_port0_dev); | |
1391 | if (rc) | |
1392 | goto out_remove_stepping_mode; | |
1393 | rc = etr_register_port(&etr_port1_dev); | |
1394 | if (rc) | |
1395 | goto out_remove_port0; | |
1396 | return 0; | |
1397 | ||
1398 | out_remove_port0: | |
1399 | etr_unregister_port(&etr_port0_dev); | |
1400 | out_remove_stepping_mode: | |
1401 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); | |
1402 | out_remove_stepping_port: | |
1403 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); | |
1404 | out_unreg_class: | |
1405 | sysdev_class_unregister(&etr_sysclass); | |
1406 | out: | |
1407 | return rc; | |
1da177e4 LT |
1408 | } |
1409 | ||
d54853ef | 1410 | device_initcall(etr_init_sysfs); |