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dbd70fb4 1/*
a53c8fab 2 * Copyright IBM Corp. 2007, 2011
dbd70fb4
HC
3 * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
4 */
5
395d31d4
MS
6#define KMSG_COMPONENT "cpu"
7#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
8
83a24e32 9#include <linux/workqueue.h>
8c910580 10#include <linux/bootmem.h>
83a24e32
HC
11#include <linux/cpuset.h>
12#include <linux/device.h>
80020fbd 13#include <linux/export.h>
83a24e32 14#include <linux/kernel.h>
dbd70fb4 15#include <linux/sched.h>
105ab3d8 16#include <linux/sched/topology.h>
83a24e32 17#include <linux/delay.h>
d05d15da
HC
18#include <linux/init.h>
19#include <linux/slab.h>
dbd70fb4
HC
20#include <linux/cpu.h>
21#include <linux/smp.h>
83a24e32 22#include <linux/mm.h>
3a368f74
PH
23#include <linux/nodemask.h>
24#include <linux/node.h>
78609132 25#include <asm/sysinfo.h>
3a368f74 26#include <asm/numa.h>
dbd70fb4 27
c10fde0d
HC
28#define PTF_HORIZONTAL (0UL)
29#define PTF_VERTICAL (1UL)
30#define PTF_CHECK (2UL)
dbd70fb4 31
4cb14bc8
HC
32struct mask_info {
33 struct mask_info *next;
10d38589 34 unsigned char id;
dbd70fb4
HC
35 cpumask_t mask;
36};
37
d1e57508 38static void set_topology_timer(void);
dbd70fb4 39static void topology_work_fn(struct work_struct *work);
c30f91b6 40static struct sysinfo_15_1_x *tl_info;
dbd70fb4 41
d1e57508 42static DECLARE_WORK(topology_work, topology_work_fn);
d00aa4e7 43
3a3814c2 44/*
30fc4ca2 45 * Socket/Book linked lists and cpu_topology updates are
3a3814c2
MH
46 * protected by "sched_domains_mutex".
47 */
d1e57508 48static struct mask_info socket_info;
4cb14bc8 49static struct mask_info book_info;
adac0f1e 50static struct mask_info drawer_info;
d1e57508 51
30fc4ca2
HC
52struct cpu_topology_s390 cpu_topology[NR_CPUS];
53EXPORT_SYMBOL_GPL(cpu_topology);
83a24e32 54
8c910580
HC
55cpumask_t cpus_with_topology;
56
4cb14bc8 57static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
dbd70fb4 58{
dbd70fb4
HC
59 cpumask_t mask;
60
d1e57508 61 cpumask_copy(&mask, cpumask_of(cpu));
68cc795d 62 if (!MACHINE_HAS_TOPOLOGY)
0b52783d 63 return mask;
d1e57508
HC
64 for (; info; info = info->next) {
65 if (cpumask_test_cpu(cpu, &info->mask))
66 return info->mask;
0b52783d 67 }
dbd70fb4
HC
68 return mask;
69}
70
10ad34bc
MS
71static cpumask_t cpu_thread_map(unsigned int cpu)
72{
73 cpumask_t mask;
74 int i;
75
76 cpumask_copy(&mask, cpumask_of(cpu));
68cc795d 77 if (!MACHINE_HAS_TOPOLOGY)
10ad34bc
MS
78 return mask;
79 cpu -= cpu % (smp_cpu_mtid + 1);
80 for (i = 0; i <= smp_cpu_mtid; i++)
81 if (cpu_present(cpu + i))
82 cpumask_set_cpu(cpu + i, &mask);
83 return mask;
84}
85
86d18a55
HC
86static void add_cpus_to_mask(struct topology_core *tl_core,
87 struct mask_info *drawer,
88 struct mask_info *book,
89 struct mask_info *socket)
dbd70fb4 90{
439eb131 91 struct cpu_topology_s390 *topo;
10ad34bc 92 unsigned int core;
dbd70fb4 93
10ad34bc
MS
94 for_each_set_bit(core, &tl_core->mask[0], TOPOLOGY_CORE_BITS) {
95 unsigned int rcore;
96 int lcpu, i;
dbd70fb4 97
10ad34bc
MS
98 rcore = TOPOLOGY_CORE_BITS - 1 - core + tl_core->origin;
99 lcpu = smp_find_processor_id(rcore << smp_cpu_mt_shift);
d1e57508
HC
100 if (lcpu < 0)
101 continue;
10ad34bc 102 for (i = 0; i <= smp_cpu_mtid; i++) {
30fc4ca2 103 topo = &cpu_topology[lcpu + i];
adac0f1e 104 topo->drawer_id = drawer->id;
439eb131 105 topo->book_id = book->id;
86d18a55 106 topo->socket_id = socket->id;
439eb131
HC
107 topo->core_id = rcore;
108 topo->thread_id = lcpu + i;
adac0f1e 109 cpumask_set_cpu(lcpu + i, &drawer->mask);
10ad34bc
MS
110 cpumask_set_cpu(lcpu + i, &book->mask);
111 cpumask_set_cpu(lcpu + i, &socket->mask);
8c910580 112 cpumask_set_cpu(lcpu + i, &cpus_with_topology);
10ad34bc 113 smp_cpu_set_polarization(lcpu + i, tl_core->pp);
dbd70fb4
HC
114 }
115 }
116}
117
4cb14bc8 118static void clear_masks(void)
dbd70fb4 119{
4cb14bc8 120 struct mask_info *info;
dbd70fb4 121
d1e57508 122 info = &socket_info;
4cb14bc8 123 while (info) {
0f1959f5 124 cpumask_clear(&info->mask);
4cb14bc8
HC
125 info = info->next;
126 }
4cb14bc8
HC
127 info = &book_info;
128 while (info) {
0f1959f5 129 cpumask_clear(&info->mask);
4cb14bc8 130 info = info->next;
dbd70fb4 131 }
adac0f1e
HC
132 info = &drawer_info;
133 while (info) {
134 cpumask_clear(&info->mask);
135 info = info->next;
136 }
dbd70fb4
HC
137}
138
c30f91b6 139static union topology_entry *next_tle(union topology_entry *tle)
dbd70fb4 140{
c30f91b6 141 if (!tle->nl)
10ad34bc 142 return (union topology_entry *)((struct topology_core *)tle + 1);
c30f91b6 143 return (union topology_entry *)((struct topology_container *)tle + 1);
dbd70fb4
HC
144}
145
86d18a55 146static void tl_to_masks(struct sysinfo_15_1_x *info)
dbd70fb4 147{
d1e57508 148 struct mask_info *socket = &socket_info;
83a24e32 149 struct mask_info *book = &book_info;
adac0f1e 150 struct mask_info *drawer = &drawer_info;
c30f91b6 151 union topology_entry *tle, *end;
4cb14bc8 152
86d18a55 153 clear_masks();
c10fde0d 154 tle = info->tle;
c30f91b6 155 end = (union topology_entry *)((unsigned long)info + info->length);
dbd70fb4
HC
156 while (tle < end) {
157 switch (tle->nl) {
adac0f1e
HC
158 case 3:
159 drawer = drawer->next;
160 drawer->id = tle->container.id;
161 break;
dbd70fb4 162 case 2:
4cb14bc8
HC
163 book = book->next;
164 book->id = tle->container.id;
dbd70fb4
HC
165 break;
166 case 1:
d1e57508
HC
167 socket = socket->next;
168 socket->id = tle->container.id;
dbd70fb4
HC
169 break;
170 case 0:
86d18a55 171 add_cpus_to_mask(&tle->cpu, drawer, book, socket);
4baeb964
HC
172 break;
173 default:
174 clear_masks();
175 return;
176 }
177 tle = next_tle(tle);
178 }
179}
180
c10fde0d
HC
181static void topology_update_polarization_simple(void)
182{
183 int cpu;
184
185 mutex_lock(&smp_cpu_state_mutex);
5439050f 186 for_each_possible_cpu(cpu)
50ab9a9a 187 smp_cpu_set_polarization(cpu, POLARIZATION_HRZ);
c10fde0d
HC
188 mutex_unlock(&smp_cpu_state_mutex);
189}
190
191static int ptf(unsigned long fc)
dbd70fb4
HC
192{
193 int rc;
194
195 asm volatile(
196 " .insn rre,0xb9a20000,%1,%1\n"
197 " ipm %0\n"
198 " srl %0,28\n"
199 : "=d" (rc)
c10fde0d
HC
200 : "d" (fc) : "cc");
201 return rc;
202}
203
204int topology_set_cpu_management(int fc)
205{
83a24e32 206 int cpu, rc;
c10fde0d 207
9186d7a9 208 if (!MACHINE_HAS_TOPOLOGY)
c10fde0d
HC
209 return -EOPNOTSUPP;
210 if (fc)
211 rc = ptf(PTF_VERTICAL);
212 else
213 rc = ptf(PTF_HORIZONTAL);
214 if (rc)
215 return -EBUSY;
5439050f 216 for_each_possible_cpu(cpu)
50ab9a9a 217 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
dbd70fb4
HC
218 return rc;
219}
220
d1e57508 221static void update_cpu_masks(void)
d00aa4e7 222{
439eb131 223 struct cpu_topology_s390 *topo;
d00aa4e7
HC
224 int cpu;
225
4cb14bc8 226 for_each_possible_cpu(cpu) {
30fc4ca2 227 topo = &cpu_topology[cpu];
439eb131
HC
228 topo->thread_mask = cpu_thread_map(cpu);
229 topo->core_mask = cpu_group_map(&socket_info, cpu);
230 topo->book_mask = cpu_group_map(&book_info, cpu);
adac0f1e 231 topo->drawer_mask = cpu_group_map(&drawer_info, cpu);
d1e57508 232 if (!MACHINE_HAS_TOPOLOGY) {
439eb131
HC
233 topo->thread_id = cpu;
234 topo->core_id = cpu;
235 topo->socket_id = cpu;
236 topo->book_id = cpu;
adac0f1e 237 topo->drawer_id = cpu;
8c910580
HC
238 if (cpu_present(cpu))
239 cpumask_set_cpu(cpu, &cpus_with_topology);
d1e57508 240 }
4cb14bc8 241 }
3a368f74 242 numa_update_cpu_topology();
4cb14bc8
HC
243}
244
96f4a70d 245void store_topology(struct sysinfo_15_1_x *info)
4cb14bc8 246{
adac0f1e 247 stsi(info, 15, 1, min(topology_max_mnest, 4));
d00aa4e7
HC
248}
249
8c910580 250static int __arch_update_cpu_topology(void)
dbd70fb4 251{
c30f91b6 252 struct sysinfo_15_1_x *info = tl_info;
8c910580 253 int rc = 0;
dbd70fb4 254
8c910580 255 cpumask_clear(&cpus_with_topology);
3a368f74
PH
256 if (MACHINE_HAS_TOPOLOGY) {
257 rc = 1;
258 store_topology(info);
259 tl_to_masks(info);
c10fde0d 260 }
d1e57508 261 update_cpu_masks();
3a368f74
PH
262 if (!MACHINE_HAS_TOPOLOGY)
263 topology_update_polarization_simple();
8c910580
HC
264 return rc;
265}
266
267int arch_update_cpu_topology(void)
268{
269 struct device *dev;
270 int cpu, rc;
271
272 rc = __arch_update_cpu_topology();
dbd70fb4 273 for_each_online_cpu(cpu) {
8a25a2fd
KS
274 dev = get_cpu_device(cpu);
275 kobject_uevent(&dev->kobj, KOBJ_CHANGE);
dbd70fb4 276 }
3a368f74 277 return rc;
dbd70fb4
HC
278}
279
fd781fa2
HC
280static void topology_work_fn(struct work_struct *work)
281{
f414f5f1 282 rebuild_sched_domains();
dbd70fb4
HC
283}
284
c10fde0d
HC
285void topology_schedule_update(void)
286{
287 schedule_work(&topology_work);
288}
289
dbd70fb4
HC
290static void topology_timer_fn(unsigned long ignored)
291{
c10fde0d
HC
292 if (ptf(PTF_CHECK))
293 topology_schedule_update();
dbd70fb4
HC
294 set_topology_timer();
295}
296
d68bddb7
HC
297static struct timer_list topology_timer =
298 TIMER_DEFERRED_INITIALIZER(topology_timer_fn, 0, 0);
299
300static atomic_t topology_poll = ATOMIC_INIT(0);
301
dbd70fb4
HC
302static void set_topology_timer(void)
303{
d68bddb7
HC
304 if (atomic_add_unless(&topology_poll, -1, 0))
305 mod_timer(&topology_timer, jiffies + HZ / 10);
306 else
307 mod_timer(&topology_timer, jiffies + HZ * 60);
308}
309
310void topology_expect_change(void)
311{
312 if (!MACHINE_HAS_TOPOLOGY)
313 return;
314 /* This is racy, but it doesn't matter since it is just a heuristic.
315 * Worst case is that we poll in a higher frequency for a bit longer.
316 */
317 if (atomic_read(&topology_poll) > 60)
318 return;
319 atomic_add(60, &topology_poll);
320 set_topology_timer();
dbd70fb4
HC
321}
322
83a24e32
HC
323static int cpu_management;
324
72f31889
LT
325static ssize_t dispatching_show(struct device *dev,
326 struct device_attribute *attr,
83a24e32
HC
327 char *buf)
328{
329 ssize_t count;
330
331 mutex_lock(&smp_cpu_state_mutex);
332 count = sprintf(buf, "%d\n", cpu_management);
333 mutex_unlock(&smp_cpu_state_mutex);
334 return count;
335}
336
72f31889
LT
337static ssize_t dispatching_store(struct device *dev,
338 struct device_attribute *attr,
83a24e32
HC
339 const char *buf,
340 size_t count)
341{
342 int val, rc;
343 char delim;
344
345 if (sscanf(buf, "%d %c", &val, &delim) != 1)
346 return -EINVAL;
347 if (val != 0 && val != 1)
348 return -EINVAL;
349 rc = 0;
350 get_online_cpus();
351 mutex_lock(&smp_cpu_state_mutex);
352 if (cpu_management == val)
353 goto out;
354 rc = topology_set_cpu_management(val);
d68bddb7
HC
355 if (rc)
356 goto out;
357 cpu_management = val;
358 topology_expect_change();
83a24e32
HC
359out:
360 mutex_unlock(&smp_cpu_state_mutex);
361 put_online_cpus();
362 return rc ? rc : count;
363}
72f31889 364static DEVICE_ATTR(dispatching, 0644, dispatching_show,
83a24e32
HC
365 dispatching_store);
366
72f31889
LT
367static ssize_t cpu_polarization_show(struct device *dev,
368 struct device_attribute *attr, char *buf)
83a24e32
HC
369{
370 int cpu = dev->id;
371 ssize_t count;
372
373 mutex_lock(&smp_cpu_state_mutex);
50ab9a9a 374 switch (smp_cpu_get_polarization(cpu)) {
83a24e32
HC
375 case POLARIZATION_HRZ:
376 count = sprintf(buf, "horizontal\n");
377 break;
378 case POLARIZATION_VL:
379 count = sprintf(buf, "vertical:low\n");
380 break;
381 case POLARIZATION_VM:
382 count = sprintf(buf, "vertical:medium\n");
383 break;
384 case POLARIZATION_VH:
385 count = sprintf(buf, "vertical:high\n");
386 break;
387 default:
388 count = sprintf(buf, "unknown\n");
389 break;
390 }
391 mutex_unlock(&smp_cpu_state_mutex);
392 return count;
393}
72f31889 394static DEVICE_ATTR(polarization, 0444, cpu_polarization_show, NULL);
83a24e32
HC
395
396static struct attribute *topology_cpu_attrs[] = {
72f31889 397 &dev_attr_polarization.attr,
83a24e32
HC
398 NULL,
399};
400
401static struct attribute_group topology_cpu_attr_group = {
402 .attrs = topology_cpu_attrs,
403};
404
405int topology_cpu_init(struct cpu *cpu)
406{
72f31889 407 return sysfs_create_group(&cpu->dev.kobj, &topology_cpu_attr_group);
83a24e32
HC
408}
409
3ddb1b75 410static const struct cpumask *cpu_thread_mask(int cpu)
10ad34bc 411{
30fc4ca2 412 return &cpu_topology[cpu].thread_mask;
10ad34bc
MS
413}
414
415
2dfd7476
VG
416const struct cpumask *cpu_coregroup_mask(int cpu)
417{
30fc4ca2 418 return &cpu_topology[cpu].core_mask;
2dfd7476
VG
419}
420
421static const struct cpumask *cpu_book_mask(int cpu)
422{
30fc4ca2 423 return &cpu_topology[cpu].book_mask;
2dfd7476
VG
424}
425
adac0f1e
HC
426static const struct cpumask *cpu_drawer_mask(int cpu)
427{
30fc4ca2 428 return &cpu_topology[cpu].drawer_mask;
adac0f1e
HC
429}
430
2dfd7476 431static struct sched_domain_topology_level s390_topology[] = {
10ad34bc 432 { cpu_thread_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
2dfd7476
VG
433 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
434 { cpu_book_mask, SD_INIT_NAME(BOOK) },
adac0f1e 435 { cpu_drawer_mask, SD_INIT_NAME(DRAWER) },
c0e5ddab 436 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
2dfd7476
VG
437 { NULL, },
438};
439
d05d15da
HC
440static void __init alloc_masks(struct sysinfo_15_1_x *info,
441 struct mask_info *mask, int offset)
442{
443 int i, nr_masks;
444
445 nr_masks = info->mag[TOPOLOGY_NR_MAG - offset];
446 for (i = 0; i < info->mnest - offset; i++)
447 nr_masks *= info->mag[TOPOLOGY_NR_MAG - offset - 1 - i];
448 nr_masks = max(nr_masks, 1);
449 for (i = 0; i < nr_masks; i++) {
8c910580 450 mask->next = memblock_virt_alloc(sizeof(*mask->next), 8);
d05d15da
HC
451 mask = mask->next;
452 }
453}
454
8c910580 455void __init topology_init_early(void)
d05d15da
HC
456{
457 struct sysinfo_15_1_x *info;
d05d15da 458
ebb299a5 459 set_sched_topology(s390_topology);
d05d15da 460 if (!MACHINE_HAS_TOPOLOGY)
8c910580 461 goto out;
8676caa4 462 tl_info = memblock_virt_alloc(PAGE_SIZE, PAGE_SIZE);
d05d15da
HC
463 info = tl_info;
464 store_topology(info);
496e59cc
HC
465 pr_info("The CPU configuration topology of the machine is: %d %d %d %d %d %d / %d\n",
466 info->mag[0], info->mag[1], info->mag[2], info->mag[3],
467 info->mag[4], info->mag[5], info->mnest);
d05d15da
HC
468 alloc_masks(info, &socket_info, 1);
469 alloc_masks(info, &book_info, 2);
adac0f1e 470 alloc_masks(info, &drawer_info, 3);
8c910580
HC
471out:
472 __arch_update_cpu_topology();
d05d15da 473}
d05d15da 474
83a24e32
HC
475static int __init topology_init(void)
476{
48e9a6c1
MS
477 if (MACHINE_HAS_TOPOLOGY)
478 set_topology_timer();
479 else
83a24e32 480 topology_update_polarization_simple();
72f31889 481 return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching);
83a24e32
HC
482}
483device_initcall(topology_init);