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Commit | Line | Data |
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dbd70fb4 | 1 | /* |
a53c8fab | 2 | * Copyright IBM Corp. 2007, 2011 |
dbd70fb4 HC |
3 | * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> |
4 | */ | |
5 | ||
395d31d4 MS |
6 | #define KMSG_COMPONENT "cpu" |
7 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
8 | ||
83a24e32 | 9 | #include <linux/workqueue.h> |
dbd70fb4 | 10 | #include <linux/bootmem.h> |
83a24e32 HC |
11 | #include <linux/cpuset.h> |
12 | #include <linux/device.h> | |
13 | #include <linux/kernel.h> | |
dbd70fb4 | 14 | #include <linux/sched.h> |
83a24e32 HC |
15 | #include <linux/init.h> |
16 | #include <linux/delay.h> | |
dbd70fb4 HC |
17 | #include <linux/cpu.h> |
18 | #include <linux/smp.h> | |
83a24e32 | 19 | #include <linux/mm.h> |
dbd70fb4 | 20 | |
c10fde0d HC |
21 | #define PTF_HORIZONTAL (0UL) |
22 | #define PTF_VERTICAL (1UL) | |
23 | #define PTF_CHECK (2UL) | |
dbd70fb4 | 24 | |
4cb14bc8 HC |
25 | struct mask_info { |
26 | struct mask_info *next; | |
10d38589 | 27 | unsigned char id; |
dbd70fb4 HC |
28 | cpumask_t mask; |
29 | }; | |
30 | ||
c9af3fa9 | 31 | static int topology_enabled = 1; |
dbd70fb4 | 32 | static void topology_work_fn(struct work_struct *work); |
c30f91b6 | 33 | static struct sysinfo_15_1_x *tl_info; |
dbd70fb4 HC |
34 | static void set_topology_timer(void); |
35 | static DECLARE_WORK(topology_work, topology_work_fn); | |
74af2831 HC |
36 | /* topology_lock protects the core linked list */ |
37 | static DEFINE_SPINLOCK(topology_lock); | |
dbd70fb4 | 38 | |
4cb14bc8 | 39 | static struct mask_info core_info; |
d00aa4e7 | 40 | cpumask_t cpu_core_map[NR_CPUS]; |
10d38589 | 41 | unsigned char cpu_core_id[NR_CPUS]; |
d00aa4e7 | 42 | |
4cb14bc8 HC |
43 | static struct mask_info book_info; |
44 | cpumask_t cpu_book_map[NR_CPUS]; | |
45 | unsigned char cpu_book_id[NR_CPUS]; | |
83a24e32 HC |
46 | |
47 | /* smp_cpu_state_mutex must be held when accessing this array */ | |
48 | int cpu_polarization[NR_CPUS]; | |
4cb14bc8 HC |
49 | |
50 | static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu) | |
dbd70fb4 | 51 | { |
dbd70fb4 HC |
52 | cpumask_t mask; |
53 | ||
0f1959f5 | 54 | cpumask_clear(&mask); |
0b52783d HC |
55 | if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) { |
56 | cpumask_copy(&mask, cpumask_of(cpu)); | |
57 | return mask; | |
58 | } | |
4cb14bc8 | 59 | while (info) { |
0f1959f5 | 60 | if (cpumask_test_cpu(cpu, &info->mask)) { |
4cb14bc8 | 61 | mask = info->mask; |
dbd70fb4 HC |
62 | break; |
63 | } | |
4cb14bc8 | 64 | info = info->next; |
dbd70fb4 | 65 | } |
0f1959f5 KM |
66 | if (cpumask_empty(&mask)) |
67 | cpumask_copy(&mask, cpumask_of(cpu)); | |
dbd70fb4 HC |
68 | return mask; |
69 | } | |
70 | ||
f6bf1a8a HC |
71 | static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu, |
72 | struct mask_info *book, | |
73 | struct mask_info *core, | |
4baeb964 | 74 | int one_core_per_cpu) |
dbd70fb4 HC |
75 | { |
76 | unsigned int cpu; | |
77 | ||
c30f91b6 HC |
78 | for (cpu = find_first_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS); |
79 | cpu < TOPOLOGY_CPU_BITS; | |
80 | cpu = find_next_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS, cpu + 1)) | |
dbd70fb4 | 81 | { |
8b646bd7 MS |
82 | unsigned int rcpu; |
83 | int lcpu; | |
dbd70fb4 | 84 | |
c30f91b6 | 85 | rcpu = TOPOLOGY_CPU_BITS - 1 - cpu + tl_cpu->origin; |
8b646bd7 MS |
86 | lcpu = smp_find_processor_id(rcpu); |
87 | if (lcpu >= 0) { | |
0f1959f5 | 88 | cpumask_set_cpu(lcpu, &book->mask); |
4cb14bc8 | 89 | cpu_book_id[lcpu] = book->id; |
0f1959f5 | 90 | cpumask_set_cpu(lcpu, &core->mask); |
4baeb964 | 91 | if (one_core_per_cpu) { |
f6bf1a8a HC |
92 | cpu_core_id[lcpu] = rcpu; |
93 | core = core->next; | |
94 | } else { | |
95 | cpu_core_id[lcpu] = core->id; | |
96 | } | |
83a24e32 | 97 | cpu_set_polarization(lcpu, tl_cpu->pp); |
dbd70fb4 HC |
98 | } |
99 | } | |
f6bf1a8a | 100 | return core; |
dbd70fb4 HC |
101 | } |
102 | ||
4cb14bc8 | 103 | static void clear_masks(void) |
dbd70fb4 | 104 | { |
4cb14bc8 | 105 | struct mask_info *info; |
dbd70fb4 | 106 | |
4cb14bc8 HC |
107 | info = &core_info; |
108 | while (info) { | |
0f1959f5 | 109 | cpumask_clear(&info->mask); |
4cb14bc8 HC |
110 | info = info->next; |
111 | } | |
4cb14bc8 HC |
112 | info = &book_info; |
113 | while (info) { | |
0f1959f5 | 114 | cpumask_clear(&info->mask); |
4cb14bc8 | 115 | info = info->next; |
dbd70fb4 HC |
116 | } |
117 | } | |
118 | ||
c30f91b6 | 119 | static union topology_entry *next_tle(union topology_entry *tle) |
dbd70fb4 | 120 | { |
c30f91b6 HC |
121 | if (!tle->nl) |
122 | return (union topology_entry *)((struct topology_cpu *)tle + 1); | |
123 | return (union topology_entry *)((struct topology_container *)tle + 1); | |
dbd70fb4 HC |
124 | } |
125 | ||
4baeb964 | 126 | static void __tl_to_cores_generic(struct sysinfo_15_1_x *info) |
dbd70fb4 | 127 | { |
4cb14bc8 | 128 | struct mask_info *core = &core_info; |
83a24e32 | 129 | struct mask_info *book = &book_info; |
c30f91b6 | 130 | union topology_entry *tle, *end; |
4cb14bc8 | 131 | |
c10fde0d | 132 | tle = info->tle; |
c30f91b6 | 133 | end = (union topology_entry *)((unsigned long)info + info->length); |
dbd70fb4 HC |
134 | while (tle < end) { |
135 | switch (tle->nl) { | |
dbd70fb4 | 136 | case 2: |
4cb14bc8 HC |
137 | book = book->next; |
138 | book->id = tle->container.id; | |
dbd70fb4 HC |
139 | break; |
140 | case 1: | |
141 | core = core->next; | |
10d38589 | 142 | core->id = tle->container.id; |
dbd70fb4 HC |
143 | break; |
144 | case 0: | |
4baeb964 | 145 | add_cpus_to_mask(&tle->cpu, book, core, 0); |
dbd70fb4 HC |
146 | break; |
147 | default: | |
4cb14bc8 | 148 | clear_masks(); |
4baeb964 | 149 | return; |
dbd70fb4 HC |
150 | } |
151 | tle = next_tle(tle); | |
152 | } | |
4baeb964 HC |
153 | } |
154 | ||
155 | static void __tl_to_cores_z10(struct sysinfo_15_1_x *info) | |
156 | { | |
157 | struct mask_info *core = &core_info; | |
158 | struct mask_info *book = &book_info; | |
159 | union topology_entry *tle, *end; | |
160 | ||
161 | tle = info->tle; | |
162 | end = (union topology_entry *)((unsigned long)info + info->length); | |
163 | while (tle < end) { | |
164 | switch (tle->nl) { | |
165 | case 1: | |
166 | book = book->next; | |
167 | book->id = tle->container.id; | |
168 | break; | |
169 | case 0: | |
170 | core = add_cpus_to_mask(&tle->cpu, book, core, 1); | |
171 | break; | |
172 | default: | |
173 | clear_masks(); | |
174 | return; | |
175 | } | |
176 | tle = next_tle(tle); | |
177 | } | |
178 | } | |
179 | ||
180 | static void tl_to_cores(struct sysinfo_15_1_x *info) | |
181 | { | |
182 | struct cpuid cpu_id; | |
183 | ||
184 | get_cpu_id(&cpu_id); | |
185 | spin_lock_irq(&topology_lock); | |
186 | clear_masks(); | |
187 | switch (cpu_id.machine) { | |
188 | case 0x2097: | |
189 | case 0x2098: | |
190 | __tl_to_cores_z10(info); | |
191 | break; | |
192 | default: | |
193 | __tl_to_cores_generic(info); | |
194 | } | |
74af2831 | 195 | spin_unlock_irq(&topology_lock); |
dbd70fb4 HC |
196 | } |
197 | ||
c10fde0d HC |
198 | static void topology_update_polarization_simple(void) |
199 | { | |
200 | int cpu; | |
201 | ||
202 | mutex_lock(&smp_cpu_state_mutex); | |
5439050f | 203 | for_each_possible_cpu(cpu) |
83a24e32 | 204 | cpu_set_polarization(cpu, POLARIZATION_HRZ); |
c10fde0d HC |
205 | mutex_unlock(&smp_cpu_state_mutex); |
206 | } | |
207 | ||
208 | static int ptf(unsigned long fc) | |
dbd70fb4 HC |
209 | { |
210 | int rc; | |
211 | ||
212 | asm volatile( | |
213 | " .insn rre,0xb9a20000,%1,%1\n" | |
214 | " ipm %0\n" | |
215 | " srl %0,28\n" | |
216 | : "=d" (rc) | |
c10fde0d HC |
217 | : "d" (fc) : "cc"); |
218 | return rc; | |
219 | } | |
220 | ||
221 | int topology_set_cpu_management(int fc) | |
222 | { | |
83a24e32 | 223 | int cpu, rc; |
c10fde0d | 224 | |
9186d7a9 | 225 | if (!MACHINE_HAS_TOPOLOGY) |
c10fde0d HC |
226 | return -EOPNOTSUPP; |
227 | if (fc) | |
228 | rc = ptf(PTF_VERTICAL); | |
229 | else | |
230 | rc = ptf(PTF_HORIZONTAL); | |
231 | if (rc) | |
232 | return -EBUSY; | |
5439050f | 233 | for_each_possible_cpu(cpu) |
83a24e32 | 234 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
dbd70fb4 HC |
235 | return rc; |
236 | } | |
237 | ||
d00aa4e7 HC |
238 | static void update_cpu_core_map(void) |
239 | { | |
4cb14bc8 | 240 | unsigned long flags; |
d00aa4e7 HC |
241 | int cpu; |
242 | ||
4cb14bc8 HC |
243 | spin_lock_irqsave(&topology_lock, flags); |
244 | for_each_possible_cpu(cpu) { | |
245 | cpu_core_map[cpu] = cpu_group_map(&core_info, cpu); | |
4cb14bc8 | 246 | cpu_book_map[cpu] = cpu_group_map(&book_info, cpu); |
4cb14bc8 HC |
247 | } |
248 | spin_unlock_irqrestore(&topology_lock, flags); | |
249 | } | |
250 | ||
96f4a70d | 251 | void store_topology(struct sysinfo_15_1_x *info) |
4cb14bc8 | 252 | { |
4cb14bc8 HC |
253 | int rc; |
254 | ||
255 | rc = stsi(info, 15, 1, 3); | |
256 | if (rc != -ENOSYS) | |
257 | return; | |
4cb14bc8 | 258 | stsi(info, 15, 1, 2); |
d00aa4e7 HC |
259 | } |
260 | ||
ee79d1bd | 261 | int arch_update_cpu_topology(void) |
dbd70fb4 | 262 | { |
c30f91b6 | 263 | struct sysinfo_15_1_x *info = tl_info; |
8a25a2fd | 264 | struct device *dev; |
dbd70fb4 HC |
265 | int cpu; |
266 | ||
9186d7a9 | 267 | if (!MACHINE_HAS_TOPOLOGY) { |
d00aa4e7 | 268 | update_cpu_core_map(); |
c10fde0d | 269 | topology_update_polarization_simple(); |
ee79d1bd | 270 | return 0; |
c10fde0d | 271 | } |
4cb14bc8 | 272 | store_topology(info); |
dbd70fb4 | 273 | tl_to_cores(info); |
d00aa4e7 | 274 | update_cpu_core_map(); |
dbd70fb4 | 275 | for_each_online_cpu(cpu) { |
8a25a2fd KS |
276 | dev = get_cpu_device(cpu); |
277 | kobject_uevent(&dev->kobj, KOBJ_CHANGE); | |
dbd70fb4 | 278 | } |
ee79d1bd | 279 | return 1; |
dbd70fb4 HC |
280 | } |
281 | ||
fd781fa2 HC |
282 | static void topology_work_fn(struct work_struct *work) |
283 | { | |
f414f5f1 | 284 | rebuild_sched_domains(); |
dbd70fb4 HC |
285 | } |
286 | ||
c10fde0d HC |
287 | void topology_schedule_update(void) |
288 | { | |
289 | schedule_work(&topology_work); | |
290 | } | |
291 | ||
dbd70fb4 HC |
292 | static void topology_timer_fn(unsigned long ignored) |
293 | { | |
c10fde0d HC |
294 | if (ptf(PTF_CHECK)) |
295 | topology_schedule_update(); | |
dbd70fb4 HC |
296 | set_topology_timer(); |
297 | } | |
298 | ||
d68bddb7 HC |
299 | static struct timer_list topology_timer = |
300 | TIMER_DEFERRED_INITIALIZER(topology_timer_fn, 0, 0); | |
301 | ||
302 | static atomic_t topology_poll = ATOMIC_INIT(0); | |
303 | ||
dbd70fb4 HC |
304 | static void set_topology_timer(void) |
305 | { | |
d68bddb7 HC |
306 | if (atomic_add_unless(&topology_poll, -1, 0)) |
307 | mod_timer(&topology_timer, jiffies + HZ / 10); | |
308 | else | |
309 | mod_timer(&topology_timer, jiffies + HZ * 60); | |
310 | } | |
311 | ||
312 | void topology_expect_change(void) | |
313 | { | |
314 | if (!MACHINE_HAS_TOPOLOGY) | |
315 | return; | |
316 | /* This is racy, but it doesn't matter since it is just a heuristic. | |
317 | * Worst case is that we poll in a higher frequency for a bit longer. | |
318 | */ | |
319 | if (atomic_read(&topology_poll) > 60) | |
320 | return; | |
321 | atomic_add(60, &topology_poll); | |
322 | set_topology_timer(); | |
dbd70fb4 HC |
323 | } |
324 | ||
2b1a61f0 | 325 | static int __init early_parse_topology(char *p) |
dbd70fb4 | 326 | { |
c9af3fa9 | 327 | if (strncmp(p, "off", 3)) |
2b1a61f0 | 328 | return 0; |
c9af3fa9 | 329 | topology_enabled = 0; |
2b1a61f0 | 330 | return 0; |
dbd70fb4 | 331 | } |
2b1a61f0 | 332 | early_param("topology", early_parse_topology); |
dbd70fb4 | 333 | |
caa04f69 SO |
334 | static void __init alloc_masks(struct sysinfo_15_1_x *info, |
335 | struct mask_info *mask, int offset) | |
4cb14bc8 HC |
336 | { |
337 | int i, nr_masks; | |
338 | ||
c30f91b6 | 339 | nr_masks = info->mag[TOPOLOGY_NR_MAG - offset]; |
4cb14bc8 | 340 | for (i = 0; i < info->mnest - offset; i++) |
c30f91b6 | 341 | nr_masks *= info->mag[TOPOLOGY_NR_MAG - offset - 1 - i]; |
4cb14bc8 HC |
342 | nr_masks = max(nr_masks, 1); |
343 | for (i = 0; i < nr_masks; i++) { | |
344 | mask->next = alloc_bootmem(sizeof(struct mask_info)); | |
345 | mask = mask->next; | |
346 | } | |
347 | } | |
348 | ||
dbd70fb4 HC |
349 | void __init s390_init_cpu_topology(void) |
350 | { | |
c30f91b6 | 351 | struct sysinfo_15_1_x *info; |
dbd70fb4 HC |
352 | int i; |
353 | ||
9186d7a9 | 354 | if (!MACHINE_HAS_TOPOLOGY) |
dbd70fb4 | 355 | return; |
dbd70fb4 | 356 | tl_info = alloc_bootmem_pages(PAGE_SIZE); |
dbd70fb4 | 357 | info = tl_info; |
4cb14bc8 | 358 | store_topology(info); |
395d31d4 | 359 | pr_info("The CPU configuration topology of the machine is:"); |
c30f91b6 | 360 | for (i = 0; i < TOPOLOGY_NR_MAG; i++) |
83a24e32 HC |
361 | printk(KERN_CONT " %d", info->mag[i]); |
362 | printk(KERN_CONT " / %d\n", info->mnest); | |
f6bf1a8a | 363 | alloc_masks(info, &core_info, 1); |
f6bf1a8a | 364 | alloc_masks(info, &book_info, 2); |
dbd70fb4 | 365 | } |
83a24e32 HC |
366 | |
367 | static int cpu_management; | |
368 | ||
72f31889 LT |
369 | static ssize_t dispatching_show(struct device *dev, |
370 | struct device_attribute *attr, | |
83a24e32 HC |
371 | char *buf) |
372 | { | |
373 | ssize_t count; | |
374 | ||
375 | mutex_lock(&smp_cpu_state_mutex); | |
376 | count = sprintf(buf, "%d\n", cpu_management); | |
377 | mutex_unlock(&smp_cpu_state_mutex); | |
378 | return count; | |
379 | } | |
380 | ||
72f31889 LT |
381 | static ssize_t dispatching_store(struct device *dev, |
382 | struct device_attribute *attr, | |
83a24e32 HC |
383 | const char *buf, |
384 | size_t count) | |
385 | { | |
386 | int val, rc; | |
387 | char delim; | |
388 | ||
389 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
390 | return -EINVAL; | |
391 | if (val != 0 && val != 1) | |
392 | return -EINVAL; | |
393 | rc = 0; | |
394 | get_online_cpus(); | |
395 | mutex_lock(&smp_cpu_state_mutex); | |
396 | if (cpu_management == val) | |
397 | goto out; | |
398 | rc = topology_set_cpu_management(val); | |
d68bddb7 HC |
399 | if (rc) |
400 | goto out; | |
401 | cpu_management = val; | |
402 | topology_expect_change(); | |
83a24e32 HC |
403 | out: |
404 | mutex_unlock(&smp_cpu_state_mutex); | |
405 | put_online_cpus(); | |
406 | return rc ? rc : count; | |
407 | } | |
72f31889 | 408 | static DEVICE_ATTR(dispatching, 0644, dispatching_show, |
83a24e32 HC |
409 | dispatching_store); |
410 | ||
72f31889 LT |
411 | static ssize_t cpu_polarization_show(struct device *dev, |
412 | struct device_attribute *attr, char *buf) | |
83a24e32 HC |
413 | { |
414 | int cpu = dev->id; | |
415 | ssize_t count; | |
416 | ||
417 | mutex_lock(&smp_cpu_state_mutex); | |
418 | switch (cpu_read_polarization(cpu)) { | |
419 | case POLARIZATION_HRZ: | |
420 | count = sprintf(buf, "horizontal\n"); | |
421 | break; | |
422 | case POLARIZATION_VL: | |
423 | count = sprintf(buf, "vertical:low\n"); | |
424 | break; | |
425 | case POLARIZATION_VM: | |
426 | count = sprintf(buf, "vertical:medium\n"); | |
427 | break; | |
428 | case POLARIZATION_VH: | |
429 | count = sprintf(buf, "vertical:high\n"); | |
430 | break; | |
431 | default: | |
432 | count = sprintf(buf, "unknown\n"); | |
433 | break; | |
434 | } | |
435 | mutex_unlock(&smp_cpu_state_mutex); | |
436 | return count; | |
437 | } | |
72f31889 | 438 | static DEVICE_ATTR(polarization, 0444, cpu_polarization_show, NULL); |
83a24e32 HC |
439 | |
440 | static struct attribute *topology_cpu_attrs[] = { | |
72f31889 | 441 | &dev_attr_polarization.attr, |
83a24e32 HC |
442 | NULL, |
443 | }; | |
444 | ||
445 | static struct attribute_group topology_cpu_attr_group = { | |
446 | .attrs = topology_cpu_attrs, | |
447 | }; | |
448 | ||
449 | int topology_cpu_init(struct cpu *cpu) | |
450 | { | |
72f31889 | 451 | return sysfs_create_group(&cpu->dev.kobj, &topology_cpu_attr_group); |
83a24e32 HC |
452 | } |
453 | ||
454 | static int __init topology_init(void) | |
455 | { | |
456 | if (!MACHINE_HAS_TOPOLOGY) { | |
457 | topology_update_polarization_simple(); | |
458 | goto out; | |
459 | } | |
83a24e32 HC |
460 | set_topology_timer(); |
461 | out: | |
462 | update_cpu_core_map(); | |
72f31889 | 463 | return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching); |
83a24e32 HC |
464 | } |
465 | device_initcall(topology_init); |