[mirror_ubuntu-eoan-kernel.git] / arch / s390 / kernel / uprobes.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  User-space Probes (UProbes) for s390
 *
 *    Copyright IBM Corp. 2014
 *    Author(s): Jan Willeke,
 */

#include <linux/uaccess.h>
#include <linux/uprobes.h>
#include <linux/compat.h>
#include <linux/kdebug.h>
#include <linux/sched/task_stack.h>

#include <asm/switch_to.h>
#include <asm/facility.h>
#include <asm/kprobes.h>
#include <asm/dis.h>
#include "entry.h"

#define	UPROBE_TRAP_NR	UINT_MAX

int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
			     unsigned long addr)
{
	return probe_is_prohibited_opcode(auprobe->insn);
}

int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
{
	if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
		return -EINVAL;
	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
		return -EINVAL;
	clear_pt_regs_flag(regs, PIF_PER_TRAP);
	auprobe->saved_per = psw_bits(regs->psw).per;
	auprobe->saved_int_code = regs->int_code;
	regs->int_code = UPROBE_TRAP_NR;
	regs->psw.addr = current->utask->xol_vaddr;
	set_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
	update_cr_regs(current);
	return 0;
}

bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
{
	struct pt_regs *regs = task_pt_regs(tsk);

	if (regs->int_code != UPROBE_TRAP_NR)
		return true;
	return false;
}

static int check_per_event(unsigned short cause, unsigned long control,
			   struct pt_regs *regs)
{
	if (!(regs->psw.mask & PSW_MASK_PER))
		return 0;
	/* user space single step */
	if (control == 0)
		return 1;
	/* over indication for storage alteration */
	if ((control & 0x20200000) && (cause & 0x2000))
		return 1;
	if (cause & 0x8000) {
		/* all branches */
		if ((control & 0x80800000) == 0x80000000)
			return 1;
		/* branch into selected range */
		if (((control & 0x80800000) == 0x80800000) &&
		    regs->psw.addr >= current->thread.per_user.start &&
		    regs->psw.addr <= current->thread.per_user.end)
			return 1;
	}
	return 0;
}

int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
{
	int fixup = probe_get_fixup_type(auprobe->insn);
	struct uprobe_task *utask = current->utask;

	clear_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
	update_cr_regs(current);
	psw_bits(regs->psw).per = auprobe->saved_per;
	regs->int_code = auprobe->saved_int_code;

	if (fixup & FIXUP_PSW_NORMAL)
		regs->psw.addr += utask->vaddr - utask->xol_vaddr;
	if (fixup & FIXUP_RETURN_REGISTER) {
		int reg = (auprobe->insn[0] & 0xf0) >> 4;

		regs->gprs[reg] += utask->vaddr - utask->xol_vaddr;
	}
	if (fixup & FIXUP_BRANCH_NOT_TAKEN) {
		int ilen = insn_length(auprobe->insn[0] >> 8);

		if (regs->psw.addr - utask->xol_vaddr == ilen)
			regs->psw.addr = utask->vaddr + ilen;
	}
	if (check_per_event(current->thread.per_event.cause,
			    current->thread.per_user.control, regs)) {
		/* fix per address */
		current->thread.per_event.address = utask->vaddr;
		/* trigger per event */
		set_pt_regs_flag(regs, PIF_PER_TRAP);
	}
	return 0;
}

int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val,
				 void *data)
{
	struct die_args *args = data;
	struct pt_regs *regs = args->regs;

	if (!user_mode(regs))
		return NOTIFY_DONE;
	if (regs->int_code & 0x200) /* Trap during transaction */
		return NOTIFY_DONE;
	switch (val) {
	case DIE_BPT:
		if (uprobe_pre_sstep_notifier(regs))
			return NOTIFY_STOP;
		break;
	case DIE_SSTEP:
		if (uprobe_post_sstep_notifier(regs))
			return NOTIFY_STOP;
	default:
		break;
	}
	return NOTIFY_DONE;
}

void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
{
	clear_thread_flag(TIF_UPROBE_SINGLESTEP);
	regs->int_code = auprobe->saved_int_code;
	regs->psw.addr = current->utask->vaddr;
	current->thread.per_event.address = current->utask->vaddr;
}

unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline,
						struct pt_regs *regs)
{
	unsigned long orig;

	orig = regs->gprs[14];
	regs->gprs[14] = trampoline;
	return orig;
}

bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
			     struct pt_regs *regs)
{
	if (ctx == RP_CHECK_CHAIN_CALL)
		return user_stack_pointer(regs) <= ret->stack;
	else
		return user_stack_pointer(regs) < ret->stack;
}

/* Instruction Emulation */

static void adjust_psw_addr(psw_t *psw, unsigned long len)
{
	psw->addr = __rewind_psw(*psw, -len);
}

#define EMU_ILLEGAL_OP		1
#define EMU_SPECIFICATION	2
#define EMU_ADDRESSING		3

#define emu_load_ril(ptr, output)			\
({							\
	unsigned int mask = sizeof(*(ptr)) - 1;		\
	__typeof__(*(ptr)) input;			\
	int __rc = 0;					\
							\
	if (!test_facility(34))				\
		__rc = EMU_ILLEGAL_OP;			\
	else if ((u64 __force)ptr & mask)		\
		__rc = EMU_SPECIFICATION;		\
	else if (get_user(input, ptr))			\
		__rc = EMU_ADDRESSING;			\
	else						\
		*(output) = input;			\
	__rc;						\
})

#define emu_store_ril(regs, ptr, input)			\
({							\
	unsigned int mask = sizeof(*(ptr)) - 1;		\
	__typeof__(ptr) __ptr = (ptr);			\
	int __rc = 0;					\
							\
	if (!test_facility(34))				\
		__rc = EMU_ILLEGAL_OP;			\
	else if ((u64 __force)__ptr & mask)		\
		__rc = EMU_SPECIFICATION;		\
	else if (put_user(*(input), __ptr))		\
		__rc = EMU_ADDRESSING;			\
	if (__rc == 0)					\
		sim_stor_event(regs,			\
			       (void __force *)__ptr,	\
			       mask + 1);		\
	__rc;						\
})

#define emu_cmp_ril(regs, ptr, cmp)			\
({							\
	unsigned int mask = sizeof(*(ptr)) - 1;		\
	__typeof__(*(ptr)) input;			\
	int __rc = 0;					\
							\
	if (!test_facility(34))				\
		__rc = EMU_ILLEGAL_OP;			\
	else if ((u64 __force)ptr & mask)		\
		__rc = EMU_SPECIFICATION;		\
	else if (get_user(input, ptr))			\
		__rc = EMU_ADDRESSING;			\
	else if (input > *(cmp))			\
		psw_bits((regs)->psw).cc = 1;		\
	else if (input < *(cmp))			\
		psw_bits((regs)->psw).cc = 2;		\
	else						\
		psw_bits((regs)->psw).cc = 0;		\
	__rc;						\
})

struct insn_ril {
	u8 opc0;
	u8 reg	: 4;
	u8 opc1 : 4;
	s32 disp;
} __packed;

union split_register {
	u64 u64;
	u32 u32[2];
	u16 u16[4];
	s64 s64;
	s32 s32[2];
	s16 s16[4];
};

/*
 * If user per registers are setup to trace storage alterations and an
 * emulated store took place on a fitting address a user trap is generated.
 */
static void sim_stor_event(struct pt_regs *regs, void *addr, int len)
{
	if (!(regs->psw.mask & PSW_MASK_PER))
		return;
	if (!(current->thread.per_user.control & PER_EVENT_STORE))
		return;
	if ((void *)current->thread.per_user.start > (addr + len))
		return;
	if ((void *)current->thread.per_user.end < addr)
		return;
	current->thread.per_event.address = regs->psw.addr;
	current->thread.per_event.cause = PER_EVENT_STORE >> 16;
	set_pt_regs_flag(regs, PIF_PER_TRAP);
}

/*
 * pc relative instructions are emulated, since parameters may not be
 * accessible from the xol area due to range limitations.
 */
static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs)
{
	union split_register *rx;
	struct insn_ril *insn;
	unsigned int ilen;
	void *uptr;
	int rc = 0;

	insn = (struct insn_ril *) &auprobe->insn;
	rx = (union split_register *) &regs->gprs[insn->reg];
	uptr = (void *)(regs->psw.addr + (insn->disp * 2));
	ilen = insn_length(insn->opc0);

	switch (insn->opc0) {
	case 0xc0:
		switch (insn->opc1) {
		case 0x00: /* larl */
			rx->u64 = (unsigned long)uptr;
			break;
		}
		break;
	case 0xc4:
		switch (insn->opc1) {
		case 0x02: /* llhrl */
			rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]);
			break;
		case 0x04: /* lghrl */
			rc = emu_load_ril((s16 __user *)uptr, &rx->u64);
			break;
		case 0x05: /* lhrl */
			rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]);
			break;
		case 0x06: /* llghrl */
			rc = emu_load_ril((u16 __user *)uptr, &rx->u64);
			break;
		case 0x08: /* lgrl */
			rc = emu_load_ril((u64 __user *)uptr, &rx->u64);
			break;
		case 0x0c: /* lgfrl */
			rc = emu_load_ril((s32 __user *)uptr, &rx->u64);
			break;
		case 0x0d: /* lrl */
			rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]);
			break;
		case 0x0e: /* llgfrl */
			rc = emu_load_ril((u32 __user *)uptr, &rx->u64);
			break;
		case 0x07: /* sthrl */
			rc = emu_store_ril(regs, (u16 __user *)uptr, &rx->u16[3]);
			break;
		case 0x0b: /* stgrl */
			rc = emu_store_ril(regs, (u64 __user *)uptr, &rx->u64);
			break;
		case 0x0f: /* strl */
			rc = emu_store_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
			break;
		}
		break;
	case 0xc6:
		switch (insn->opc1) {
		case 0x02: /* pfdrl */
			if (!test_facility(34))
				rc = EMU_ILLEGAL_OP;
			break;
		case 0x04: /* cghrl */
			rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s64);
			break;
		case 0x05: /* chrl */
			rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s32[1]);
			break;
		case 0x06: /* clghrl */
			rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u64);
			break;
		case 0x07: /* clhrl */
			rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u32[1]);
			break;
		case 0x08: /* cgrl */
			rc = emu_cmp_ril(regs, (s64 __user *)uptr, &rx->s64);
			break;
		case 0x0a: /* clgrl */
			rc = emu_cmp_ril(regs, (u64 __user *)uptr, &rx->u64);
			break;
		case 0x0c: /* cgfrl */
			rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s64);
			break;
		case 0x0d: /* crl */
			rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s32[1]);
			break;
		case 0x0e: /* clgfrl */
			rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u64);
			break;
		case 0x0f: /* clrl */
			rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
			break;
		}
		break;
	}
	adjust_psw_addr(&regs->psw, ilen);
	switch (rc) {
	case EMU_ILLEGAL_OP:
		regs->int_code = ilen << 16 | 0x0001;
		do_report_trap(regs, SIGILL, ILL_ILLOPC, NULL);
		break;
	case EMU_SPECIFICATION:
		regs->int_code = ilen << 16 | 0x0006;
		do_report_trap(regs, SIGILL, ILL_ILLOPC , NULL);
		break;
	case EMU_ADDRESSING:
		regs->int_code = ilen << 16 | 0x0005;
		do_report_trap(regs, SIGSEGV, SEGV_MAPERR, NULL);
		break;
	}
}

bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
{
	if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||
	    ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
	     !is_compat_task())) {
		regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
		do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);
		return true;
	}
	if (probe_is_insn_relative_long(auprobe->insn)) {
		handle_insn_ril(auprobe, regs);
		return true;
	}
	return false;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
2a0a5b22 JW	2	/*
	3	* User-space Probes (UProbes) for s390
	4	*
	5	* Copyright IBM Corp. 2014
	6	* Author(s): Jan Willeke,
	7	*/
	8
2a0a5b22 JW	9	#include <linux/uaccess.h>
	10	#include <linux/uprobes.h>
	11	#include <linux/compat.h>
	12	#include <linux/kdebug.h>
68db0cf1 IM	13	#include <linux/sched/task_stack.h>
68db0cf1 IM	14
2a0a5b22 JW	15	#include <asm/switch_to.h>
2a0a5b22 JW	16	#include <asm/facility.h>
d6fe5be3	17	#include <asm/kprobes.h>
2a0a5b22 JW	18	#include <asm/dis.h>
	19	#include "entry.h"
	20
	21	#define UPROBE_TRAP_NR UINT_MAX
	22
	23	int arch_uprobe_analyze_insn(struct arch_uprobe auprobe, struct mm_struct mm,
	24	unsigned long addr)
	25	{
	26	return probe_is_prohibited_opcode(auprobe->insn);
	27	}
	28
	29	int arch_uprobe_pre_xol(struct arch_uprobe auprobe, struct pt_regs regs)
	30	{
8bb3fdd6	31	if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
2a0a5b22	32	return -EINVAL;
8bb3fdd6	33	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
2a0a5b22 JW	34	return -EINVAL;
2a0a5b22 JW	35	clear_pt_regs_flag(regs, PIF_PER_TRAP);
a7525982	36	auprobe->saved_per = psw_bits(regs->psw).per;
2a0a5b22 JW	37	auprobe->saved_int_code = regs->int_code;
	38	regs->int_code = UPROBE_TRAP_NR;
	39	regs->psw.addr = current->utask->xol_vaddr;
	40	set_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
	41	update_cr_regs(current);
	42	return 0;
	43	}
	44
	45	bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
	46	{
	47	struct pt_regs *regs = task_pt_regs(tsk);
	48
	49	if (regs->int_code != UPROBE_TRAP_NR)
	50	return true;
	51	return false;
	52	}
	53
8d1a2427 JW	54	static int check_per_event(unsigned short cause, unsigned long control,
	55	struct pt_regs *regs)
	56	{
	57	if (!(regs->psw.mask & PSW_MASK_PER))
	58	return 0;
	59	/* user space single step */
	60	if (control == 0)
	61	return 1;
	62	/* over indication for storage alteration */
	63	if ((control & 0x20200000) && (cause & 0x2000))
	64	return 1;
	65	if (cause & 0x8000) {
	66	/* all branches */
	67	if ((control & 0x80800000) == 0x80000000)
	68	return 1;
	69	/* branch into selected range */
	70	if (((control & 0x80800000) == 0x80800000) &&
	71	regs->psw.addr >= current->thread.per_user.start &&
	72	regs->psw.addr <= current->thread.per_user.end)
	73	return 1;
	74	}
	75	return 0;
	76	}
	77
2a0a5b22 JW	78	int arch_uprobe_post_xol(struct arch_uprobe auprobe, struct pt_regs regs)
	79	{
	80	int fixup = probe_get_fixup_type(auprobe->insn);
	81	struct uprobe_task *utask = current->utask;
	82
	83	clear_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
	84	update_cr_regs(current);
a7525982	85	psw_bits(regs->psw).per = auprobe->saved_per;
2a0a5b22 JW	86	regs->int_code = auprobe->saved_int_code;
	87
	88	if (fixup & FIXUP_PSW_NORMAL)
	89	regs->psw.addr += utask->vaddr - utask->xol_vaddr;
	90	if (fixup & FIXUP_RETURN_REGISTER) {
	91	int reg = (auprobe->insn[0] & 0xf0) >> 4;
	92
	93	regs->gprs[reg] += utask->vaddr - utask->xol_vaddr;
	94	}
	95	if (fixup & FIXUP_BRANCH_NOT_TAKEN) {
	96	int ilen = insn_length(auprobe->insn[0] >> 8);
	97
	98	if (regs->psw.addr - utask->xol_vaddr == ilen)
	99	regs->psw.addr = utask->vaddr + ilen;
	100	}
8d1a2427 JW	101	if (check_per_event(current->thread.per_event.cause,
	102	current->thread.per_user.control, regs)) {
	103	/* fix per address */
	104	current->thread.per_event.address = utask->vaddr;
	105	/* trigger per event */
	106	set_pt_regs_flag(regs, PIF_PER_TRAP);
	107	}
2a0a5b22 JW	108	return 0;
	109	}
	110
	111	int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val,
	112	void *data)
	113	{
	114	struct die_args *args = data;
	115	struct pt_regs *regs = args->regs;
	116
	117	if (!user_mode(regs))
	118	return NOTIFY_DONE;
	119	if (regs->int_code & 0x200) /* Trap during transaction */
	120	return NOTIFY_DONE;
	121	switch (val) {
	122	case DIE_BPT:
	123	if (uprobe_pre_sstep_notifier(regs))
	124	return NOTIFY_STOP;
	125	break;
	126	case DIE_SSTEP:
	127	if (uprobe_post_sstep_notifier(regs))
	128	return NOTIFY_STOP;
	129	default:
	130	break;
	131	}
	132	return NOTIFY_DONE;
	133	}
	134
	135	void arch_uprobe_abort_xol(struct arch_uprobe auprobe, struct pt_regs regs)
	136	{
	137	clear_thread_flag(TIF_UPROBE_SINGLESTEP);
	138	regs->int_code = auprobe->saved_int_code;
	139	regs->psw.addr = current->utask->vaddr;
8d1a2427	140	current->thread.per_event.address = current->utask->vaddr;
2a0a5b22 JW	141	}
	142
	143	unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline,
	144	struct pt_regs *regs)
	145	{
	146	unsigned long orig;
	147
	148	orig = regs->gprs[14];
	149	regs->gprs[14] = trampoline;
	150	return orig;
	151	}
	152
783c3b53 HC	153	bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
	154	struct pt_regs *regs)
	155	{
	156	if (ctx == RP_CHECK_CHAIN_CALL)
	157	return user_stack_pointer(regs) <= ret->stack;
	158	else
	159	return user_stack_pointer(regs) < ret->stack;
	160	}
	161
2a0a5b22 JW	162	/* Instruction Emulation */
	163
	164	static void adjust_psw_addr(psw_t *psw, unsigned long len)
	165	{
	166	psw->addr = __rewind_psw(*psw, -len);
	167	}
	168
	169	#define EMU_ILLEGAL_OP 1
	170	#define EMU_SPECIFICATION 2
	171	#define EMU_ADDRESSING 3
	172
	173	#define emu_load_ril(ptr, output) \
	174	({ \
	175	unsigned int mask = sizeof(*(ptr)) - 1; \
	176	__typeof__(*(ptr)) input; \
	177	int __rc = 0; \
	178	\
	179	if (!test_facility(34)) \
	180	__rc = EMU_ILLEGAL_OP; \
	181	else if ((u64 __force)ptr & mask) \
	182	__rc = EMU_SPECIFICATION; \
	183	else if (get_user(input, ptr)) \
	184	__rc = EMU_ADDRESSING; \
	185	else \
	186	*(output) = input; \
	187	__rc; \
	188	})
	189
8d1a2427	190	#define emu_store_ril(regs, ptr, input) \
2a0a5b22 JW	191	({ \
2a0a5b22 JW	192	unsigned int mask = sizeof(*(ptr)) - 1; \
8d1a2427	193	__typeof__(ptr) __ptr = (ptr); \
2a0a5b22 JW	194	int __rc = 0; \
	195	\
	196	if (!test_facility(34)) \
	197	__rc = EMU_ILLEGAL_OP; \
8d1a2427	198	else if ((u64 __force)__ptr & mask) \
2a0a5b22	199	__rc = EMU_SPECIFICATION; \
8d1a2427	200	else if (put_user(*(input), __ptr)) \
2a0a5b22	201	__rc = EMU_ADDRESSING; \
8d1a2427	202	if (__rc == 0) \
9f9d86e1 HC	203	sim_stor_event(regs, \
	204	(void __force *)__ptr, \
	205	mask + 1); \
2a0a5b22 JW	206	__rc; \
	207	})
	208
	209	#define emu_cmp_ril(regs, ptr, cmp) \
	210	({ \
	211	unsigned int mask = sizeof(*(ptr)) - 1; \
	212	__typeof__(*(ptr)) input; \
	213	int __rc = 0; \
	214	\
	215	if (!test_facility(34)) \
	216	__rc = EMU_ILLEGAL_OP; \
	217	else if ((u64 __force)ptr & mask) \
	218	__rc = EMU_SPECIFICATION; \
	219	else if (get_user(input, ptr)) \
	220	__rc = EMU_ADDRESSING; \
	221	else if (input > *(cmp)) \
	222	psw_bits((regs)->psw).cc = 1; \
	223	else if (input < *(cmp)) \
	224	psw_bits((regs)->psw).cc = 2; \
	225	else \
	226	psw_bits((regs)->psw).cc = 0; \
	227	__rc; \
	228	})
	229
	230	struct insn_ril {
	231	u8 opc0;
	232	u8 reg : 4;
	233	u8 opc1 : 4;
	234	s32 disp;
	235	} __packed;
	236
	237	union split_register {
	238	u64 u64;
	239	u32 u32[2];
	240	u16 u16[4];
	241	s64 s64;
	242	s32 s32[2];
	243	s16 s16[4];
	244	};
	245
8d1a2427 JW	246	/*
	247	* If user per registers are setup to trace storage alterations and an
	248	* emulated store took place on a fitting address a user trap is generated.
	249	*/
	250	static void sim_stor_event(struct pt_regs regs, void addr, int len)
	251	{
	252	if (!(regs->psw.mask & PSW_MASK_PER))
	253	return;
	254	if (!(current->thread.per_user.control & PER_EVENT_STORE))
	255	return;
	256	if ((void *)current->thread.per_user.start > (addr + len))
	257	return;
	258	if ((void *)current->thread.per_user.end < addr)
	259	return;
	260	current->thread.per_event.address = regs->psw.addr;
	261	current->thread.per_event.cause = PER_EVENT_STORE >> 16;
	262	set_pt_regs_flag(regs, PIF_PER_TRAP);
	263	}
	264
2a0a5b22 JW	265	/*
	266	* pc relative instructions are emulated, since parameters may not be
	267	* accessible from the xol area due to range limitations.
	268	*/
	269	static void handle_insn_ril(struct arch_uprobe auprobe, struct pt_regs regs)
	270	{
	271	union split_register *rx;
	272	struct insn_ril *insn;
	273	unsigned int ilen;
	274	void *uptr;
	275	int rc = 0;
	276
	277	insn = (struct insn_ril *) &auprobe->insn;
	278	rx = (union split_register *) &regs->gprs[insn->reg];
	279	uptr = (void )(regs->psw.addr + (insn->disp 2));
	280	ilen = insn_length(insn->opc0);
	281
	282	switch (insn->opc0) {
	283	case 0xc0:
	284	switch (insn->opc1) {
	285	case 0x00: /* larl */
	286	rx->u64 = (unsigned long)uptr;
	287	break;
	288	}
	289	break;
	290	case 0xc4:
	291	switch (insn->opc1) {
	292	case 0x02: /* llhrl */
	293	rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]);
	294	break;
	295	case 0x04: /* lghrl */
	296	rc = emu_load_ril((s16 __user *)uptr, &rx->u64);
	297	break;
	298	case 0x05: /* lhrl */
	299	rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]);
	300	break;
	301	case 0x06: /* llghrl */
	302	rc = emu_load_ril((u16 __user *)uptr, &rx->u64);
	303	break;
	304	case 0x08: /* lgrl */
	305	rc = emu_load_ril((u64 __user *)uptr, &rx->u64);
	306	break;
	307	case 0x0c: /* lgfrl */
	308	rc = emu_load_ril((s32 __user *)uptr, &rx->u64);
	309	break;
	310	case 0x0d: /* lrl */
	311	rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]);
	312	break;
	313	case 0x0e: /* llgfrl */
	314	rc = emu_load_ril((u32 __user *)uptr, &rx->u64);
	315	break;
	316	case 0x07: /* sthrl */
8d1a2427	317	rc = emu_store_ril(regs, (u16 __user *)uptr, &rx->u16[3]);
2a0a5b22 JW	318	break;
2a0a5b22 JW	319	case 0x0b: /* stgrl */
8d1a2427	320	rc = emu_store_ril(regs, (u64 __user *)uptr, &rx->u64);
2a0a5b22 JW	321	break;
2a0a5b22 JW	322	case 0x0f: /* strl */
8d1a2427	323	rc = emu_store_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
2a0a5b22 JW	324	break;
	325	}
	326	break;
	327	case 0xc6:
	328	switch (insn->opc1) {
	329	case 0x02: /* pfdrl */
	330	if (!test_facility(34))
	331	rc = EMU_ILLEGAL_OP;
	332	break;
	333	case 0x04: /* cghrl */
	334	rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s64);
	335	break;
	336	case 0x05: /* chrl */
	337	rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s32[1]);
	338	break;
	339	case 0x06: /* clghrl */
	340	rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u64);
	341	break;
	342	case 0x07: /* clhrl */
	343	rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u32[1]);
	344	break;
	345	case 0x08: /* cgrl */
	346	rc = emu_cmp_ril(regs, (s64 __user *)uptr, &rx->s64);
	347	break;
	348	case 0x0a: /* clgrl */
	349	rc = emu_cmp_ril(regs, (u64 __user *)uptr, &rx->u64);
	350	break;
	351	case 0x0c: /* cgfrl */
	352	rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s64);
	353	break;
	354	case 0x0d: /* crl */
	355	rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s32[1]);
	356	break;
	357	case 0x0e: /* clgfrl */
	358	rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u64);
	359	break;
	360	case 0x0f: /* clrl */
	361	rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
	362	break;
	363	}
	364	break;
	365	}
	366	adjust_psw_addr(&regs->psw, ilen);
	367	switch (rc) {
	368	case EMU_ILLEGAL_OP:
	369	regs->int_code = ilen << 16 \| 0x0001;
	370	do_report_trap(regs, SIGILL, ILL_ILLOPC, NULL);
	371	break;
	372	case EMU_SPECIFICATION:
	373	regs->int_code = ilen << 16 \| 0x0006;
	374	do_report_trap(regs, SIGILL, ILL_ILLOPC , NULL);
	375	break;
	376	case EMU_ADDRESSING:
	377	regs->int_code = ilen << 16 \| 0x0005;
	378	do_report_trap(regs, SIGSEGV, SEGV_MAPERR, NULL);
	379	break;
	380	}
	381	}
	382
	383	bool arch_uprobe_skip_sstep(struct arch_uprobe auprobe, struct pt_regs regs)
	384	{
8bb3fdd6 HC	385	if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) \|\|
8bb3fdd6 HC	386	((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
2a0a5b22 JW	387	!is_compat_task())) {
	388	regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
	389	do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);
	390	return true;
	391	}
	392	if (probe_is_insn_relative_long(auprobe->insn)) {
	393	handle_insn_ril(auprobe, regs);
	394	return true;
	395	}
	396	return false;
	397	}