[mirror_ubuntu-bionic-kernel.git] / arch / s390 / pci / pci_insn.c

// SPDX-License-Identifier: GPL-2.0
/*
 * s390 specific pci instructions
 *
 * Copyright IBM Corp. 2013
 */

#include <linux/export.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <asm/facility.h>
#include <asm/pci_insn.h>
#include <asm/pci_debug.h>
#include <asm/processor.h>

#define ZPCI_INSN_BUSY_DELAY	1	/* 1 microsecond */

static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
{
	struct {
		u64 req;
		u64 offset;
		u8 cc;
		u8 status;
	} __packed data = {req, offset, cc, status};

	zpci_err_hex(&data, sizeof(data));
}

/* Modify PCI Function Controls */
static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
{
	u8 cc;

	asm volatile (
		"	.insn	rxy,0xe300000000d0,%[req],%[fib]\n"
		"	ipm	%[cc]\n"
		"	srl	%[cc],28\n"
		: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
		: : "cc");
	*status = req >> 24 & 0xff;
	return cc;
}

u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
{
	u8 cc;

	do {
		cc = __mpcifc(req, fib, status);
		if (cc == 2)
			msleep(ZPCI_INSN_BUSY_DELAY);
	} while (cc == 2);

	if (cc)
		zpci_err_insn(cc, *status, req, 0);

	return cc;
}

/* Refresh PCI Translations */
static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
{
	register u64 __addr asm("2") = addr;
	register u64 __range asm("3") = range;
	u8 cc;

	asm volatile (
		"	.insn	rre,0xb9d30000,%[fn],%[addr]\n"
		"	ipm	%[cc]\n"
		"	srl	%[cc],28\n"
		: [cc] "=d" (cc), [fn] "+d" (fn)
		: [addr] "d" (__addr), "d" (__range)
		: "cc");
	*status = fn >> 24 & 0xff;
	return cc;
}

int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
{
	u8 cc, status;

	do {
		cc = __rpcit(fn, addr, range, &status);
		if (cc == 2)
			udelay(ZPCI_INSN_BUSY_DELAY);
	} while (cc == 2);

	if (cc)
		zpci_err_insn(cc, status, addr, range);

	return (cc) ? -EIO : 0;
}

/* Set Interruption Controls */
int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
{
	if (!test_facility(72))
		return -EIO;
	asm volatile (
		"	.insn	rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
		: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
	return 0;
}

/* PCI Load */
static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
{
	register u64 __req asm("2") = req;
	register u64 __offset asm("3") = offset;
	int cc = -ENXIO;
	u64 __data;

	asm volatile (
		"	.insn	rre,0xb9d20000,%[data],%[req]\n"
		"0:	ipm	%[cc]\n"
		"	srl	%[cc],28\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
		:  "d" (__offset)
		: "cc");
	*status = __req >> 24 & 0xff;
	*data = __data;
	return cc;
}

static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
{
	u64 __data;
	int cc;

	cc = ____pcilg(&__data, req, offset, status);
	if (!cc)
		*data = __data;

	return cc;
}

int zpci_load(u64 *data, u64 req, u64 offset)
{
	u8 status;
	int cc;

	do {
		cc = __pcilg(data, req, offset, &status);
		if (cc == 2)
			udelay(ZPCI_INSN_BUSY_DELAY);
	} while (cc == 2);

	if (cc)
		zpci_err_insn(cc, status, req, offset);

	return (cc > 0) ? -EIO : cc;
}
EXPORT_SYMBOL_GPL(zpci_load);

/* PCI Store */
static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
{
	register u64 __req asm("2") = req;
	register u64 __offset asm("3") = offset;
	int cc = -ENXIO;

	asm volatile (
		"	.insn	rre,0xb9d00000,%[data],%[req]\n"
		"0:	ipm	%[cc]\n"
		"	srl	%[cc],28\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: [cc] "+d" (cc), [req] "+d" (__req)
		: "d" (__offset), [data] "d" (data)
		: "cc");
	*status = __req >> 24 & 0xff;
	return cc;
}

int zpci_store(u64 data, u64 req, u64 offset)
{
	u8 status;
	int cc;

	do {
		cc = __pcistg(data, req, offset, &status);
		if (cc == 2)
			udelay(ZPCI_INSN_BUSY_DELAY);
	} while (cc == 2);

	if (cc)
		zpci_err_insn(cc, status, req, offset);

	return (cc > 0) ? -EIO : cc;
}
EXPORT_SYMBOL_GPL(zpci_store);

/* PCI Store Block */
static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
{
	int cc = -ENXIO;

	asm volatile (
		"	.insn	rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
		"0:	ipm	%[cc]\n"
		"	srl	%[cc],28\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: [cc] "+d" (cc), [req] "+d" (req)
		: [offset] "d" (offset), [data] "Q" (*data)
		: "cc");
	*status = req >> 24 & 0xff;
	return cc;
}

int zpci_store_block(const u64 *data, u64 req, u64 offset)
{
	u8 status;
	int cc;

	do {
		cc = __pcistb(data, req, offset, &status);
		if (cc == 2)
			udelay(ZPCI_INSN_BUSY_DELAY);
	} while (cc == 2);

	if (cc)
		zpci_err_insn(cc, status, req, offset);

	return (cc > 0) ? -EIO : cc;
}
EXPORT_SYMBOL_GPL(zpci_store_block);
Commit	Line	Data
adbb3901	1	// SPDX-License-Identifier: GPL-2.0
cbcca5d0 SO	2	/*
	3	* s390 specific pci instructions
	4	*
	5	* Copyright IBM Corp. 2013
	6	*/
	7
	8	#include <linux/export.h>
	9	#include <linux/errno.h>
	10	#include <linux/delay.h>
48070c73	11	#include <asm/facility.h>
cbcca5d0	12	#include <asm/pci_insn.h>
3d8258e4	13	#include <asm/pci_debug.h>
f0bacb7f	14	#include <asm/processor.h>
cbcca5d0 SO	15
	16	#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
	17
3d8258e4 SO	18	static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
	19	{
	20	struct {
3d8258e4 SO	21	u64 req;
3d8258e4 SO	22	u64 offset;
7cc8944e SO	23	u8 cc;
	24	u8 status;
	25	} __packed data = {req, offset, cc, status};
3d8258e4 SO	26
	27	zpci_err_hex(&data, sizeof(data));
	28	}
	29
cbcca5d0 SO	30	/* Modify PCI Function Controls */
	31	static inline u8 __mpcifc(u64 req, struct zpci_fib fib, u8 status)
	32	{
	33	u8 cc;
	34
	35	asm volatile (
	36	" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
	37	" ipm %[cc]\n"
	38	" srl %[cc],28\n"
	39	: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
	40	: : "cc");
	41	*status = req >> 24 & 0xff;
	42	return cc;
	43	}
	44
4dfbd3ef	45	u8 zpci_mod_fc(u64 req, struct zpci_fib fib, u8 status)
cbcca5d0	46	{
4dfbd3ef	47	u8 cc;
cbcca5d0 SO	48
cbcca5d0 SO	49	do {
4dfbd3ef	50	cc = __mpcifc(req, fib, status);
cbcca5d0 SO	51	if (cc == 2)
	52	msleep(ZPCI_INSN_BUSY_DELAY);
	53	} while (cc == 2);
	54
	55	if (cc)
4dfbd3ef	56	zpci_err_insn(cc, *status, req, 0);
3d8258e4	57
4dfbd3ef	58	return cc;
cbcca5d0 SO	59	}
	60
	61	/* Refresh PCI Translations */
	62	static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
	63	{
	64	register u64 __addr asm("2") = addr;
	65	register u64 __range asm("3") = range;
	66	u8 cc;
	67
	68	asm volatile (
	69	" .insn rre,0xb9d30000,%[fn],%[addr]\n"
	70	" ipm %[cc]\n"
	71	" srl %[cc],28\n"
	72	: [cc] "=d" (cc), [fn] "+d" (fn)
	73	: [addr] "d" (__addr), "d" (__range)
	74	: "cc");
	75	*status = fn >> 24 & 0xff;
	76	return cc;
	77	}
	78
9389339f	79	int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
cbcca5d0 SO	80	{
	81	u8 cc, status;
	82
	83	do {
	84	cc = __rpcit(fn, addr, range, &status);
	85	if (cc == 2)
	86	udelay(ZPCI_INSN_BUSY_DELAY);
	87	} while (cc == 2);
	88
	89	if (cc)
3d8258e4 SO	90	zpci_err_insn(cc, status, addr, range);
3d8258e4 SO	91
cbcca5d0 SO	92	return (cc) ? -EIO : 0;
	93	}
	94
	95	/* Set Interruption Controls */
48070c73	96	int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
cbcca5d0	97	{
48070c73 CB	98	if (!test_facility(72))
48070c73 CB	99	return -EIO;
cbcca5d0 SO	100	asm volatile (
	101	" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
	102	: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
48070c73	103	return 0;
cbcca5d0 SO	104	}
	105
	106	/* PCI Load */
7b411ac6	107	static inline int ____pcilg(u64 data, u64 req, u64 offset, u8 status)
cbcca5d0 SO	108	{
	109	register u64 __req asm("2") = req;
	110	register u64 __offset asm("3") = offset;
f0bacb7f	111	int cc = -ENXIO;
cbcca5d0	112	u64 __data;
cbcca5d0 SO	113
	114	asm volatile (
	115	" .insn rre,0xb9d20000,%[data],%[req]\n"
f0bacb7f	116	"0: ipm %[cc]\n"
cbcca5d0	117	" srl %[cc],28\n"
f0bacb7f SO	118	"1:\n"
	119	EX_TABLE(0b, 1b)
	120	: [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
cbcca5d0 SO	121	: "d" (__offset)
	122	: "cc");
	123	*status = __req >> 24 & 0xff;
7b411ac6 HC	124	*data = __data;
	125	return cc;
	126	}
	127
	128	static inline int __pcilg(u64 data, u64 req, u64 offset, u8 status)
	129	{
	130	u64 __data;
	131	int cc;
	132
	133	cc = ____pcilg(&__data, req, offset, status);
b170bad4 SO	134	if (!cc)
	135	*data = __data;
	136
cbcca5d0 SO	137	return cc;
	138	}
	139
9389339f	140	int zpci_load(u64 *data, u64 req, u64 offset)
cbcca5d0	141	{
f0bacb7f SO	142	u8 status;
f0bacb7f SO	143	int cc;
cbcca5d0 SO	144
	145	do {
	146	cc = __pcilg(data, req, offset, &status);
	147	if (cc == 2)
	148	udelay(ZPCI_INSN_BUSY_DELAY);
	149	} while (cc == 2);
	150
f0bacb7f	151	if (cc)
3d8258e4 SO	152	zpci_err_insn(cc, status, req, offset);
3d8258e4 SO	153
f0bacb7f	154	return (cc > 0) ? -EIO : cc;
cbcca5d0	155	}
9389339f	156	EXPORT_SYMBOL_GPL(zpci_load);
cbcca5d0 SO	157
cbcca5d0 SO	158	/* PCI Store */
f0bacb7f	159	static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
cbcca5d0 SO	160	{
	161	register u64 __req asm("2") = req;
	162	register u64 __offset asm("3") = offset;
f0bacb7f	163	int cc = -ENXIO;
cbcca5d0 SO	164
	165	asm volatile (
	166	" .insn rre,0xb9d00000,%[data],%[req]\n"
f0bacb7f	167	"0: ipm %[cc]\n"
cbcca5d0	168	" srl %[cc],28\n"
f0bacb7f SO	169	"1:\n"
	170	EX_TABLE(0b, 1b)
	171	: [cc] "+d" (cc), [req] "+d" (__req)
cbcca5d0 SO	172	: "d" (__offset), [data] "d" (data)
	173	: "cc");
	174	*status = __req >> 24 & 0xff;
	175	return cc;
	176	}
	177
9389339f	178	int zpci_store(u64 data, u64 req, u64 offset)
cbcca5d0	179	{
f0bacb7f SO	180	u8 status;
f0bacb7f SO	181	int cc;
cbcca5d0 SO	182
	183	do {
	184	cc = __pcistg(data, req, offset, &status);
	185	if (cc == 2)
	186	udelay(ZPCI_INSN_BUSY_DELAY);
	187	} while (cc == 2);
	188
	189	if (cc)
3d8258e4 SO	190	zpci_err_insn(cc, status, req, offset);
3d8258e4 SO	191
f0bacb7f	192	return (cc > 0) ? -EIO : cc;
cbcca5d0	193	}
9389339f	194	EXPORT_SYMBOL_GPL(zpci_store);
cbcca5d0 SO	195
cbcca5d0 SO	196	/* PCI Store Block */
f0bacb7f	197	static inline int __pcistb(const u64 data, u64 req, u64 offset, u8 status)
cbcca5d0	198	{
f0bacb7f	199	int cc = -ENXIO;
cbcca5d0 SO	200
	201	asm volatile (
	202	" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
f0bacb7f	203	"0: ipm %[cc]\n"
cbcca5d0	204	" srl %[cc],28\n"
f0bacb7f SO	205	"1:\n"
	206	EX_TABLE(0b, 1b)
	207	: [cc] "+d" (cc), [req] "+d" (req)
cbcca5d0 SO	208	: [offset] "d" (offset), [data] "Q" (*data)
	209	: "cc");
	210	*status = req >> 24 & 0xff;
	211	return cc;
	212	}
	213
9389339f	214	int zpci_store_block(const u64 *data, u64 req, u64 offset)
cbcca5d0	215	{
f0bacb7f SO	216	u8 status;
f0bacb7f SO	217	int cc;
cbcca5d0 SO	218
	219	do {
	220	cc = __pcistb(data, req, offset, &status);
	221	if (cc == 2)
	222	udelay(ZPCI_INSN_BUSY_DELAY);
	223	} while (cc == 2);
	224
	225	if (cc)
3d8258e4 SO	226	zpci_err_insn(cc, status, req, offset);
3d8258e4 SO	227
f0bacb7f	228	return (cc > 0) ? -EIO : cc;
cbcca5d0	229	}
9389339f	230	EXPORT_SYMBOL_GPL(zpci_store_block);