[mirror_ubuntu-bionic-kernel.git] / arch / score / kernel / irq.c

/*
 * arch/score/kernel/irq.c
 *
 * Score Processor version.
 *
 * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
 *  Chen Liqin <liqin.chen@sunplusct.com>
 *  Lennox Wu <lennox.wu@sunplusct.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>

#include <asm/io.h>

/* the interrupt controller is hardcoded at this address */
#define SCORE_PIC		((u32 __iomem __force *)0x95F50000)

#define INT_PNDL		0
#define INT_PNDH		1
#define INT_PRIORITY_M		2
#define INT_PRIORITY_SG0	4
#define INT_PRIORITY_SG1	5
#define INT_PRIORITY_SG2	6
#define INT_PRIORITY_SG3	7
#define INT_MASKL		8
#define INT_MASKH		9

/*
 * handles all normal device IRQs
 */
asmlinkage void do_IRQ(int irq)
{
	irq_enter();
	generic_handle_irq(irq);
	irq_exit();
}

static void score_mask(struct irq_data *d)
{
	unsigned int irq_source = 63 - d->irq;

	if (irq_source < 32)
		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \
			(1 << irq_source)), SCORE_PIC + INT_MASKL);
	else
		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \
			(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
}

static void score_unmask(struct irq_data *d)
{
	unsigned int irq_source = 63 - d->irq;

	if (irq_source < 32)
		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
			~(1 << irq_source)), SCORE_PIC + INT_MASKL);
	else
		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \
			~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
}

struct irq_chip score_irq_chip = {
	.name		= "Score7-level",
	.irq_mask	= score_mask,
	.irq_mask_ack	= score_mask,
	.irq_unmask	= score_unmask,
};

/*
 * initialise the interrupt system
 */
void __init init_IRQ(void)
{
	int index;
	unsigned long target_addr;

	for (index = 0; index < NR_IRQS; ++index)
		irq_set_chip_and_handler(index, &score_irq_chip,
					 handle_level_irq);

	for (target_addr = IRQ_VECTOR_BASE_ADDR;
		target_addr <= IRQ_VECTOR_END_ADDR;
		target_addr += IRQ_VECTOR_SIZE)
		memcpy((void *)target_addr, \
			interrupt_exception_vector, IRQ_VECTOR_SIZE);

	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKL);
	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKH);

	__asm__ __volatile__(
		"mtcr	%0, cr3\n\t"
		: : "r" (EXCEPTION_VECTOR_BASE_ADDR | \
			VECTOR_ADDRESS_OFFSET_MODE16));
}
Commit	Line	Data
6bc9a396 CL	1	/*
	2	* arch/score/kernel/irq.c
	3	*
	4	* Score Processor version.
	5	*
	6	* Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
	7	* Chen Liqin <liqin.chen@sunplusct.com>
	8	* Lennox Wu <lennox.wu@sunplusct.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, see the file COPYING, or write
	22	* to the Free Software Foundation, Inc.,
	23	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	24	*/
	25
	26	#include <linux/interrupt.h>
	27	#include <linux/kernel_stat.h>
	28	#include <linux/seq_file.h>
	29
	30	#include <asm/io.h>
	31
9b05706a AB	32	/* the interrupt controller is hardcoded at this address */
	33	#define SCORE_PIC ((u32 __iomem __force *)0x95F50000)
	34
	35	#define INT_PNDL 0
	36	#define INT_PNDH 1
	37	#define INT_PRIORITY_M 2
	38	#define INT_PRIORITY_SG0 4
	39	#define INT_PRIORITY_SG1 5
	40	#define INT_PRIORITY_SG2 6
	41	#define INT_PRIORITY_SG3 7
	42	#define INT_MASKL 8
	43	#define INT_MASKH 9
	44
6bc9a396 CL	45	/*
	46	* handles all normal device IRQs
	47	*/
	48	asmlinkage void do_IRQ(int irq)
	49	{
	50	irq_enter();
	51	generic_handle_irq(irq);
	52	irq_exit();
	53	}
	54
7182297e	55	static void score_mask(struct irq_data *d)
6bc9a396	56	{
7182297e	57	unsigned int irq_source = 63 - d->irq;
6bc9a396 CL	58
6bc9a396 CL	59	if (irq_source < 32)
9b05706a AB	60	__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) \| \
9b05706a AB	61	(1 << irq_source)), SCORE_PIC + INT_MASKL);
6bc9a396	62	else
9b05706a AB	63	__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) \| \
9b05706a AB	64	(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
6bc9a396 CL	65	}
6bc9a396 CL	66
7182297e	67	static void score_unmask(struct irq_data *d)
6bc9a396	68	{
7182297e	69	unsigned int irq_source = 63 - d->irq;
6bc9a396 CL	70
6bc9a396 CL	71	if (irq_source < 32)
9b05706a AB	72	__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
9b05706a AB	73	~(1 << irq_source)), SCORE_PIC + INT_MASKL);
6bc9a396	74	else
9b05706a AB	75	__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \
9b05706a AB	76	~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
6bc9a396 CL	77	}
	78
	79	struct irq_chip score_irq_chip = {
	80	.name = "Score7-level",
7182297e TG	81	.irq_mask = score_mask,
	82	.irq_mask_ack = score_mask,
	83	.irq_unmask = score_unmask,
6bc9a396 CL	84	};
	85
	86	/*
	87	* initialise the interrupt system
	88	*/
	89	void __init init_IRQ(void)
	90	{
	91	int index;
	92	unsigned long target_addr;
	93
	94	for (index = 0; index < NR_IRQS; ++index)
99135351	95	irq_set_chip_and_handler(index, &score_irq_chip,
6bc9a396 CL	96	handle_level_irq);
	97
	98	for (target_addr = IRQ_VECTOR_BASE_ADDR;
	99	target_addr <= IRQ_VECTOR_END_ADDR;
	100	target_addr += IRQ_VECTOR_SIZE)
	101	memcpy((void *)target_addr, \
	102	interrupt_exception_vector, IRQ_VECTOR_SIZE);
	103
9b05706a AB	104	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKL);
9b05706a AB	105	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKH);
6bc9a396 CL	106
	107	__asm__ __volatile__(
	108	"mtcr %0, cr3\n\t"
	109	: : "r" (EXCEPTION_VECTOR_BASE_ADDR \| \
	110	VECTOR_ADDRESS_OFFSET_MODE16));
	111	}