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Merge branch 'sh/dmaengine' into sh-latest
[mirror_ubuntu-jammy-kernel.git] / arch / sh / boards / mach-ap325rxa / setup.c
CommitLineData
04e917b6
YG		 1/*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
4875ea22 15#include <linux/interrupt.h>
04e917b6 16#include <linux/platform_device.h>
365e1087 17#include <linux/mmc/host.h>
960b9e7e 18#include <linux/mmc/sh_mobile_sdhi.h>
04e917b6 19#include <linux/mtd/physmap.h>
908978ac 20#include <linux/mtd/sh_flctl.h>
04e917b6 21#include <linux/delay.h>
026953db 22#include <linux/i2c.h>
9c158b15
GL		 23#include <linux/regulator/fixed.h>
24#include <linux/regulator/machine.h>
90b76491 25#include <linux/smsc911x.h>
16587c45 26#include <linux/gpio.h>
a1ad8033 27#include <linux/videodev2.h>
9c23c516 28#include <linux/sh_intc.h>
47131258 29#include <media/ov772x.h>
ba087e6f 30#include <media/soc_camera.h>
8b2224dc
MD		 31#include <media/soc_camera_platform.h>
32#include <media/sh_mobile_ceu.h>
225c9a8d 33#include <video/sh_mobile_lcdc.h>
04e917b6 34#include <asm/io.h>
6968980a 35#include <asm/clock.h>
86c7d03a 36#include <asm/suspend.h>
f7275650 37#include <cpu/sh7723.h>
04e917b6 38
9c158b15
GL		 39/* Dummy supplies, where voltage doesn't matter */
40static struct regulator_consumer_supply dummy_supplies[] = {
41 REGULATOR_SUPPLY("vddvario", "smsc911x"),
42 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
43};
44
90b76491
SG		 45static struct smsc911x_platform_config smsc911x_config = {
46 .phy_interface = PHY_INTERFACE_MODE_MII,
47 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
48 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
49 .flags = SMSC911X_USE_32BIT,
4875ea22
MD		 50};
51
90b76491 52static struct resource smsc9118_resources[] = {
04e917b6
YG		 53 [0] = {
54 .start = 0xb6080000,
55 .end = 0xb60fffff,
56 .flags = IORESOURCE_MEM,
57 },
58 [1] = {
9c23c516
PM		 59 .start = evt2irq(0x660),
60 .end = evt2irq(0x660),
04e917b6
YG		 61 .flags = IORESOURCE_IRQ,
62 }
63};
64
90b76491
SG		 65static struct platform_device smsc9118_device = {
66 .name = "smsc911x",
04e917b6 67 .id = -1,
90b76491
SG		 68 .num_resources = ARRAY_SIZE(smsc9118_resources),
69 .resource = smsc9118_resources,
4875ea22 70 .dev = {
90b76491 71 .platform_data = &smsc911x_config,
4875ea22 72 },
04e917b6
YG		 73};
74
aa88f169
NI		 75/*
76 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
77 * If this area erased, this board can not boot.
78 */
04e917b6
YG		 79static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
80 {
aa88f169
NI		 81 .name = "uboot",
82 .offset = 0,
83 .size = (1 * 1024 * 1024),
84 .mask_flags = MTD_WRITEABLE, /* Read-only */
85 }, {
86 .name = "kernel",
87 .offset = MTDPART_OFS_APPEND,
88 .size = (2 * 1024 * 1024),
89 }, {
90 .name = "free-area0",
91 .offset = MTDPART_OFS_APPEND,
92 .size = ((7 * 1024 * 1024) + (512 * 1024)),
04e917b6 93 }, {
aa88f169
NI		 94 .name = "CPLD-Data",
95 .offset = MTDPART_OFS_APPEND,
96 .mask_flags = MTD_WRITEABLE, /* Read-only */
97 .size = (1024 * 128 * 2),
04e917b6 98 }, {
aa88f169
NI		 99 .name = "free-area1",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
04e917b6
YG		 102 },
103};
104
105static struct physmap_flash_data ap325rxa_nor_flash_data = {
106 .width = 2,
107 .parts = ap325rxa_nor_flash_partitions,
108 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
109};
110
111static struct resource ap325rxa_nor_flash_resources[] = {
112 [0] = {
113 .name = "NOR Flash",
114 .start = 0x00000000,
115 .end = 0x00ffffff,
116 .flags = IORESOURCE_MEM,
117 }
118};
119
120static struct platform_device ap325rxa_nor_flash_device = {
121 .name = "physmap-flash",
122 .resource = ap325rxa_nor_flash_resources,
123 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
124 .dev = {
125 .platform_data = &ap325rxa_nor_flash_data,
126 },
127};
128
908978ac
YS		 129static struct mtd_partition nand_partition_info[] = {
130 {
131 .name = "nand_data",
132 .offset = 0,
133 .size = MTDPART_SIZ_FULL,
134 },
135};
136
137static struct resource nand_flash_resources[] = {
138 [0] = {
139 .start = 0xa4530000,
140 .end = 0xa45300ff,
141 .flags = IORESOURCE_MEM,
142 }
143};
144
145static struct sh_flctl_platform_data nand_flash_data = {
146 .parts = nand_partition_info,
147 .nr_parts = ARRAY_SIZE(nand_partition_info),
148 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
149 .has_hwecc = 1,
150};
151
152static struct platform_device nand_flash_device = {
153 .name = "sh_flctl",
154 .resource = nand_flash_resources,
155 .num_resources = ARRAY_SIZE(nand_flash_resources),
156 .dev = {
157 .platform_data = &nand_flash_data,
158 },
159};
160
6968980a
MD		 161#define FPGA_LCDREG 0xB4100180
162#define FPGA_BKLREG 0xB4100212
163#define FPGA_LCDREG_VAL 0x0018
8b2224dc 164#define PORT_MSELCRB 0xA4050182
908978ac
YS		 165#define PORT_HIZCRC 0xA405015C
166#define PORT_DRVCRA 0xA405018A
167#define PORT_DRVCRB 0xA405018C
6968980a 168
018882aa 169static int ap320_wvga_set_brightness(int brightness)
bacbe55b
AC		 170{
171 if (brightness) {
172 gpio_set_value(GPIO_PTS3, 0);
173 __raw_writew(0x100, FPGA_BKLREG);
174 } else {
175 __raw_writew(0, FPGA_BKLREG);
176 gpio_set_value(GPIO_PTS3, 1);
177 }
9c23c516 178
bacbe55b
AC		 179 return 0;
180}
181
018882aa 182static int ap320_wvga_get_brightness(void)
bacbe55b
AC		 183{
184 return gpio_get_value(GPIO_PTS3);
185}
186
018882aa 187static void ap320_wvga_power_on(void)
6968980a
MD		 188{
189 msleep(100);
190
191 /* ASD AP-320/325 LCD ON */
9d56dd3b 192 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
6968980a
MD		 193}
194
018882aa 195static void ap320_wvga_power_off(void)
93356d07 196{
93356d07 197 /* ASD AP-320/325 LCD OFF */
9d56dd3b 198 __raw_writew(0, FPGA_LCDREG);
93356d07
MD		 199}
200
e04008eb 201static const struct fb_videomode ap325rxa_lcdc_modes[] = {
44432407
GL		 202 {
203 .name = "LB070WV1",
204 .xres = 800,
205 .yres = 480,
206 .left_margin = 32,
207 .right_margin = 160,
208 .hsync_len = 8,
209 .upper_margin = 63,
210 .lower_margin = 80,
211 .vsync_len = 1,
212 .sync = 0, /* hsync and vsync are active low */
213 },
214};
215
6968980a
MD		 216static struct sh_mobile_lcdc_info lcdc_info = {
217 .clock_source = LCDC_CLK_EXTERNAL,
218 .ch[0] = {
219 .chan = LCDC_CHAN_MAINLCD,
edd153a3 220 .fourcc = V4L2_PIX_FMT_RGB565,
6968980a
MD		 221 .interface_type = RGB18,
222 .clock_divider = 1,
93ff2598
LP		 223 .lcd_modes = ap325rxa_lcdc_modes,
224 .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
afaad83b
LP		 225 .panel_cfg = {
226 .width = 152, /* 7.0 inch */
ce9c008c 227 .height = 91,
6968980a 228 .display_on = ap320_wvga_power_on,
93356d07 229 .display_off = ap320_wvga_power_off,
bacbe55b
AC		 230 },
231 .bl_info = {
232 .name = "sh_mobile_lcdc_bl",
233 .max_brightness = 1,
43059b0f
LP		 234 .set_brightness = ap320_wvga_set_brightness,
235 .get_brightness = ap320_wvga_get_brightness,
6968980a
MD		 236 },
237 }
238};
239
240static struct resource lcdc_resources[] = {
241 [0] = {
242 .name = "LCDC",
243 .start = 0xfe940000, /* P4-only space */
a6f15ade 244 .end = 0xfe942fff,
6968980a
MD		 245 .flags = IORESOURCE_MEM,
246 },
07905554 247 [1] = {
9c23c516 248 .start = evt2irq(0x580),
07905554
MD		 249 .flags = IORESOURCE_IRQ,
250 },
6968980a
MD		 251};
252
253static struct platform_device lcdc_device = {
254 .name = "sh_mobile_lcdc_fb",
255 .num_resources = ARRAY_SIZE(lcdc_resources),
256 .resource = lcdc_resources,
257 .dev = {
258 .platform_data = &lcdc_info,
259 },
260};
261
86746284
KM		 262static void camera_power(int val)
263{
264 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
265 mdelay(10);
266}
267
e565b518 268#ifdef CONFIG_I2C
47131258 269/* support for the old ncm03j camera */
8b2224dc
MD		 270static unsigned char camera_ncm03j_magic[] =
271{
272 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
273 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
274 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
275 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
276 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
277 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
278 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
279 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
280 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
281 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
282 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
283 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
284 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
285 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
286 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
287 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
288};
289
47131258
KM		 290static int camera_probe(void)
291{
292 struct i2c_adapter *a = i2c_get_adapter(0);
293 struct i2c_msg msg;
294 int ret;
295
37869fa2
MD		 296 if (!a)
297 return -ENODEV;
298
47131258
KM		 299 camera_power(1);
300 msg.addr = 0x6e;
301 msg.buf = camera_ncm03j_magic;
302 msg.len = 2;
303 msg.flags = 0;
304 ret = i2c_transfer(a, &msg, 1);
305 camera_power(0);
306
307 return ret;
308}
309
8b2224dc
MD		 310static int camera_set_capture(struct soc_camera_platform_info *info,
311 int enable)
312{
313 struct i2c_adapter *a = i2c_get_adapter(0);
314 struct i2c_msg msg;
315 int ret = 0;
316 int i;
317
86746284 318 camera_power(0);
8b2224dc
MD		 319 if (!enable)
320 return 0; /* no disable for now */
321
86746284 322 camera_power(1);
8b2224dc
MD		 323 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
324 u_int8_t buf[8];
325
326 msg.addr = 0x6e;
327 msg.buf = buf;
328 msg.len = 2;
329 msg.flags = 0;
330
331 buf[0] = camera_ncm03j_magic[i];
332 buf[1] = camera_ncm03j_magic[i + 1];
333
334 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
335 }
336
337 return ret;
338}
339
7dfff953
GL		 340static int ap325rxa_camera_add(struct soc_camera_device *icd);
341static void ap325rxa_camera_del(struct soc_camera_device *icd);
c41debaf 342
8b2224dc 343static struct soc_camera_platform_info camera_info = {
8b2224dc
MD		 344 .format_name = "UYVY",
345 .format_depth = 16,
346 .format = {
ace6e979 347 .code = V4L2_MBUS_FMT_UYVY8_2X8,
8b2224dc 348 .colorspace = V4L2_COLORSPACE_SMPTE170M,
760697be 349 .field = V4L2_FIELD_NONE,
8b2224dc
MD		 350 .width = 640,
351 .height = 480,
352 },
7e5cf0ae
GL		 353 .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
354 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
355 V4L2_MBUS_DATA_ACTIVE_HIGH,
356 .mbus_type = V4L2_MBUS_PARALLEL,
8b2224dc 357 .set_capture = camera_set_capture,
0f448294
GL		 358};
359
f4cdd757 360static struct soc_camera_link camera_link = {
0f448294
GL		 361 .bus_id = 0,
362 .add_device = ap325rxa_camera_add,
363 .del_device = ap325rxa_camera_del,
364 .module_name = "soc_camera_platform",
365 .priv = &camera_info,
8b2224dc
MD		 366};
367
a3793a0d
GL		 368static struct platform_device *camera_device;
369
370static void ap325rxa_camera_release(struct device *dev)
0bab829d 371{
a3793a0d 372 soc_camera_platform_release(&camera_device);
0bab829d
GL		 373}
374
7dfff953 375static int ap325rxa_camera_add(struct soc_camera_device *icd)
47131258 376{
7dfff953 377 int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
a3793a0d
GL		 378 ap325rxa_camera_release, 0);
379 if (ret < 0)
380 return ret;
47131258 381
a3793a0d
GL		 382 ret = camera_probe();
383 if (ret < 0)
7dfff953 384 soc_camera_platform_del(icd, camera_device, &camera_link);
bc1937b4 385
a3793a0d 386 return ret;
47131258 387}
47131258 388
7dfff953 389static void ap325rxa_camera_del(struct soc_camera_device *icd)
c41debaf 390{
7dfff953 391 soc_camera_platform_del(icd, camera_device, &camera_link);
c41debaf 392}
e565b518 393#endif /* CONFIG_I2C */
8b2224dc 394
47131258
KM		 395static int ov7725_power(struct device *dev, int mode)
396{
397 camera_power(0);
398 if (mode)
399 camera_power(1);
400
401 return 0;
402}
403
8b2224dc 404static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
46368fa0 405 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
8b2224dc
MD		 406};
407
408static struct resource ceu_resources[] = {
409 [0] = {
410 .name = "CEU",
411 .start = 0xfe910000,
412 .end = 0xfe91009f,
413 .flags = IORESOURCE_MEM,
414 },
415 [1] = {
9c23c516 416 .start = evt2irq(0x880),
8b2224dc
MD		 417 .flags = IORESOURCE_IRQ,
418 },
419 [2] = {
420 /* place holder for contiguous memory */
421 },
422};
423
424static struct platform_device ceu_device = {
425 .name = "sh_mobile_ceu",
a42b6dd6 426 .id = 0, /* "ceu0" clock */
8b2224dc
MD		 427 .num_resources = ARRAY_SIZE(ceu_resources),
428 .resource = ceu_resources,
429 .dev = {
430 .platform_data = &sh_mobile_ceu_info,
431 },
432};
433
9c158b15
GL		 434/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
435static struct regulator_consumer_supply fixed3v3_power_consumers[] =
436{
437 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
438 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
439 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
440 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
441};
442
17f81473
MD		 443static struct resource sdhi0_cn3_resources[] = {
444 [0] = {
445 .name = "SDHI0",
446 .start = 0x04ce0000,
d80e9221 447 .end = 0x04ce00ff,
17f81473
MD		 448 .flags = IORESOURCE_MEM,
449 },
450 [1] = {
9c23c516 451 .start = evt2irq(0xe80),
17f81473
MD		 452 .flags = IORESOURCE_IRQ,
453 },
fbdd9a70
MD		 454};
455
365e1087
AH		 456static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
457 .tmio_caps = MMC_CAP_SDIO_IRQ,
458};
459
17f81473
MD		 460static struct platform_device sdhi0_cn3_device = {
461 .name = "sh_mobile_sdhi",
8b431a7e 462 .id = 0, /* "sdhi0" clock */
17f81473
MD		 463 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
464 .resource = sdhi0_cn3_resources,
365e1087
AH		 465 .dev = {
466 .platform_data = &sdhi0_cn3_data,
467 },
fbdd9a70
MD		 468};
469
8b431a7e
MD		 470static struct resource sdhi1_cn7_resources[] = {
471 [0] = {
472 .name = "SDHI1",
473 .start = 0x04cf0000,
d80e9221 474 .end = 0x04cf00ff,
8b431a7e
MD		 475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
9c23c516 478 .start = evt2irq(0x4e0),
8b431a7e
MD		 479 .flags = IORESOURCE_IRQ,
480 },
481};
482
365e1087
AH		 483static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
484 .tmio_caps = MMC_CAP_SDIO_IRQ,
485};
486
8b431a7e
MD		 487static struct platform_device sdhi1_cn7_device = {
488 .name = "sh_mobile_sdhi",
489 .id = 1, /* "sdhi1" clock */
490 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
491 .resource = sdhi1_cn7_resources,
365e1087
AH		 492 .dev = {
493 .platform_data = &sdhi1_cn7_data,
494 },
8b431a7e
MD		 495};
496
026953db 497static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
a3e02706
NI		 498 {
499 I2C_BOARD_INFO("pcf8563", 0x51),
500 },
194a1730
GL		 501};
502
503static struct i2c_board_info ap325rxa_i2c_camera[] = {
47131258
KM		 504 {
505 I2C_BOARD_INFO("ov772x", 0x21),
194a1730
GL		 506 },
507};
508
509static struct ov772x_camera_info ov7725_info = {
284f28ee 510 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
194a1730 511 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
0f448294
GL		 512};
513
514static struct soc_camera_link ov7725_link = {
515 .bus_id = 0,
516 .power = ov7725_power,
517 .board_info = &ap325rxa_i2c_camera[0],
518 .i2c_adapter_id = 0,
0f448294 519 .priv = &ov7725_info,
194a1730
GL		 520};
521
c41debaf
GL		 522static struct platform_device ap325rxa_camera[] = {
523 {
524 .name = "soc-camera-pdrv",
525 .id = 0,
526 .dev = {
0f448294 527 .platform_data = &ov7725_link,
c41debaf
GL		 528 },
529 }, {
530 .name = "soc-camera-pdrv",
531 .id = 1,
532 .dev = {
0f448294 533 .platform_data = &camera_link,
c41debaf 534 },
47131258 535 },
026953db
MD		 536};
537
194a1730
GL		 538static struct platform_device *ap325rxa_devices[] __initdata = {
539 &smsc9118_device,
540 &ap325rxa_nor_flash_device,
541 &lcdc_device,
542 &ceu_device,
543 &nand_flash_device,
17f81473 544 &sdhi0_cn3_device,
8b431a7e 545 &sdhi1_cn7_device,
c41debaf
GL		 546 &ap325rxa_camera[0],
547 &ap325rxa_camera[1],
194a1730
GL		 548};
549
86c7d03a
MD		 550extern char ap325rxa_sdram_enter_start;
551extern char ap325rxa_sdram_enter_end;
552extern char ap325rxa_sdram_leave_start;
553extern char ap325rxa_sdram_leave_end;
554
04e917b6
YG		 555static int __init ap325rxa_devices_setup(void)
556{
86c7d03a
MD		 557 /* register board specific self-refresh code */
558 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
559 &ap325rxa_sdram_enter_start,
560 &ap325rxa_sdram_enter_end,
561 &ap325rxa_sdram_leave_start,
562 &ap325rxa_sdram_leave_end);
563
9c158b15
GL		 564 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
565 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
566 regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
567
16587c45
MD		 568 /* LD3 and LD4 LEDs */
569 gpio_request(GPIO_PTX5, NULL); /* RUN */
570 gpio_direction_output(GPIO_PTX5, 1);
571 gpio_export(GPIO_PTX5, 0);
572
573 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
574 gpio_direction_output(GPIO_PTX4, 0);
575 gpio_export(GPIO_PTX4, 0);
576
577 /* SW1 input */
578 gpio_request(GPIO_PTF7, NULL); /* MODE */
579 gpio_direction_input(GPIO_PTF7);
580 gpio_export(GPIO_PTF7, 0);
581
582 /* LCDC */
16587c45
MD		 583 gpio_request(GPIO_FN_LCDD15, NULL);
584 gpio_request(GPIO_FN_LCDD14, NULL);
585 gpio_request(GPIO_FN_LCDD13, NULL);
586 gpio_request(GPIO_FN_LCDD12, NULL);
587 gpio_request(GPIO_FN_LCDD11, NULL);
588 gpio_request(GPIO_FN_LCDD10, NULL);
589 gpio_request(GPIO_FN_LCDD9, NULL);
590 gpio_request(GPIO_FN_LCDD8, NULL);
591 gpio_request(GPIO_FN_LCDD7, NULL);
592 gpio_request(GPIO_FN_LCDD6, NULL);
593 gpio_request(GPIO_FN_LCDD5, NULL);
594 gpio_request(GPIO_FN_LCDD4, NULL);
595 gpio_request(GPIO_FN_LCDD3, NULL);
596 gpio_request(GPIO_FN_LCDD2, NULL);
597 gpio_request(GPIO_FN_LCDD1, NULL);
598 gpio_request(GPIO_FN_LCDD0, NULL);
599 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
600 gpio_request(GPIO_FN_LCDDCK, NULL);
601 gpio_request(GPIO_FN_LCDVEPWC, NULL);
602 gpio_request(GPIO_FN_LCDVCPWC, NULL);
603 gpio_request(GPIO_FN_LCDVSYN, NULL);
604 gpio_request(GPIO_FN_LCDHSYN, NULL);
605 gpio_request(GPIO_FN_LCDDISP, NULL);
606 gpio_request(GPIO_FN_LCDDON, NULL);
607
608 /* LCD backlight */
609 gpio_request(GPIO_PTS3, NULL);
610 gpio_direction_output(GPIO_PTS3, 1);
611
612 /* CEU */
16587c45
MD		 613 gpio_request(GPIO_FN_VIO_CLK2, NULL);
614 gpio_request(GPIO_FN_VIO_VD2, NULL);
615 gpio_request(GPIO_FN_VIO_HD2, NULL);
616 gpio_request(GPIO_FN_VIO_FLD, NULL);
617 gpio_request(GPIO_FN_VIO_CKO, NULL);
618 gpio_request(GPIO_FN_VIO_D15, NULL);
619 gpio_request(GPIO_FN_VIO_D14, NULL);
620 gpio_request(GPIO_FN_VIO_D13, NULL);
621 gpio_request(GPIO_FN_VIO_D12, NULL);
622 gpio_request(GPIO_FN_VIO_D11, NULL);
623 gpio_request(GPIO_FN_VIO_D10, NULL);
624 gpio_request(GPIO_FN_VIO_D9, NULL);
625 gpio_request(GPIO_FN_VIO_D8, NULL);
626
627 gpio_request(GPIO_PTZ7, NULL);
628 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
629 gpio_request(GPIO_PTZ6, NULL);
630 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
631 gpio_request(GPIO_PTZ5, NULL);
86746284 632 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
16587c45
MD		 633 gpio_request(GPIO_PTZ4, NULL);
634 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
635
9d56dd3b 636 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
8b2224dc 637
908978ac 638 /* FLCTL */
dd0e20e5
PM		 639 gpio_request(GPIO_FN_FCE, NULL);
640 gpio_request(GPIO_FN_NAF7, NULL);
641 gpio_request(GPIO_FN_NAF6, NULL);
642 gpio_request(GPIO_FN_NAF5, NULL);
643 gpio_request(GPIO_FN_NAF4, NULL);
644 gpio_request(GPIO_FN_NAF3, NULL);
645 gpio_request(GPIO_FN_NAF2, NULL);
646 gpio_request(GPIO_FN_NAF1, NULL);
647 gpio_request(GPIO_FN_NAF0, NULL);
648 gpio_request(GPIO_FN_FCDE, NULL);
649 gpio_request(GPIO_FN_FOE, NULL);
650 gpio_request(GPIO_FN_FSC, NULL);
651 gpio_request(GPIO_FN_FWE, NULL);
652 gpio_request(GPIO_FN_FRB, NULL);
908978ac 653
9d56dd3b
PM		 654 __raw_writew(0, PORT_HIZCRC);
655 __raw_writew(0xFFFF, PORT_DRVCRA);
656 __raw_writew(0xFFFF, PORT_DRVCRB);
908978ac 657
8b2224dc 658 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
6968980a 659
8b431a7e 660 /* SDHI0 - CN3 - SD CARD */
17f81473
MD		 661 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
662 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
663 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
664 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
665 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
666 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
667 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
668 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
669
8b431a7e
MD		 670 /* SDHI1 - CN7 - MICRO SD CARD */
671 gpio_request(GPIO_FN_SDHI1CD, NULL);
672 gpio_request(GPIO_FN_SDHI1D3, NULL);
673 gpio_request(GPIO_FN_SDHI1D2, NULL);
674 gpio_request(GPIO_FN_SDHI1D1, NULL);
675 gpio_request(GPIO_FN_SDHI1D0, NULL);
676 gpio_request(GPIO_FN_SDHI1CMD, NULL);
677 gpio_request(GPIO_FN_SDHI1CLK, NULL);
678
026953db
MD		 679 i2c_register_board_info(0, ap325rxa_i2c_devices,
680 ARRAY_SIZE(ap325rxa_i2c_devices));
908978ac 681
04e917b6
YG		 682 return platform_add_devices(ap325rxa_devices,
683 ARRAY_SIZE(ap325rxa_devices));
684}
dbefd606 685arch_initcall(ap325rxa_devices_setup);
04e917b6 686
c01641b4
MD		 687/* Return the board specific boot mode pin configuration */
688static int ap325rxa_mode_pins(void)
689{
690 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
691 * MD3=0: 16-bit Area0 Bus Width
692 * MD5=1: Little Endian
693 * TSTMD=1, MD8=1: Test Mode Disabled
694 */
695 return MODE_PIN5 | MODE_PIN8;
696}
697
04e917b6
YG		 698static struct sh_machine_vector mv_ap325rxa __initmv = {
699 .mv_name = "AP-325RXA",
c01641b4 700 .mv_mode_pins = ap325rxa_mode_pins,
04e917b6 701};
Ubuntu Jammy Linux kernel mirror