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Merge branch 'akpm' (patches from Andrew)
[mirror_ubuntu-jammy-kernel.git] / arch / sh / boards / mach-ecovec24 / setup.c
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aaf9128a 1// SPDX-License-Identifier: GPL-2.0
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2/*
3 * Copyright (C) 2009 Renesas Solutions Corp.
4 *
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
4138b740 6 */
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7#include <asm/clock.h>
8#include <asm/heartbeat.h>
9#include <asm/suspend.h>
10#include <cpu/sh7724.h>
11#include <linux/delay.h>
4138b740 12#include <linux/device.h>
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13#include <linux/i2c.h>
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/input.h>
17#include <linux/input/sh_keysc.h>
18#include <linux/interrupt.h>
19#include <linux/memblock.h>
20#include <linux/mfd/tmio.h>
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21#include <linux/mmc/host.h>
22#include <linux/mmc/sh_mmcif.h>
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23#include <linux/mtd/physmap.h>
24#include <linux/gpio.h>
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25#include <linux/gpio/machine.h>
26#include <linux/platform_data/gpio_backlight.h>
27#include <linux/platform_data/tsc2007.h>
28#include <linux/platform_device.h>
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29#include <linux/regulator/fixed.h>
30#include <linux/regulator/machine.h>
cf8e56bf 31#include <linux/sh_eth.h>
9307d115 32#include <linux/sh_intc.h>
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33#include <linux/spi/mmc_spi.h>
34#include <linux/spi/sh_msiof.h>
35#include <linux/spi/spi.h>
36#include <linux/usb/r8a66597.h>
37#include <linux/usb/renesas_usbhs.h>
a1ad8033 38#include <linux/videodev2.h>
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39
40#include <media/drv-intf/renesas-ceu.h>
41#include <media/i2c/mt9t112.h>
42#include <media/i2c/tw9910.h>
43
1980fdc4 44#include <sound/sh_fsi.h>
064bfada 45#include <sound/simple_card.h>
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46
47#include <video/sh_mobile_lcdc.h>
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48
49/*
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50 * Address Interface BusWidth
51 *-----------------------------------------
52 * 0x0000_0000 uboot 16bit
53 * 0x0004_0000 Linux romImage 16bit
54 * 0x0014_0000 MTD for Linux 16bit
55 * 0x0400_0000 Internal I/O 16/32bit
56 * 0x0800_0000 DRAM 32bit
57 * 0x1800_0000 MFI 16bit
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58 */
59
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60/* SWITCH
61 *------------------------------
62 * DS2[1] = FlashROM write protect ON : write protect
63 * OFF : No write protect
64 * DS2[2] = RMII / TS, SCIF ON : RMII
65 * OFF : TS, SCIF3
66 * DS2[3] = Camera / Video ON : Camera
67 * OFF : NTSC/PAL (IN)
68 * DS2[5] = NTSC_OUT Clock ON : On board OSC
69 * OFF : SH7724 DV_CLK
70 * DS2[6-7] = MMC / SD ON-OFF : SD
71 * OFF-ON : MMC
72 */
73
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74/*
75 * FSI - DA7210
76 *
77 * it needs amixer settings for playing
78 *
79 * amixer set 'HeadPhone' 80
80 * amixer set 'Out Mixer Left DAC Left' on
81 * amixer set 'Out Mixer Right DAC Right' on
82 */
83
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84#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
85static phys_addr_t ceu0_dma_membase;
86static phys_addr_t ceu1_dma_membase;
87
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88/* Heartbeat */
89static unsigned char led_pos[] = { 0, 1, 2, 3 };
a09d2831 90
4138b740 91static struct heartbeat_data heartbeat_data = {
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92 .nr_bits = 4,
93 .bit_pos = led_pos,
94};
95
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96static struct resource heartbeat_resource = {
97 .start = 0xA405012C, /* PTG */
98 .end = 0xA405012E - 1,
99 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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100};
101
102static struct platform_device heartbeat_device = {
103 .name = "heartbeat",
104 .id = -1,
105 .dev = {
106 .platform_data = &heartbeat_data,
107 },
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108 .num_resources = 1,
109 .resource = &heartbeat_resource,
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110};
111
112/* MTD */
113static struct mtd_partition nor_flash_partitions[] = {
114 {
b7056bc1 115 .name = "boot loader",
4138b740 116 .offset = 0,
b7056bc1 117 .size = (5 * 1024 * 1024),
d5ce010c 118 .mask_flags = MTD_WRITEABLE, /* force read-only */
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119 }, {
120 .name = "free-area",
121 .offset = MTDPART_OFS_APPEND,
122 .size = MTDPART_SIZ_FULL,
123 },
124};
125
126static struct physmap_flash_data nor_flash_data = {
127 .width = 2,
128 .parts = nor_flash_partitions,
129 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
130};
131
132static struct resource nor_flash_resources[] = {
133 [0] = {
134 .name = "NOR Flash",
135 .start = 0x00000000,
136 .end = 0x03ffffff,
137 .flags = IORESOURCE_MEM,
138 }
139};
140
141static struct platform_device nor_flash_device = {
142 .name = "physmap-flash",
143 .resource = nor_flash_resources,
144 .num_resources = ARRAY_SIZE(nor_flash_resources),
145 .dev = {
146 .platform_data = &nor_flash_data,
147 },
148};
149
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150/* SH Eth */
151#define SH_ETH_ADDR (0xA4600000)
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152static struct resource sh_eth_resources[] = {
153 [0] = {
154 .start = SH_ETH_ADDR,
155 .end = SH_ETH_ADDR + 0x1FC,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
9307d115 159 .start = evt2irq(0xd60),
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160 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
161 },
162};
163
3ce09334 164static struct sh_eth_plat_data sh_eth_plat = {
35a35408 165 .phy = 0x1f, /* SMSC LAN8700 */
9055f895 166 .phy_interface = PHY_INTERFACE_MODE_MII,
acf3cc28 167 .ether_link_active_low = 1
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168};
169
170static struct platform_device sh_eth_device = {
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171 .name = "sh7724-ether",
172 .id = 0,
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173 .dev = {
174 .platform_data = &sh_eth_plat,
175 },
176 .num_resources = ARRAY_SIZE(sh_eth_resources),
177 .resource = sh_eth_resources,
178};
179
907050a3 180/* USB0 host */
3ce09334 181static void usb0_port_power(int port, int power)
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182{
183 gpio_set_value(GPIO_PTB4, power);
184}
185
186static struct r8a66597_platdata usb0_host_data = {
187 .on_chip = 1,
188 .port_power = usb0_port_power,
189};
190
191static struct resource usb0_host_resources[] = {
192 [0] = {
193 .start = 0xa4d80000,
194 .end = 0xa4d80124 - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 [1] = {
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198 .start = evt2irq(0xa20),
199 .end = evt2irq(0xa20),
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200 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
201 },
202};
203
204static struct platform_device usb0_host_device = {
205 .name = "r8a66597_hcd",
206 .id = 0,
207 .dev = {
208 .dma_mask = NULL, /* not use dma */
209 .coherent_dma_mask = 0xffffffff,
210 .platform_data = &usb0_host_data,
211 },
212 .num_resources = ARRAY_SIZE(usb0_host_resources),
213 .resource = usb0_host_resources,
214};
215
3714a9a0 216/* USB1 host/function */
3ce09334 217static void usb1_port_power(int port, int power)
907050a3 218{
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219 gpio_set_value(GPIO_PTB5, power);
220}
221
3714a9a0 222static struct r8a66597_platdata usb1_common_data = {
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223 .on_chip = 1,
224 .port_power = usb1_port_power,
225};
226
3714a9a0 227static struct resource usb1_common_resources[] = {
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228 [0] = {
229 .start = 0xa4d90000,
230 .end = 0xa4d90124 - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
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234 .start = evt2irq(0xa40),
235 .end = evt2irq(0xa40),
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236 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
237 },
238};
239
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240static struct platform_device usb1_common_device = {
241 /* .name will be added in arch_setup */
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242 .id = 1,
243 .dev = {
244 .dma_mask = NULL, /* not use dma */
245 .coherent_dma_mask = 0xffffffff,
3714a9a0 246 .platform_data = &usb1_common_data,
907050a3 247 },
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248 .num_resources = ARRAY_SIZE(usb1_common_resources),
249 .resource = usb1_common_resources,
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250};
251
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252/*
253 * USBHS
254 */
255static int usbhs_get_id(struct platform_device *pdev)
256{
257 return gpio_get_value(GPIO_PTB3);
258}
259
225da3e3 260static int usbhs_phy_reset(struct platform_device *pdev)
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261{
262 /* enable vbus if HOST */
263 if (!gpio_get_value(GPIO_PTB3))
264 gpio_set_value(GPIO_PTB5, 1);
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265
266 return 0;
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267}
268
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269static struct renesas_usbhs_platform_info usbhs_info = {
270 .platform_callback = {
271 .get_id = usbhs_get_id,
1ca8fe38 272 .phy_reset = usbhs_phy_reset,
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273 },
274 .driver_param = {
275 .buswait_bwait = 4,
276 .detection_delay = 5,
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277 .d0_tx_id = SHDMA_SLAVE_USB1D0_TX,
278 .d0_rx_id = SHDMA_SLAVE_USB1D0_RX,
279 .d1_tx_id = SHDMA_SLAVE_USB1D1_TX,
280 .d1_rx_id = SHDMA_SLAVE_USB1D1_RX,
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281 },
282};
283
284static struct resource usbhs_resources[] = {
285 [0] = {
286 .start = 0xa4d90000,
287 .end = 0xa4d90124 - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
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291 .start = evt2irq(0xa40),
292 .end = evt2irq(0xa40),
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293 .flags = IORESOURCE_IRQ,
294 },
295};
296
297static struct platform_device usbhs_device = {
298 .name = "renesas_usbhs",
299 .id = 1,
300 .dev = {
301 .dma_mask = NULL, /* not use dma */
302 .coherent_dma_mask = 0xffffffff,
303 .platform_data = &usbhs_info,
304 },
305 .num_resources = ARRAY_SIZE(usbhs_resources),
306 .resource = usbhs_resources,
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307};
308
fe79f919 309/* LCDC and backlight */
e04008eb 310static const struct fb_videomode ecovec_lcd_modes[] = {
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311 {
312 .name = "Panel",
313 .xres = 800,
314 .yres = 480,
315 .left_margin = 220,
316 .right_margin = 110,
317 .hsync_len = 70,
318 .upper_margin = 20,
319 .lower_margin = 5,
320 .vsync_len = 5,
321 .sync = 0, /* hsync and vsync are active low */
322 },
323};
324
e04008eb 325static const struct fb_videomode ecovec_dvi_modes[] = {
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326 {
327 .name = "DVI",
328 .xres = 1280,
329 .yres = 720,
330 .left_margin = 220,
331 .right_margin = 110,
332 .hsync_len = 40,
333 .upper_margin = 20,
334 .lower_margin = 5,
335 .vsync_len = 5,
336 .sync = 0, /* hsync and vsync are active low */
337 },
338};
339
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340static struct sh_mobile_lcdc_info lcdc_info = {
341 .ch[0] = {
342 .interface_type = RGB18,
343 .chan = LCDC_CHAN_MAINLCD,
edd153a3 344 .fourcc = V4L2_PIX_FMT_RGB565,
afaad83b 345 .panel_cfg = { /* 7.0 inch */
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346 .width = 152,
347 .height = 91,
348 },
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349 }
350};
351
352static struct resource lcdc_resources[] = {
353 [0] = {
354 .name = "LCDC",
355 .start = 0xfe940000,
a6f15ade 356 .end = 0xfe942fff,
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357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
9307d115 360 .start = evt2irq(0xf40),
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361 .flags = IORESOURCE_IRQ,
362 },
363};
364
365static struct platform_device lcdc_device = {
366 .name = "sh_mobile_lcdc_fb",
367 .num_resources = ARRAY_SIZE(lcdc_resources),
368 .resource = lcdc_resources,
369 .dev = {
370 .platform_data = &lcdc_info,
371 },
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372};
373
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374static struct gpio_backlight_platform_data gpio_backlight_data = {
375 .fbdev = &lcdc_device.dev,
376 .gpio = GPIO_PTR1,
377 .def_value = 1,
378 .name = "backlight",
379};
380
381static struct platform_device gpio_backlight_device = {
382 .name = "gpio-backlight",
383 .dev = {
384 .platform_data = &gpio_backlight_data,
385 },
386};
387
2153ad32 388/* CEU0 */
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389static struct ceu_platform_data ceu0_pdata = {
390 .num_subdevs = 2,
391 .subdevs = {
392 { /* [0] = mt9t112 */
393 .flags = 0,
394 .bus_width = 8,
395 .bus_shift = 0,
396 .i2c_adapter_id = 0,
397 .i2c_address = 0x3c,
398 },
399 { /* [1] = tw9910 */
400 .flags = 0,
401 .bus_width = 8,
402 .bus_shift = 0,
403 .i2c_adapter_id = 0,
404 .i2c_address = 0x45,
405 },
406 },
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407};
408
409static struct resource ceu0_resources[] = {
410 [0] = {
411 .name = "CEU0",
412 .start = 0xfe910000,
413 .end = 0xfe91009f,
414 .flags = IORESOURCE_MEM,
415 },
416 [1] = {
9307d115 417 .start = evt2irq(0x880),
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418 .flags = IORESOURCE_IRQ,
419 },
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420};
421
422static struct platform_device ceu0_device = {
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423 .name = "renesas-ceu",
424 .id = 0, /* ceu.0 */
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425 .num_resources = ARRAY_SIZE(ceu0_resources),
426 .resource = ceu0_resources,
427 .dev = {
c2f9b05f 428 .platform_data = &ceu0_pdata,
2153ad32 429 },
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430};
431
432/* CEU1 */
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433static struct ceu_platform_data ceu1_pdata = {
434 .num_subdevs = 1,
435 .subdevs = {
436 { /* [0] = mt9t112 */
437 .flags = 0,
438 .bus_width = 8,
439 .bus_shift = 0,
440 .i2c_adapter_id = 1,
441 .i2c_address = 0x3c,
442 },
443 },
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444};
445
446static struct resource ceu1_resources[] = {
447 [0] = {
448 .name = "CEU1",
449 .start = 0xfe914000,
450 .end = 0xfe91409f,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
9307d115 454 .start = evt2irq(0x9e0),
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455 .flags = IORESOURCE_IRQ,
456 },
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457};
458
459static struct platform_device ceu1_device = {
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460 .name = "renesas-ceu",
461 .id = 1, /* ceu.1 */
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462 .num_resources = ARRAY_SIZE(ceu1_resources),
463 .resource = ceu1_resources,
464 .dev = {
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465 .platform_data = &ceu1_pdata,
466 },
467};
468
469/* Power up/down GPIOs for camera devices and video decoder */
470static struct gpiod_lookup_table tw9910_gpios = {
471 .dev_id = "0-0045",
472 .table = {
473 GPIO_LOOKUP("sh7724_pfc", GPIO_PTU2, "pdn", GPIO_ACTIVE_HIGH),
474 },
475};
476
477static struct gpiod_lookup_table mt9t112_0_gpios = {
478 .dev_id = "0-003c",
479 .table = {
480 GPIO_LOOKUP("sh7724_pfc", GPIO_PTA3, "standby",
481 GPIO_ACTIVE_HIGH),
482 },
483};
484
485static struct gpiod_lookup_table mt9t112_1_gpios = {
486 .dev_id = "1-003c",
487 .table = {
488 GPIO_LOOKUP("sh7724_pfc", GPIO_PTA4, "standby",
489 GPIO_ACTIVE_HIGH),
2153ad32 490 },
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491};
492
125ecce6 493/* I2C device */
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494static struct tw9910_video_info tw9910_info = {
495 .buswidth = 8,
496 .mpout = TW9910_MPO_FIELD,
497};
498
499static struct mt9t112_platform_data mt9t112_0_pdata = {
500 .flags = MT9T112_FLAG_PCLK_RISING_EDGE,
501 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
502};
503
504static struct mt9t112_platform_data mt9t112_1_pdata = {
505 .flags = MT9T112_FLAG_PCLK_RISING_EDGE,
506 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
507};
508
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509static struct i2c_board_info i2c0_devices[] = {
510 {
511 I2C_BOARD_INFO("da7210", 0x1a),
512 },
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513 {
514 I2C_BOARD_INFO("tw9910", 0x45),
515 .platform_data = &tw9910_info,
516 },
517 {
518 /* 1st camera */
519 I2C_BOARD_INFO("mt9t112", 0x3c),
520 .platform_data = &mt9t112_0_pdata,
521 },
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522};
523
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524static struct i2c_board_info i2c1_devices[] = {
525 {
526 I2C_BOARD_INFO("r2025sd", 0x32),
527 },
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528 {
529 I2C_BOARD_INFO("lis3lv02d", 0x1c),
9307d115 530 .irq = evt2irq(0x620),
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531 },
532 {
533 /* 2nd camera */
534 I2C_BOARD_INFO("mt9t112", 0x3c),
535 .platform_data = &mt9t112_1_pdata,
536 },
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537};
538
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539/* KEYSC */
540static struct sh_keysc_info keysc_info = {
541 .mode = SH_KEYSC_MODE_1,
542 .scan_timing = 3,
543 .delay = 50,
544 .kycr2_delay = 100,
545 .keycodes = { KEY_1, 0, 0, 0, 0,
546 KEY_2, 0, 0, 0, 0,
547 KEY_3, 0, 0, 0, 0,
548 KEY_4, 0, 0, 0, 0,
549 KEY_5, 0, 0, 0, 0,
550 KEY_6, 0, 0, 0, 0, },
551};
552
553static struct resource keysc_resources[] = {
554 [0] = {
555 .name = "KEYSC",
556 .start = 0x044b0000,
557 .end = 0x044b000f,
558 .flags = IORESOURCE_MEM,
559 },
560 [1] = {
9307d115 561 .start = evt2irq(0xbe0),
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562 .flags = IORESOURCE_IRQ,
563 },
564};
565
566static struct platform_device keysc_device = {
567 .name = "sh_keysc",
568 .id = 0, /* keysc0 clock */
569 .num_resources = ARRAY_SIZE(keysc_resources),
570 .resource = keysc_resources,
571 .dev = {
572 .platform_data = &keysc_info,
573 },
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574};
575
8810e055 576/* TouchScreen */
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577#define IRQ0 evt2irq(0x600)
578
07f9e5cf 579static int ts_get_pendown_state(struct device *dev)
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580{
581 int val = 0;
582 gpio_free(GPIO_FN_INTC_IRQ0);
583 gpio_request(GPIO_PTZ0, NULL);
584 gpio_direction_input(GPIO_PTZ0);
585
586 val = gpio_get_value(GPIO_PTZ0);
587
588 gpio_free(GPIO_PTZ0);
589 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
590
591 return val ? 0 : 1;
592}
593
594static int ts_init(void)
595{
596 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
597 return 0;
598}
599
3ce09334 600static struct tsc2007_platform_data tsc2007_info = {
8810e055 601 .model = 2007,
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602 .x_plate_ohms = 180,
603 .get_pendown_state = ts_get_pendown_state,
604 .init_platform_hw = ts_init,
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605};
606
607static struct i2c_board_info ts_i2c_clients = {
608 I2C_BOARD_INFO("tsc2007", 0x48),
609 .type = "tsc2007",
610 .platform_data = &tsc2007_info,
611 .irq = IRQ0,
612};
613
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614static struct regulator_consumer_supply cn12_power_consumers[] =
615{
616 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
617 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
618 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
619 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
620};
621
622static struct regulator_init_data cn12_power_init_data = {
623 .constraints = {
624 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
625 },
626 .num_consumer_supplies = ARRAY_SIZE(cn12_power_consumers),
627 .consumer_supplies = cn12_power_consumers,
628};
629
630static struct fixed_voltage_config cn12_power_info = {
631 .supply_name = "CN12 SD/MMC Vdd",
632 .microvolts = 3300000,
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GL
633 .enable_high = 1,
634 .init_data = &cn12_power_init_data,
635};
636
637static struct platform_device cn12_power = {
638 .name = "reg-fixed-voltage",
639 .id = 0,
640 .dev = {
641 .platform_data = &cn12_power_info,
642 },
643};
644
efdfeb07
LW
645static struct gpiod_lookup_table cn12_power_gpiod_table = {
646 .dev_id = "reg-fixed-voltage.0",
647 .table = {
648 /* Offset 7 on port B */
649 GPIO_LOOKUP("sh7724_pfc", GPIO_PTB7,
650 NULL, GPIO_ACTIVE_HIGH),
651 { },
652 },
653};
654
5744c881 655#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1238c684 656/* SDHI0 */
d4c191df
GL
657static struct regulator_consumer_supply sdhi0_power_consumers[] =
658{
659 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
660 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
661};
662
663static struct regulator_init_data sdhi0_power_init_data = {
664 .constraints = {
665 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
666 },
667 .num_consumer_supplies = ARRAY_SIZE(sdhi0_power_consumers),
668 .consumer_supplies = sdhi0_power_consumers,
669};
670
671static struct fixed_voltage_config sdhi0_power_info = {
672 .supply_name = "CN11 SD/MMC Vdd",
673 .microvolts = 3300000,
d4c191df
GL
674 .enable_high = 1,
675 .init_data = &sdhi0_power_init_data,
676};
677
678static struct platform_device sdhi0_power = {
679 .name = "reg-fixed-voltage",
680 .id = 1,
681 .dev = {
682 .platform_data = &sdhi0_power_info,
683 },
684};
685
efdfeb07
LW
686static struct gpiod_lookup_table sdhi0_power_gpiod_table = {
687 .dev_id = "reg-fixed-voltage.1",
688 .table = {
689 /* Offset 6 on port B */
690 GPIO_LOOKUP("sh7724_pfc", GPIO_PTB6,
691 NULL, GPIO_ACTIVE_HIGH),
692 { },
693 },
694};
695
faed9303
LW
696static struct gpiod_lookup_table sdhi0_gpio_table = {
697 .dev_id = "sh_mobile_sdhi.0",
698 .table = {
699 /* Card detect */
700 GPIO_LOOKUP("sh7724_pfc", GPIO_PTY7, "cd", GPIO_ACTIVE_LOW),
701 { },
702 },
703};
704
84f11d5b
KM
705static struct tmio_mmc_data sdhi0_info = {
706 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
707 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
708 .capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
4eb80146 709 MMC_CAP_NEEDS_POLL,
98779ad8
MD
710};
711
96987d96
KM
712static struct resource sdhi0_resources[] = {
713 [0] = {
714 .name = "SDHI0",
715 .start = 0x04ce0000,
d80e9221 716 .end = 0x04ce00ff,
96987d96
KM
717 .flags = IORESOURCE_MEM,
718 },
719 [1] = {
9307d115 720 .start = evt2irq(0xe80),
96987d96
KM
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct platform_device sdhi0_device = {
726 .name = "sh_mobile_sdhi",
727 .num_resources = ARRAY_SIZE(sdhi0_resources),
728 .resource = sdhi0_resources,
729 .id = 0,
98779ad8
MD
730 .dev = {
731 .platform_data = &sdhi0_info,
732 },
96987d96
KM
733};
734
d4c191df
GL
735#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
736/* SDHI1 */
84f11d5b
KM
737static struct tmio_mmc_data sdhi1_info = {
738 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
739 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
740 .capabilities = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
4eb80146 741 MMC_CAP_NEEDS_POLL,
faed9303
LW
742};
743
744static struct gpiod_lookup_table sdhi1_gpio_table = {
745 .dev_id = "sh_mobile_sdhi.1",
746 .table = {
747 /* Card detect */
748 GPIO_LOOKUP("sh7724_pfc", GPIO_PTW7, "cd", GPIO_ACTIVE_LOW),
749 { },
750 },
98779ad8
MD
751};
752
96987d96
KM
753static struct resource sdhi1_resources[] = {
754 [0] = {
755 .name = "SDHI1",
756 .start = 0x04cf0000,
d80e9221 757 .end = 0x04cf00ff,
96987d96
KM
758 .flags = IORESOURCE_MEM,
759 },
760 [1] = {
9307d115 761 .start = evt2irq(0x4e0),
96987d96
KM
762 .flags = IORESOURCE_IRQ,
763 },
764};
765
766static struct platform_device sdhi1_device = {
767 .name = "sh_mobile_sdhi",
768 .num_resources = ARRAY_SIZE(sdhi1_resources),
769 .resource = sdhi1_resources,
770 .id = 1,
98779ad8
MD
771 .dev = {
772 .platform_data = &sdhi1_info,
773 },
96987d96 774};
1238c684 775#endif /* CONFIG_MMC_SH_MMCIF */
96987d96 776
1ce4da7a
MD
777#else
778
9503e891 779/* MMC SPI */
1ce4da7a
MD
780static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
781{
782 gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
783}
784
785static struct mmc_spi_platform_data mmc_spi_info = {
1ce4da7a 786 .caps = MMC_CAP_NEEDS_POLL,
afa2c940 787 .caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
1ce4da7a
MD
788 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
789 .setpower = mmc_spi_setpower,
5716fb9b
LW
790};
791
792static struct gpiod_lookup_table mmc_spi_gpio_table = {
793 .dev_id = "mmc_spi.0", /* device "mmc_spi" @ CS0 */
794 .table = {
795 /* Card detect */
796 GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY7, NULL, 0,
797 GPIO_ACTIVE_LOW),
798 /* Write protect */
799 GPIO_LOOKUP_IDX("sh7724_pfc", GPIO_PTY6, NULL, 1,
800 GPIO_ACTIVE_HIGH),
801 { },
802 },
1ce4da7a
MD
803};
804
805static struct spi_board_info spi_bus[] = {
806 {
807 .modalias = "mmc_spi",
808 .platform_data = &mmc_spi_info,
809 .max_speed_hz = 5000000,
810 .mode = SPI_MODE_0,
811 .controller_data = (void *) GPIO_PTM4,
812 },
813};
814
9503e891 815/* MSIOF0 */
1ce4da7a
MD
816static struct sh_msiof_spi_info msiof0_data = {
817 .num_chipselect = 1,
818};
819
820static struct resource msiof0_resources[] = {
821 [0] = {
822 .name = "MSIOF0",
823 .start = 0xa4c40000,
824 .end = 0xa4c40063,
825 .flags = IORESOURCE_MEM,
826 },
827 [1] = {
9307d115 828 .start = evt2irq(0xc80),
1ce4da7a
MD
829 .flags = IORESOURCE_IRQ,
830 },
831};
832
833static struct platform_device msiof0_device = {
834 .name = "spi_sh_msiof",
835 .id = 0, /* MSIOF0 */
836 .dev = {
837 .platform_data = &msiof0_data,
838 },
839 .num_resources = ARRAY_SIZE(msiof0_resources),
840 .resource = msiof0_resources,
1ce4da7a
MD
841};
842
843#endif
844
1980fdc4 845/* FSI */
1980fdc4
KM
846static struct resource fsi_resources[] = {
847 [0] = {
848 .name = "FSI",
849 .start = 0xFE3C0000,
850 .end = 0xFE3C021d,
851 .flags = IORESOURCE_MEM,
852 },
853 [1] = {
9307d115 854 .start = evt2irq(0xf80),
1980fdc4
KM
855 .flags = IORESOURCE_IRQ,
856 },
857};
858
859static struct platform_device fsi_device = {
860 .name = "sh_fsi",
861 .id = 0,
862 .num_resources = ARRAY_SIZE(fsi_resources),
863 .resource = fsi_resources,
1980fdc4
KM
864};
865
064bfada
KM
866static struct asoc_simple_card_info fsi_da7210_info = {
867 .name = "DA7210",
868 .card = "FSIB-DA7210",
064bfada
KM
869 .codec = "da7210.0-001a",
870 .platform = "sh_fsi.0",
c7a507ee 871 .daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
a4a2992c
KM
872 .cpu_dai = {
873 .name = "fsib-dai",
a4a2992c
KM
874 },
875 .codec_dai = {
876 .name = "da7210-hifi",
a4a2992c 877 },
064bfada
KM
878};
879
880static struct platform_device fsi_da7210_device = {
881 .name = "asoc-simple-card",
882 .dev = {
883 .platform_data = &fsi_da7210_info,
ffb83e8c
KM
884 .coherent_dma_mask = DMA_BIT_MASK(32),
885 .dma_mask = &fsi_da7210_device.dev.coherent_dma_mask,
064bfada
KM
886 },
887};
888
889
26365716
KM
890/* IrDA */
891static struct resource irda_resources[] = {
892 [0] = {
893 .name = "IrDA",
894 .start = 0xA45D0000,
895 .end = 0xA45D0049,
896 .flags = IORESOURCE_MEM,
897 },
898 [1] = {
9307d115 899 .start = evt2irq(0x480),
26365716
KM
900 .flags = IORESOURCE_IRQ,
901 },
902};
903
904static struct platform_device irda_device = {
905 .name = "sh_sir",
906 .num_resources = ARRAY_SIZE(irda_resources),
907 .resource = irda_resources,
908};
909
b5dcee22 910#include <media/i2c/ak881x.h>
d647f0b7 911#include <media/drv-intf/sh_vou.h>
aee5ab0b 912
3ce09334 913static struct ak881x_pdata ak881x_pdata = {
aee5ab0b
GL
914 .flags = AK881X_IF_MODE_SLAVE,
915};
916
917static struct i2c_board_info ak8813 = {
918 I2C_BOARD_INFO("ak8813", 0x20),
919 .platform_data = &ak881x_pdata,
920};
921
3ce09334 922static struct sh_vou_pdata sh_vou_pdata = {
aee5ab0b
GL
923 .bus_fmt = SH_VOU_BUS_8BIT,
924 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
925 .board_info = &ak8813,
926 .i2c_adap = 0,
aee5ab0b
GL
927};
928
929static struct resource sh_vou_resources[] = {
930 [0] = {
931 .start = 0xfe960000,
932 .end = 0xfe962043,
933 .flags = IORESOURCE_MEM,
934 },
935 [1] = {
9307d115 936 .start = evt2irq(0x8e0),
aee5ab0b
GL
937 .flags = IORESOURCE_IRQ,
938 },
939};
940
941static struct platform_device vou_device = {
942 .name = "sh-vou",
943 .id = -1,
944 .num_resources = ARRAY_SIZE(sh_vou_resources),
945 .resource = sh_vou_resources,
946 .dev = {
947 .platform_data = &sh_vou_pdata,
948 },
aee5ab0b
GL
949};
950
5744c881 951#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
1238c684 952/* SH_MMCIF */
1238c684
YG
953static struct resource sh_mmcif_resources[] = {
954 [0] = {
955 .name = "SH_MMCIF",
956 .start = 0xA4CA0000,
957 .end = 0xA4CA00FF,
958 .flags = IORESOURCE_MEM,
959 },
960 [1] = {
961 /* MMC2I */
9307d115 962 .start = evt2irq(0x5a0),
1238c684
YG
963 .flags = IORESOURCE_IRQ,
964 },
965 [2] = {
966 /* MMC3I */
9307d115 967 .start = evt2irq(0x5c0),
1238c684
YG
968 .flags = IORESOURCE_IRQ,
969 },
970};
971
3ce09334 972static struct sh_mmcif_plat_data sh_mmcif_plat = {
1238c684
YG
973 .sup_pclk = 0, /* SH7724: Max Pclk/2 */
974 .caps = MMC_CAP_4_BIT_DATA |
975 MMC_CAP_8_BIT_DATA |
976 MMC_CAP_NEEDS_POLL,
977 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
978};
979
980static struct platform_device sh_mmcif_device = {
981 .name = "sh_mmcif",
982 .id = 0,
983 .dev = {
984 .platform_data = &sh_mmcif_plat,
985 },
986 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
987 .resource = sh_mmcif_resources,
988};
989#endif
990
c2f9b05f
JM
991static struct platform_device *ecovec_ceu_devices[] __initdata = {
992 &ceu0_device,
993 &ceu1_device,
994};
995
4138b740
KM
996static struct platform_device *ecovec_devices[] __initdata = {
997 &heartbeat_device,
998 &nor_flash_device,
35a35408 999 &sh_eth_device,
907050a3 1000 &usb0_host_device,
3714a9a0 1001 &usb1_common_device,
fb2e7394 1002 &usbhs_device,
fa3ba51b 1003 &lcdc_device,
fe79f919 1004 &gpio_backlight_device,
e9103e74 1005 &keysc_device,
d4c191df 1006 &cn12_power,
5744c881 1007#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
d4c191df 1008 &sdhi0_power,
96987d96 1009 &sdhi0_device,
5744c881 1010#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
96987d96 1011 &sdhi1_device,
1238c684 1012#endif
1ce4da7a
MD
1013#else
1014 &msiof0_device,
1015#endif
1980fdc4 1016 &fsi_device,
064bfada 1017 &fsi_da7210_device,
26365716 1018 &irda_device,
aee5ab0b 1019 &vou_device,
5744c881 1020#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
1238c684
YG
1021 &sh_mmcif_device,
1022#endif
4138b740
KM
1023};
1024
6b3b5575 1025#ifdef CONFIG_I2C
4907d57f
KM
1026#define EEPROM_ADDR 0x50
1027static u8 mac_read(struct i2c_adapter *a, u8 command)
1028{
1029 struct i2c_msg msg[2];
1030 u8 buf;
1031 int ret;
1032
1033 msg[0].addr = EEPROM_ADDR;
1034 msg[0].flags = 0;
1035 msg[0].len = 1;
1036 msg[0].buf = &command;
1037
1038 msg[1].addr = EEPROM_ADDR;
1039 msg[1].flags = I2C_M_RD;
1040 msg[1].len = 1;
1041 msg[1].buf = &buf;
1042
1043 ret = i2c_transfer(a, msg, 2);
1044 if (ret < 0) {
1045 printk(KERN_ERR "error %d\n", ret);
1046 buf = 0xff;
1047 }
1048
1049 return buf;
1050}
1051
376abbb4 1052static void __init sh_eth_init(struct sh_eth_plat_data *pd)
4907d57f
KM
1053{
1054 struct i2c_adapter *a = i2c_get_adapter(1);
4907d57f
KM
1055 int i;
1056
1057 if (!a) {
1058 pr_err("can not get I2C 1\n");
1059 return;
1060 }
1061
25985edc 1062 /* read MAC address from EEPROM */
376abbb4
MD
1063 for (i = 0; i < sizeof(pd->mac_addr); i++) {
1064 pd->mac_addr[i] = mac_read(a, 0x10 + i);
4907d57f
KM
1065 msleep(10);
1066 }
b230eb32
KM
1067
1068 i2c_put_adapter(a);
4907d57f 1069}
6b3b5575
MD
1070#else
1071static void __init sh_eth_init(struct sh_eth_plat_data *pd)
1072{
1073 pr_err("unable to read sh_eth MAC address\n");
1074}
1075#endif
4907d57f 1076
fa3ba51b 1077#define PORT_HIZA 0xA4050158
ea15edb2 1078#define IODRIVEA 0xA405018A
eb0cd9e8
MD
1079
1080extern char ecovec24_sdram_enter_start;
1081extern char ecovec24_sdram_enter_end;
1082extern char ecovec24_sdram_leave_start;
1083extern char ecovec24_sdram_leave_end;
1084
4907d57f 1085static int __init arch_setup(void)
4138b740 1086{
1980fdc4 1087 struct clk *clk;
4eb80146 1088 bool cn12_enabled = false;
1980fdc4 1089
eb0cd9e8 1090 /* register board specific self-refresh code */
2839bd61
MD
1091 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
1092 SUSP_SH_RSTANDBY,
eb0cd9e8
MD
1093 &ecovec24_sdram_enter_start,
1094 &ecovec24_sdram_enter_end,
1095 &ecovec24_sdram_leave_start,
1096 &ecovec24_sdram_leave_end);
1097
f78bab30
MD
1098 /* enable STATUS0, STATUS2 and PDSTATUS */
1099 gpio_request(GPIO_FN_STATUS0, NULL);
1100 gpio_request(GPIO_FN_STATUS2, NULL);
1101 gpio_request(GPIO_FN_PDSTATUS, NULL);
1102
4138b740
KM
1103 /* enable SCIFA0 */
1104 gpio_request(GPIO_FN_SCIF0_TXD, NULL);
1105 gpio_request(GPIO_FN_SCIF0_RXD, NULL);
4138b740
KM
1106
1107 /* enable debug LED */
1108 gpio_request(GPIO_PTG0, NULL);
1109 gpio_request(GPIO_PTG1, NULL);
1110 gpio_request(GPIO_PTG2, NULL);
1111 gpio_request(GPIO_PTG3, NULL);
b7056bc1
KM
1112 gpio_direction_output(GPIO_PTG0, 0);
1113 gpio_direction_output(GPIO_PTG1, 0);
1114 gpio_direction_output(GPIO_PTG2, 0);
1115 gpio_direction_output(GPIO_PTG3, 0);
9d56dd3b 1116 __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
4138b740 1117
35a35408
KM
1118 /* enable SH-Eth */
1119 gpio_request(GPIO_PTA1, NULL);
1120 gpio_direction_output(GPIO_PTA1, 1);
1121 mdelay(20);
1122
1123 gpio_request(GPIO_FN_RMII_RXD0, NULL);
1124 gpio_request(GPIO_FN_RMII_RXD1, NULL);
1125 gpio_request(GPIO_FN_RMII_TXD0, NULL);
1126 gpio_request(GPIO_FN_RMII_TXD1, NULL);
1127 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
1128 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
1129 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
1130 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
1131 gpio_request(GPIO_FN_MDIO, NULL);
1132 gpio_request(GPIO_FN_MDC, NULL);
1133 gpio_request(GPIO_FN_LNKSTA, NULL);
1134
907050a3 1135 /* enable USB */
9d56dd3b
PM
1136 __raw_writew(0x0000, 0xA4D80000);
1137 __raw_writew(0x0000, 0xA4D90000);
907050a3
KM
1138 gpio_request(GPIO_PTB3, NULL);
1139 gpio_request(GPIO_PTB4, NULL);
1140 gpio_request(GPIO_PTB5, NULL);
1141 gpio_direction_input(GPIO_PTB3);
1142 gpio_direction_output(GPIO_PTB4, 0);
1143 gpio_direction_output(GPIO_PTB5, 0);
9d56dd3b
PM
1144 __raw_writew(0x0600, 0xa40501d4);
1145 __raw_writew(0x0600, 0xa4050192);
907050a3 1146
3714a9a0
KM
1147 if (gpio_get_value(GPIO_PTB3)) {
1148 printk(KERN_INFO "USB1 function is selected\n");
1149 usb1_common_device.name = "r8a66597_udc";
1150 } else {
1151 printk(KERN_INFO "USB1 host is selected\n");
1152 usb1_common_device.name = "r8a66597_hcd";
1153 }
1154
fa3ba51b
KM
1155 /* enable LCDC */
1156 gpio_request(GPIO_FN_LCDD23, NULL);
1157 gpio_request(GPIO_FN_LCDD22, NULL);
1158 gpio_request(GPIO_FN_LCDD21, NULL);
1159 gpio_request(GPIO_FN_LCDD20, NULL);
1160 gpio_request(GPIO_FN_LCDD19, NULL);
1161 gpio_request(GPIO_FN_LCDD18, NULL);
1162 gpio_request(GPIO_FN_LCDD17, NULL);
1163 gpio_request(GPIO_FN_LCDD16, NULL);
1164 gpio_request(GPIO_FN_LCDD15, NULL);
1165 gpio_request(GPIO_FN_LCDD14, NULL);
1166 gpio_request(GPIO_FN_LCDD13, NULL);
1167 gpio_request(GPIO_FN_LCDD12, NULL);
1168 gpio_request(GPIO_FN_LCDD11, NULL);
1169 gpio_request(GPIO_FN_LCDD10, NULL);
1170 gpio_request(GPIO_FN_LCDD9, NULL);
1171 gpio_request(GPIO_FN_LCDD8, NULL);
1172 gpio_request(GPIO_FN_LCDD7, NULL);
1173 gpio_request(GPIO_FN_LCDD6, NULL);
1174 gpio_request(GPIO_FN_LCDD5, NULL);
1175 gpio_request(GPIO_FN_LCDD4, NULL);
1176 gpio_request(GPIO_FN_LCDD3, NULL);
1177 gpio_request(GPIO_FN_LCDD2, NULL);
1178 gpio_request(GPIO_FN_LCDD1, NULL);
1179 gpio_request(GPIO_FN_LCDD0, NULL);
1180 gpio_request(GPIO_FN_LCDDISP, NULL);
1181 gpio_request(GPIO_FN_LCDHSYN, NULL);
1182 gpio_request(GPIO_FN_LCDDCK, NULL);
1183 gpio_request(GPIO_FN_LCDVSYN, NULL);
1184 gpio_request(GPIO_FN_LCDDON, NULL);
1185 gpio_request(GPIO_FN_LCDLCLK, NULL);
9d56dd3b 1186 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
fa3ba51b
KM
1187
1188 gpio_request(GPIO_PTE6, NULL);
1189 gpio_request(GPIO_PTU1, NULL);
fa3ba51b
KM
1190 gpio_request(GPIO_PTA2, NULL);
1191 gpio_direction_input(GPIO_PTE6);
1192 gpio_direction_output(GPIO_PTU1, 0);
fa3ba51b
KM
1193 gpio_direction_output(GPIO_PTA2, 0);
1194
82b33221 1195 /* I/O buffer drive ability is high */
9d56dd3b 1196 __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
ea15edb2 1197
fa3ba51b
KM
1198 if (gpio_get_value(GPIO_PTE6)) {
1199 /* DVI */
1200 lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
44432407 1201 lcdc_info.ch[0].clock_divider = 1;
93ff2598
LP
1202 lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
1203 lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
fa3ba51b 1204
fe79f919
LP
1205 /* No backlight */
1206 gpio_backlight_data.fbdev = NULL;
1207
fa3ba51b
KM
1208 gpio_set_value(GPIO_PTA2, 1);
1209 gpio_set_value(GPIO_PTU1, 1);
1210 } else {
1211 /* Panel */
ea15edb2 1212 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
44432407 1213 lcdc_info.ch[0].clock_divider = 2;
93ff2598
LP
1214 lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
1215 lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
ea15edb2 1216
ea15edb2
KM
1217 /* FIXME
1218 *
1219 * LCDDON control is needed for Panel,
1220 * but current sh_mobile_lcdc driver doesn't control it.
1221 * It is temporary correspondence
1222 */
1223 gpio_request(GPIO_PTF4, NULL);
1224 gpio_direction_output(GPIO_PTF4, 1);
8810e055
KM
1225
1226 /* enable TouchScreen */
1227 i2c_register_board_info(0, &ts_i2c_clients, 1);
fcb8918f 1228 irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
fa3ba51b
KM
1229 }
1230
2153ad32
KM
1231 /* enable CEU0 */
1232 gpio_request(GPIO_FN_VIO0_D15, NULL);
1233 gpio_request(GPIO_FN_VIO0_D14, NULL);
1234 gpio_request(GPIO_FN_VIO0_D13, NULL);
1235 gpio_request(GPIO_FN_VIO0_D12, NULL);
1236 gpio_request(GPIO_FN_VIO0_D11, NULL);
1237 gpio_request(GPIO_FN_VIO0_D10, NULL);
1238 gpio_request(GPIO_FN_VIO0_D9, NULL);
1239 gpio_request(GPIO_FN_VIO0_D8, NULL);
1240 gpio_request(GPIO_FN_VIO0_D7, NULL);
1241 gpio_request(GPIO_FN_VIO0_D6, NULL);
1242 gpio_request(GPIO_FN_VIO0_D5, NULL);
1243 gpio_request(GPIO_FN_VIO0_D4, NULL);
1244 gpio_request(GPIO_FN_VIO0_D3, NULL);
1245 gpio_request(GPIO_FN_VIO0_D2, NULL);
1246 gpio_request(GPIO_FN_VIO0_D1, NULL);
1247 gpio_request(GPIO_FN_VIO0_D0, NULL);
1248 gpio_request(GPIO_FN_VIO0_VD, NULL);
1249 gpio_request(GPIO_FN_VIO0_CLK, NULL);
1250 gpio_request(GPIO_FN_VIO0_FLD, NULL);
1251 gpio_request(GPIO_FN_VIO0_HD, NULL);
2153ad32
KM
1252
1253 /* enable CEU1 */
1254 gpio_request(GPIO_FN_VIO1_D7, NULL);
1255 gpio_request(GPIO_FN_VIO1_D6, NULL);
1256 gpio_request(GPIO_FN_VIO1_D5, NULL);
1257 gpio_request(GPIO_FN_VIO1_D4, NULL);
1258 gpio_request(GPIO_FN_VIO1_D3, NULL);
1259 gpio_request(GPIO_FN_VIO1_D2, NULL);
1260 gpio_request(GPIO_FN_VIO1_D1, NULL);
1261 gpio_request(GPIO_FN_VIO1_D0, NULL);
1262 gpio_request(GPIO_FN_VIO1_FLD, NULL);
1263 gpio_request(GPIO_FN_VIO1_HD, NULL);
1264 gpio_request(GPIO_FN_VIO1_VD, NULL);
1265 gpio_request(GPIO_FN_VIO1_CLK, NULL);
2153ad32 1266
e9103e74
KM
1267 /* enable KEYSC */
1268 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
1269 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
1270 gpio_request(GPIO_FN_KEYOUT3, NULL);
1271 gpio_request(GPIO_FN_KEYOUT2, NULL);
1272 gpio_request(GPIO_FN_KEYOUT1, NULL);
1273 gpio_request(GPIO_FN_KEYOUT0, NULL);
1274 gpio_request(GPIO_FN_KEYIN0, NULL);
1275
064a16dc
KM
1276 /* enable user debug switch */
1277 gpio_request(GPIO_PTR0, NULL);
1278 gpio_request(GPIO_PTR4, NULL);
1279 gpio_request(GPIO_PTR5, NULL);
1280 gpio_request(GPIO_PTR6, NULL);
1281 gpio_direction_input(GPIO_PTR0);
1282 gpio_direction_input(GPIO_PTR4);
1283 gpio_direction_input(GPIO_PTR5);
1284 gpio_direction_input(GPIO_PTR6);
1285
4eb80146 1286 /* SD-card slot CN11 */
5744c881 1287#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1ce4da7a 1288 /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
96987d96
KM
1289 gpio_request(GPIO_FN_SDHI0WP, NULL);
1290 gpio_request(GPIO_FN_SDHI0CMD, NULL);
1291 gpio_request(GPIO_FN_SDHI0CLK, NULL);
1292 gpio_request(GPIO_FN_SDHI0D3, NULL);
1293 gpio_request(GPIO_FN_SDHI0D2, NULL);
1294 gpio_request(GPIO_FN_SDHI0D1, NULL);
1295 gpio_request(GPIO_FN_SDHI0D0, NULL);
1ce4da7a
MD
1296#else
1297 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1298 gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
1299 gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
1300 gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
1301 gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
1302 gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
1303 gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
1304 gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
1ce4da7a 1305
5716fb9b 1306 gpiod_add_lookup_table(&mmc_spi_gpio_table);
1ce4da7a
MD
1307 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
1308#endif
96987d96 1309
4eb80146
GL
1310 /* MMC/SD-card slot CN12 */
1311#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
1312 /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
1313 gpio_request(GPIO_FN_MMC_D7, NULL);
1314 gpio_request(GPIO_FN_MMC_D6, NULL);
1315 gpio_request(GPIO_FN_MMC_D5, NULL);
1316 gpio_request(GPIO_FN_MMC_D4, NULL);
1317 gpio_request(GPIO_FN_MMC_D3, NULL);
1318 gpio_request(GPIO_FN_MMC_D2, NULL);
1319 gpio_request(GPIO_FN_MMC_D1, NULL);
1320 gpio_request(GPIO_FN_MMC_D0, NULL);
1321 gpio_request(GPIO_FN_MMC_CLK, NULL);
1322 gpio_request(GPIO_FN_MMC_CMD, NULL);
4eb80146
GL
1323
1324 cn12_enabled = true;
1325#elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1326 /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
1327 gpio_request(GPIO_FN_SDHI1WP, NULL);
1328 gpio_request(GPIO_FN_SDHI1CMD, NULL);
1329 gpio_request(GPIO_FN_SDHI1CLK, NULL);
1330 gpio_request(GPIO_FN_SDHI1D3, NULL);
1331 gpio_request(GPIO_FN_SDHI1D2, NULL);
1332 gpio_request(GPIO_FN_SDHI1D1, NULL);
1333 gpio_request(GPIO_FN_SDHI1D0, NULL);
4eb80146 1334
4eb80146
GL
1335 cn12_enabled = true;
1336#endif
1337
1338 if (cn12_enabled)
1339 /* I/O buffer drive ability is high for CN12 */
1340 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
1341 IODRIVEA);
1342
1980fdc4
KM
1343 /* enable FSI */
1344 gpio_request(GPIO_FN_FSIMCKB, NULL);
1345 gpio_request(GPIO_FN_FSIIBSD, NULL);
1346 gpio_request(GPIO_FN_FSIOBSD, NULL);
1347 gpio_request(GPIO_FN_FSIIBBCK, NULL);
1348 gpio_request(GPIO_FN_FSIIBLRCK, NULL);
1349 gpio_request(GPIO_FN_FSIOBBCK, NULL);
1350 gpio_request(GPIO_FN_FSIOBLRCK, NULL);
1351 gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
1352
16afc9fb
KM
1353 /* set SPU2 clock to 83.4 MHz */
1354 clk = clk_get(NULL, "spu_clk");
56ea5109 1355 if (!IS_ERR(clk)) {
10305853
KM
1356 clk_set_rate(clk, clk_round_rate(clk, 83333333));
1357 clk_put(clk);
1358 }
16afc9fb 1359
1980fdc4
KM
1360 /* change parent of FSI B */
1361 clk = clk_get(NULL, "fsib_clk");
56ea5109 1362 if (!IS_ERR(clk)) {
4bd5d259
KM
1363 /* 48kHz dummy clock was used to make sure 1/1 divide */
1364 clk_set_rate(&sh7724_fsimckb_clk, 48000);
1365 clk_set_parent(clk, &sh7724_fsimckb_clk);
1366 clk_set_rate(clk, 48000);
10305853
KM
1367 clk_put(clk);
1368 }
1980fdc4
KM
1369
1370 gpio_request(GPIO_PTU0, NULL);
1371 gpio_direction_output(GPIO_PTU0, 0);
1372 mdelay(20);
1373
ea440783
NH
1374 /* enable motion sensor */
1375 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
1376 gpio_direction_input(GPIO_FN_INTC_IRQ1);
1377
6f26d19f
MD
1378 /* set VPU clock to 166 MHz */
1379 clk = clk_get(NULL, "vpu_clk");
56ea5109 1380 if (!IS_ERR(clk)) {
10305853
KM
1381 clk_set_rate(clk, clk_round_rate(clk, 166000000));
1382 clk_put(clk);
1383 }
6f26d19f 1384
26365716
KM
1385 /* enable IrDA */
1386 gpio_request(GPIO_FN_IRDA_OUT, NULL);
1387 gpio_request(GPIO_FN_IRDA_IN, NULL);
1388 gpio_request(GPIO_PTU5, NULL);
1389 gpio_direction_output(GPIO_PTU5, 0);
1390
c2f9b05f
JM
1391 /* Register gpio lookup tables for cameras and video decoder */
1392 gpiod_add_lookup_table(&tw9910_gpios);
1393 gpiod_add_lookup_table(&mt9t112_0_gpios);
1394 gpiod_add_lookup_table(&mt9t112_1_gpios);
1395
125ecce6 1396 /* enable I2C device */
1980fdc4
KM
1397 i2c_register_board_info(0, i2c0_devices,
1398 ARRAY_SIZE(i2c0_devices));
1399
125ecce6
KM
1400 i2c_register_board_info(1, i2c1_devices,
1401 ARRAY_SIZE(i2c1_devices));
1402
92359a70 1403#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
aee5ab0b
GL
1404 /* VOU */
1405 gpio_request(GPIO_FN_DV_D15, NULL);
1406 gpio_request(GPIO_FN_DV_D14, NULL);
1407 gpio_request(GPIO_FN_DV_D13, NULL);
1408 gpio_request(GPIO_FN_DV_D12, NULL);
1409 gpio_request(GPIO_FN_DV_D11, NULL);
1410 gpio_request(GPIO_FN_DV_D10, NULL);
1411 gpio_request(GPIO_FN_DV_D9, NULL);
1412 gpio_request(GPIO_FN_DV_D8, NULL);
1413 gpio_request(GPIO_FN_DV_CLKI, NULL);
1414 gpio_request(GPIO_FN_DV_CLK, NULL);
1415 gpio_request(GPIO_FN_DV_VSYNC, NULL);
1416 gpio_request(GPIO_FN_DV_HSYNC, NULL);
1417
1418 /* AK8813 power / reset sequence */
1419 gpio_request(GPIO_PTG4, NULL);
1420 gpio_request(GPIO_PTU3, NULL);
1421 /* Reset */
1422 gpio_direction_output(GPIO_PTG4, 0);
1423 /* Power down */
1424 gpio_direction_output(GPIO_PTU3, 1);
1425
1426 udelay(10);
1427
1428 /* Power up, reset */
1429 gpio_set_value(GPIO_PTU3, 0);
1430
1431 udelay(10);
1432
1433 /* Remove reset */
1434 gpio_set_value(GPIO_PTG4, 1);
92359a70 1435#endif
aee5ab0b 1436
c2f9b05f
JM
1437 /* Initialize CEU platform devices separately to map memory first */
1438 device_initialize(&ecovec_ceu_devices[0]->dev);
1439 arch_setup_pdev_archdata(ecovec_ceu_devices[0]);
1440 dma_declare_coherent_memory(&ecovec_ceu_devices[0]->dev,
1441 ceu0_dma_membase, ceu0_dma_membase,
1442 ceu0_dma_membase +
1443 CEU_BUFFER_MEMORY_SIZE - 1,
1444 DMA_MEMORY_EXCLUSIVE);
1445 platform_device_add(ecovec_ceu_devices[0]);
1446
1447 device_initialize(&ecovec_ceu_devices[1]->dev);
1448 arch_setup_pdev_archdata(ecovec_ceu_devices[1]);
1449 dma_declare_coherent_memory(&ecovec_ceu_devices[1]->dev,
1450 ceu1_dma_membase, ceu1_dma_membase,
1451 ceu1_dma_membase +
1452 CEU_BUFFER_MEMORY_SIZE - 1,
1453 DMA_MEMORY_EXCLUSIVE);
1454 platform_device_add(ecovec_ceu_devices[1]);
1455
efdfeb07
LW
1456 gpiod_add_lookup_table(&cn12_power_gpiod_table);
1457#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
1458 gpiod_add_lookup_table(&sdhi0_power_gpiod_table);
faed9303 1459 gpiod_add_lookup_table(&sdhi0_gpio_table);
faed9303
LW
1460#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1461 gpiod_add_lookup_table(&sdhi1_gpio_table);
c4916c24 1462#endif
efdfeb07
LW
1463#endif
1464
4138b740
KM
1465 return platform_add_devices(ecovec_devices,
1466 ARRAY_SIZE(ecovec_devices));
1467}
4907d57f
KM
1468arch_initcall(arch_setup);
1469
1470static int __init devices_setup(void)
1471{
376abbb4 1472 sh_eth_init(&sh_eth_plat);
4907d57f
KM
1473 return 0;
1474}
1475device_initcall(devices_setup);
1476
c2f9b05f
JM
1477/* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
1478static void __init ecovec_mv_mem_reserve(void)
1479{
1480 phys_addr_t phys;
1481 phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
1482
1483 phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
1484 memblock_free(phys, size);
1485 memblock_remove(phys, size);
1486 ceu0_dma_membase = phys;
1487
1488 phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
1489 memblock_free(phys, size);
1490 memblock_remove(phys, size);
1491 ceu1_dma_membase = phys;
1492}
1493
4138b740
KM
1494static struct sh_machine_vector mv_ecovec __initmv = {
1495 .mv_name = "R0P7724 (EcoVec)",
c2f9b05f 1496 .mv_mem_reserve = ecovec_mv_mem_reserve,
4138b740 1497};