[mirror_ubuntu-jammy-kernel.git] / arch / sh / boards / mach-hp6xx / pm.c

// SPDX-License-Identifier: GPL-2.0
/*
 * hp6x0 Power Management Routines
 *
 * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
 */
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <asm/io.h>
#include <asm/hd64461.h>
#include <asm/bl_bit.h>
#include <mach/hp6xx.h>
#include <cpu/dac.h>
#include <asm/freq.h>
#include <asm/watchdog.h>

#define INTR_OFFSET	0x600

#define STBCR		0xffffff82
#define STBCR2		0xffffff88

#define STBCR_STBY	0x80
#define STBCR_MSTP2	0x04

#define MCR		0xffffff68
#define RTCNT		0xffffff70

#define MCR_RMODE	2
#define MCR_RFSH	4

extern u8 wakeup_start;
extern u8 wakeup_end;

static void pm_enter(void)
{
	u8 stbcr, csr;
	u16 frqcr, mcr;
	u32 vbr_new, vbr_old;

	set_bl_bit();

	/* set wdt */
	csr = sh_wdt_read_csr();
	csr &= ~WTCSR_TME;
	csr |= WTCSR_CKS_4096;
	sh_wdt_write_csr(csr);
	csr = sh_wdt_read_csr();
	sh_wdt_write_cnt(0);

	/* disable PLL1 */
	frqcr = __raw_readw(FRQCR);
	frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
	__raw_writew(frqcr, FRQCR);

	/* enable standby */
	stbcr = __raw_readb(STBCR);
	__raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);

	/* set self-refresh */
	mcr = __raw_readw(MCR);
	__raw_writew(mcr & ~MCR_RFSH, MCR);

	/* set interrupt handler */
	asm volatile("stc vbr, %0" : "=r" (vbr_old));
	vbr_new = get_zeroed_page(GFP_ATOMIC);
	udelay(50);
	memcpy((void*)(vbr_new + INTR_OFFSET),
	       &wakeup_start, &wakeup_end - &wakeup_start);
	asm volatile("ldc %0, vbr" : : "r" (vbr_new));

	__raw_writew(0, RTCNT);
	__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);

	cpu_sleep();

	asm volatile("ldc %0, vbr" : : "r" (vbr_old));

	free_page(vbr_new);

	/* enable PLL1 */
	frqcr = __raw_readw(FRQCR);
	frqcr |= FRQCR_PSTBY;
	__raw_writew(frqcr, FRQCR);
	udelay(50);
	frqcr |= FRQCR_PLLEN;
	__raw_writew(frqcr, FRQCR);

	__raw_writeb(stbcr, STBCR);

	clear_bl_bit();
}

static int hp6x0_pm_enter(suspend_state_t state)
{
	u8 stbcr, stbcr2;
#ifdef CONFIG_HD64461_ENABLER
	u8 scr;
	u16 hd64461_stbcr;
#endif

#ifdef CONFIG_HD64461_ENABLER
	outb(0, HD64461_PCC1CSCIER);

	scr = inb(HD64461_PCC1SCR);
	scr |= HD64461_PCCSCR_VCC1;
	outb(scr, HD64461_PCC1SCR);

	hd64461_stbcr = inw(HD64461_STBCR);
	hd64461_stbcr |= HD64461_STBCR_SPC1ST;
	outw(hd64461_stbcr, HD64461_STBCR);
#endif

	__raw_writeb(0x1f, DACR);

	stbcr = __raw_readb(STBCR);
	__raw_writeb(0x01, STBCR);

	stbcr2 = __raw_readb(STBCR2);
	__raw_writeb(0x7f , STBCR2);

	outw(0xf07f, HD64461_SCPUCR);

	pm_enter();

	outw(0, HD64461_SCPUCR);
	__raw_writeb(stbcr, STBCR);
	__raw_writeb(stbcr2, STBCR2);

#ifdef CONFIG_HD64461_ENABLER
	hd64461_stbcr = inw(HD64461_STBCR);
	hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
	outw(hd64461_stbcr, HD64461_STBCR);

	outb(0x4c, HD64461_PCC1CSCIER);
	outb(0x00, HD64461_PCC1CSCR);
#endif

	return 0;
}

static const struct platform_suspend_ops hp6x0_pm_ops = {
	.enter		= hp6x0_pm_enter,
	.valid		= suspend_valid_only_mem,
};

static int __init hp6x0_pm_init(void)
{
	suspend_set_ops(&hp6x0_pm_ops);
	return 0;
}

late_initcall(hp6x0_pm_init);
Commit	Line	Data
aaf9128a	1	// SPDX-License-Identifier: GPL-2.0
3aa770e7 AS	2	/*
	3	* hp6x0 Power Management Routines
	4	*
	5	* Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
3aa770e7	6	*/
3aa770e7 AS	7	#include <linux/init.h>
	8	#include <linux/suspend.h>
	9	#include <linux/errno.h>
	10	#include <linux/time.h>
3e517627 MD	11	#include <linux/delay.h>
3e517627 MD	12	#include <linux/gfp.h>
3aa770e7 AS	13	#include <asm/io.h>
3aa770e7 AS	14	#include <asm/hd64461.h>
f03c4866	15	#include <asm/bl_bit.h>
7639a454	16	#include <mach/hp6xx.h>
f15cbe6f	17	#include <cpu/dac.h>
3e517627 MD	18	#include <asm/freq.h>
	19	#include <asm/watchdog.h>
	20
	21	#define INTR_OFFSET 0x600
3aa770e7 AS	22
	23	#define STBCR 0xffffff82
	24	#define STBCR2 0xffffff88
	25
3e517627 MD	26	#define STBCR_STBY 0x80
	27	#define STBCR_MSTP2 0x04
	28
	29	#define MCR 0xffffff68
	30	#define RTCNT 0xffffff70
	31
	32	#define MCR_RMODE 2
	33	#define MCR_RFSH 4
	34
	35	extern u8 wakeup_start;
	36	extern u8 wakeup_end;
	37
	38	static void pm_enter(void)
	39	{
	40	u8 stbcr, csr;
	41	u16 frqcr, mcr;
	42	u32 vbr_new, vbr_old;
	43
	44	set_bl_bit();
	45
	46	/* set wdt */
	47	csr = sh_wdt_read_csr();
	48	csr &= ~WTCSR_TME;
	49	csr \|= WTCSR_CKS_4096;
	50	sh_wdt_write_csr(csr);
	51	csr = sh_wdt_read_csr();
	52	sh_wdt_write_cnt(0);
	53
	54	/* disable PLL1 */
9d56dd3b	55	frqcr = __raw_readw(FRQCR);
3e517627	56	frqcr &= ~(FRQCR_PLLEN \| FRQCR_PSTBY);
9d56dd3b	57	__raw_writew(frqcr, FRQCR);
3e517627 MD	58
3e517627 MD	59	/* enable standby */
9d56dd3b PM	60	stbcr = __raw_readb(STBCR);
9d56dd3b PM	61	__raw_writeb(stbcr \| STBCR_STBY \| STBCR_MSTP2, STBCR);
3e517627 MD	62
3e517627 MD	63	/* set self-refresh */
9d56dd3b PM	64	mcr = __raw_readw(MCR);
9d56dd3b PM	65	__raw_writew(mcr & ~MCR_RFSH, MCR);
3e517627 MD	66
	67	/* set interrupt handler */
	68	asm volatile("stc vbr, %0" : "=r" (vbr_old));
	69	vbr_new = get_zeroed_page(GFP_ATOMIC);
	70	udelay(50);
	71	memcpy((void*)(vbr_new + INTR_OFFSET),
	72	&wakeup_start, &wakeup_end - &wakeup_start);
	73	asm volatile("ldc %0, vbr" : : "r" (vbr_new));
	74
9d56dd3b PM	75	__raw_writew(0, RTCNT);
9d56dd3b PM	76	__raw_writew(mcr \| MCR_RFSH \| MCR_RMODE, MCR);
3e517627 MD	77
	78	cpu_sleep();
	79
	80	asm volatile("ldc %0, vbr" : : "r" (vbr_old));
	81
	82	free_page(vbr_new);
	83
	84	/* enable PLL1 */
9d56dd3b	85	frqcr = __raw_readw(FRQCR);
3e517627	86	frqcr \|= FRQCR_PSTBY;
9d56dd3b	87	__raw_writew(frqcr, FRQCR);
3e517627 MD	88	udelay(50);
3e517627 MD	89	frqcr \|= FRQCR_PLLEN;
9d56dd3b	90	__raw_writew(frqcr, FRQCR);
3e517627	91
9d56dd3b	92	__raw_writeb(stbcr, STBCR);
3e517627 MD	93
	94	clear_bl_bit();
	95	}
	96
3aa770e7 AS	97	static int hp6x0_pm_enter(suspend_state_t state)
	98	{
	99	u8 stbcr, stbcr2;
	100	#ifdef CONFIG_HD64461_ENABLER
	101	u8 scr;
	102	u16 hd64461_stbcr;
	103	#endif
	104
3aa770e7 AS	105	#ifdef CONFIG_HD64461_ENABLER
	106	outb(0, HD64461_PCC1CSCIER);
	107
	108	scr = inb(HD64461_PCC1SCR);
	109	scr \|= HD64461_PCCSCR_VCC1;
	110	outb(scr, HD64461_PCC1SCR);
	111
	112	hd64461_stbcr = inw(HD64461_STBCR);
	113	hd64461_stbcr \|= HD64461_STBCR_SPC1ST;
	114	outw(hd64461_stbcr, HD64461_STBCR);
	115	#endif
	116
9d56dd3b	117	__raw_writeb(0x1f, DACR);
3aa770e7	118
9d56dd3b PM	119	stbcr = __raw_readb(STBCR);
9d56dd3b PM	120	__raw_writeb(0x01, STBCR);
3aa770e7	121
9d56dd3b PM	122	stbcr2 = __raw_readb(STBCR2);
9d56dd3b PM	123	__raw_writeb(0x7f , STBCR2);
3aa770e7 AS	124
	125	outw(0xf07f, HD64461_SCPUCR);
	126
	127	pm_enter();
	128
	129	outw(0, HD64461_SCPUCR);
9d56dd3b PM	130	__raw_writeb(stbcr, STBCR);
9d56dd3b PM	131	__raw_writeb(stbcr2, STBCR2);
3aa770e7 AS	132
	133	#ifdef CONFIG_HD64461_ENABLER
	134	hd64461_stbcr = inw(HD64461_STBCR);
	135	hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
	136	outw(hd64461_stbcr, HD64461_STBCR);
	137
	138	outb(0x4c, HD64461_PCC1CSCIER);
	139	outb(0x00, HD64461_PCC1CSCR);
	140	#endif
	141
	142	return 0;
	143	}
	144
2f55ac07	145	static const struct platform_suspend_ops hp6x0_pm_ops = {
3aa770e7	146	.enter = hp6x0_pm_enter,
26398a70	147	.valid = suspend_valid_only_mem,
3aa770e7 AS	148	};
	149
	150	static int __init hp6x0_pm_init(void)
	151	{
26398a70	152	suspend_set_ops(&hp6x0_pm_ops);
3aa770e7 AS	153	return 0;
	154	}
	155
	156	late_initcall(hp6x0_pm_init);