[mirror_ubuntu-focal-kernel.git] / arch / sh / boards / mach-migor / setup.c

/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/rawnand.h>
#include <linux/i2c.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <video/sh_mobile_lcdc.h>
#include <media/drv-intf/sh_mobile_ceu.h>
#include <media/i2c/ov772x.h>
#include <media/soc_camera.h>
#include <media/i2c/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x600), /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xbe0),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd_to_nand(mtd);

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->IO_ADDR_W);
}

static int migor_nand_flash_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

static struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

static const struct fb_videomode migor_lcd_modes[] = {
	{
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
		.name = "LB070WV1",
		.xres = 800,
		.yres = 480,
		.left_margin = 64,
		.right_margin = 16,
		.hsync_len = 120,
		.sync = 0,
#elif defined(CONFIG_SH_MIGOR_QVGA)
		.name = "PH240320T",
		.xres = 320,
		.yres = 240,
		.left_margin = 0,
		.right_margin = 16,
		.hsync_len = 8,
		.sync = FB_SYNC_HOR_HIGH_ACT,
#endif
		.upper_margin = 1,
		.lower_margin = 17,
		.vsync_len = 2,
	},
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_modes = migor_lcd_modes,
		.num_modes = ARRAY_SIZE(migor_lcd_modes),
		.panel_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#elif defined(CONFIG_SH_MIGOR_QVGA)
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_modes = migor_lcd_modes,
		.num_modes = ARRAY_SIZE(migor_lcd_modes),
		.panel_cfg = {
			.width = 49,	/* 2.4 inch */
			.height = 37,
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe942fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x580),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
};

static struct clk *camera_clk;
static DEFINE_MUTEX(camera_lock);

static void camera_power_on(int is_tw)
{
	mutex_lock(&camera_lock);

	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	 * around signal quality issues on Panel Board V2.1.
	 */
	camera_clk = clk_get(NULL, "video_clk");
	clk_set_rate(camera_clk, 10000000);
	clk_enable(camera_clk);	/* start VIO_CKO */

	/* use VIO_RST to take camera out of reset */
	mdelay(10);
	if (is_tw) {
		gpio_set_value(GPIO_PTT2, 0);
		gpio_set_value(GPIO_PTT0, 0);
	} else {
		gpio_set_value(GPIO_PTT0, 1);
	}
	gpio_set_value(GPIO_PTT3, 0);
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 1);
	mdelay(10); /* wait to let chip come out of reset */
}

static void camera_power_off(void)
{
	clk_disable(camera_clk); /* stop VIO_CKO */
	clk_put(camera_clk);

	gpio_set_value(GPIO_PTT3, 0);
	mutex_unlock(&camera_lock);
}

static int ov7725_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(0);
	else
		camera_power_off();

	return 0;
}

static int tw9910_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(1);
	else
		camera_power_off();

	return 0;
}

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x880),
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &sh_mobile_ceu_info,
	},
};

/* Fixed 3.3V regulator to be used by SDHI0 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};

static struct resource sdhi_cn9_resources[] = {
	[0] = {
		.name	= "SDHI",
		.start	= 0x04ce0000,
		.end	= 0x04ce00ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0xe80),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct tmio_mmc_data sh7724_sdhi_data = {
	.chan_priv_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
	.chan_priv_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
	.capabilities	= MMC_CAP_SDIO_IRQ,
};

static struct platform_device sdhi_cn9_device = {
	.name		= "sh_mobile_sdhi",
	.num_resources	= ARRAY_SIZE(sdhi_cn9_resources),
	.resource	= sdhi_cn9_resources,
	.dev = {
		.platform_data	= &sh7724_sdhi_data,
	},
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = evt2irq(0x6c0), /* IRQ6 */
	},
	{
		I2C_BOARD_INFO("wm8978", 0x1a),
	},
};

static struct i2c_board_info migor_i2c_camera[] = {
	{
		I2C_BOARD_INFO("ov772x", 0x21),
	},
	{
		I2C_BOARD_INFO("tw9910", 0x45),
	},
};

static struct ov772x_camera_info ov7725_info;

static struct soc_camera_link ov7725_link = {
	.power		= ov7725_power,
	.board_info	= &migor_i2c_camera[0],
	.i2c_adapter_id	= 0,
	.priv		= &ov7725_info,
};

static struct tw9910_video_info tw9910_info = {
	.buswidth	= SOCAM_DATAWIDTH_8,
	.mpout		= TW9910_MPO_FIELD,
};

static struct soc_camera_link tw9910_link = {
	.power		= tw9910_power,
	.board_info	= &migor_i2c_camera[1],
	.i2c_adapter_id	= 0,
	.priv		= &tw9910_info,
};

static struct platform_device migor_camera[] = {
	{
		.name	= "soc-camera-pdrv",
		.id	= 0,
		.dev	= {
			.platform_data = &ov7725_link,
		},
	}, {
		.name	= "soc-camera-pdrv",
		.id	= 1,
		.dev	= {
			.platform_data = &tw9910_link,
		},
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_ceu_device,
	&migor_nor_flash_device,
	&migor_nand_flash_device,
	&sdhi_cn9_device,
	&migor_camera[0],
	&migor_camera[1],
};

extern char migor_sdram_enter_start;
extern char migor_sdram_enter_end;
extern char migor_sdram_leave_start;
extern char migor_sdram_leave_end;

static int __init migor_devices_setup(void)
{
	/* register board specific self-refresh code */
	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
					&migor_sdram_enter_start,
					&migor_sdram_enter_end,
					&migor_sdram_leave_start,
					&migor_sdram_leave_end);

	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);

	/* Let D11 LED show STATUS0 */
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* Lit D12 LED show PDSTATUS */
	gpio_request(GPIO_FN_PDSTATUS, NULL);

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	__raw_writel(0x00003400, BSC_CS4BCR);
	__raw_writel(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* SDHI */
	gpio_request(GPIO_FN_SDHICD, NULL);
	gpio_request(GPIO_FN_SDHIWP, NULL);
	gpio_request(GPIO_FN_SDHID3, NULL);
	gpio_request(GPIO_FN_SDHID2, NULL);
	gpio_request(GPIO_FN_SDHID1, NULL);
	gpio_request(GPIO_FN_SDHID0, NULL);
	gpio_request(GPIO_FN_SDHICMD, NULL);
	gpio_request(GPIO_FN_SDHICLK, NULL);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	gpio_direction_output(GPIO_PTT3, 0);
	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	gpio_direction_output(GPIO_PTT2, 1);
	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	gpio_direction_output(GPIO_PTT0, 0);
#else
	gpio_direction_output(GPIO_PTT0, 1);
#endif
	__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

	/* SIU: Port B */
	gpio_request(GPIO_FN_SIUBOLR, NULL);
	gpio_request(GPIO_FN_SIUBOBT, NULL);
	gpio_request(GPIO_FN_SIUBISLD, NULL);
	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	gpio_request(GPIO_FN_SIUMCKB, NULL);

	/*
	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	 * output. Need only SIUB, set to output for master mode (table 34.2)
	 */
	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
arch_initcall(migor_devices_setup);

/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=0: Test Mode Disabled
	 */
	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_migor __initmv = {
	.mv_name		= "Migo-R",
	.mv_mode_pins		= migor_mode_pins,
};
Commit	Line	Data
70f784ec MD	1	/*
	2	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
92cfeb61	13	#include <linux/input.h>
fc1d003d	14	#include <linux/input/sh_keysc.h>
464495e5	15	#include <linux/mmc/host.h>
b8808786	16	#include <linux/mtd/physmap.h>
84f11d5b	17	#include <linux/mfd/tmio.h>
d4092d76	18	#include <linux/mtd/rawnand.h>
0c6111ec	19	#include <linux/i2c.h>
48aff643 GL	20	#include <linux/regulator/fixed.h>
48aff643 GL	21	#include <linux/regulator/machine.h>
8a3ee0fc	22	#include <linux/smc91x.h>
1765534c MD	23	#include <linux/delay.h>
1765534c MD	24	#include <linux/clk.h>
91b6f3c5	25	#include <linux/gpio.h>
a1ad8033	26	#include <linux/videodev2.h>
26819fcb	27	#include <linux/sh_intc.h>
70e5c4f0	28	#include <video/sh_mobile_lcdc.h>
d647f0b7	29	#include <media/drv-intf/sh_mobile_ceu.h>
b5dcee22	30	#include <media/i2c/ov772x.h>
a1ad8033	31	#include <media/soc_camera.h>
b5dcee22	32	#include <media/i2c/tw9910.h>
6c7d826c	33	#include <asm/clock.h>
70f784ec MD	34	#include <asm/machvec.h>
70f784ec MD	35	#include <asm/io.h>
13fa551b	36	#include <asm/suspend.h>
7639a454	37	#include <mach/migor.h>
f7275650	38	#include <cpu/sh7722.h>
70f784ec MD	39
	40	/* Address IRQ Size Bus Description
	41	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	42	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	43	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	44	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	45	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	46	*/
	47
8a3ee0fc	48	static struct smc91x_platdata smc91x_info = {
a30c89ad	49	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	50	};
8a3ee0fc MD	51
70f784ec MD	52	static struct resource smc91x_eth_resources[] = {
70f784ec MD	53	[0] = {
b026a23c MD	54	.name = "SMC91C111" ,
	55	.start = 0x10000300,
	56	.end = 0x1000030f,
70f784ec MD	57	.flags = IORESOURCE_MEM,
	58	},
	59	[1] = {
26819fcb	60	.start = evt2irq(0x600), /* IRQ0 */
d280eadc	61	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	62	},
	63	};
	64
	65	static struct platform_device smc91x_eth_device = {
	66	.name = "smc91x",
	67	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	68	.resource = smc91x_eth_resources,
8a3ee0fc MD	69	.dev = {
	70	.platform_data = &smc91x_info,
	71	},
70f784ec MD	72	};
70f784ec MD	73
92cfeb61 MD	74	static struct sh_keysc_info sh_keysc_info = {
	75	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	76	.scan_timing = 3,
	77	.delay = 5,
	78	.keycodes = {
	79	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	80	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	81	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	82	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	83	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	84	},
	85	};
	86
	87	static struct resource sh_keysc_resources[] = {
	88	[0] = {
	89	.start = 0x044b0000,
	90	.end = 0x044b000f,
	91	.flags = IORESOURCE_MEM,
	92	},
	93	[1] = {
26819fcb	94	.start = evt2irq(0xbe0),
92cfeb61 MD	95	.flags = IORESOURCE_IRQ,
	96	},
	97	};
	98
	99	static struct platform_device sh_keysc_device = {
	100	.name = "sh_keysc",
090d951b	101	.id = 0, /* "keysc0" clock */
92cfeb61 MD	102	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	103	.resource = sh_keysc_resources,
	104	.dev = {
	105	.platform_data = &sh_keysc_info,
	106	},
	107	};
	108
b8808786 MD	109	static struct mtd_partition migor_nor_flash_partitions[] =
	110	{
	111	{
	112	.name = "uboot",
	113	.offset = 0,
	114	.size = (1 * 1024 * 1024),
	115	.mask_flags = MTD_WRITEABLE, /* Read-only */
	116	},
	117	{
	118	.name = "rootfs",
	119	.offset = MTDPART_OFS_APPEND,
	120	.size = (15 * 1024 * 1024),
	121	},
	122	{
	123	.name = "other",
	124	.offset = MTDPART_OFS_APPEND,
	125	.size = MTDPART_SIZ_FULL,
	126	},
	127	};
	128
	129	static struct physmap_flash_data migor_nor_flash_data = {
	130	.width = 2,
	131	.parts = migor_nor_flash_partitions,
	132	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	133	};
	134
	135	static struct resource migor_nor_flash_resources[] = {
	136	[0] = {
	137	.name = "NOR Flash",
	138	.start = 0x00000000,
	139	.end = 0x03ffffff,
	140	.flags = IORESOURCE_MEM,
	141	}
	142	};
	143
	144	static struct platform_device migor_nor_flash_device = {
	145	.name = "physmap-flash",
	146	.resource = migor_nor_flash_resources,
	147	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	148	.dev = {
	149	.platform_data = &migor_nor_flash_data,
	150	},
	151	};
	152
3c803a9a MD	153	static struct mtd_partition migor_nand_flash_partitions[] = {
	154	{
	155	.name = "nanddata1",
	156	.offset = 0x0,
	157	.size = 512 * 1024 * 1024,
	158	},
	159	{
	160	.name = "nanddata2",
	161	.offset = MTDPART_OFS_APPEND,
	162	.size = 512 * 1024 * 1024,
	163	},
	164	};
	165
	166	static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
	167	unsigned int ctrl)
	168	{
7326ffef	169	struct nand_chip *chip = mtd_to_nand(mtd);
3c803a9a MD	170
	171	if (cmd == NAND_CMD_NONE)
	172	return;
	173
	174	if (ctrl & NAND_CLE)
	175	writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	176	else if (ctrl & NAND_ALE)
	177	writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	178	else
	179	writeb(cmd, chip->IO_ADDR_W);
	180	}
	181
	182	static int migor_nand_flash_ready(struct mtd_info *mtd)
	183	{
91b6f3c5	184	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	185	}
3c803a9a MD	186
30e0cc1a	187	static struct platform_nand_data migor_nand_flash_data = {
3c803a9a MD	188	.chip = {
	189	.nr_chips = 1,
	190	.partitions = migor_nand_flash_partitions,
	191	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	192	.chip_delay = 20,
3c803a9a MD	193	},
	194	.ctrl = {
	195	.dev_ready = migor_nand_flash_ready,
	196	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	197	},
	198	};
	199
	200	static struct resource migor_nand_flash_resources[] = {
	201	[0] = {
	202	.name = "NAND Flash",
	203	.start = 0x18000000,
	204	.end = 0x18ffffff,
	205	.flags = IORESOURCE_MEM,
	206	},
	207	};
	208
	209	static struct platform_device migor_nand_flash_device = {
	210	.name = "gen_nand",
	211	.resource = migor_nand_flash_resources,
	212	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	213	.dev = {
	214	.platform_data = &migor_nand_flash_data,
	215	}
	216	};
	217
e04008eb	218	static const struct fb_videomode migor_lcd_modes[] = {
44432407 GL	219	{
	220	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	221	.name = "LB070WV1",
	222	.xres = 800,
	223	.yres = 480,
	224	.left_margin = 64,
	225	.right_margin = 16,
	226	.hsync_len = 120,
	227	.sync = 0,
	228	#elif defined(CONFIG_SH_MIGOR_QVGA)
	229	.name = "PH240320T",
	230	.xres = 320,
	231	.yres = 240,
	232	.left_margin = 0,
	233	.right_margin = 16,
	234	.hsync_len = 8,
	235	.sync = FB_SYNC_HOR_HIGH_ACT,
	236	#endif
	237	.upper_margin = 1,
	238	.lower_margin = 17,
	239	.vsync_len = 2,
	240	},
	241	};
	242
8b1285f1	243	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
44432407	244	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
8b1285f1 MD	245	.clock_source = LCDC_CLK_BUS,
	246	.ch[0] = {
	247	.chan = LCDC_CHAN_MAINLCD,
edd153a3	248	.fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1 MD	249	.interface_type = RGB16,
8b1285f1 MD	250	.clock_divider = 2,
93ff2598 LP	251	.lcd_modes = migor_lcd_modes,
93ff2598 LP	252	.num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b	253	.panel_cfg = { /* 7.0 inch */
ce9c008c MD	254	.width = 152,
	255	.height = 91,
	256	},
8b1285f1	257	}
44432407	258	#elif defined(CONFIG_SH_MIGOR_QVGA)
8b1285f1 MD	259	.clock_source = LCDC_CLK_PERIPHERAL,
	260	.ch[0] = {
	261	.chan = LCDC_CHAN_MAINLCD,
edd153a3	262	.fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1 MD	263	.interface_type = SYS16A,
8b1285f1 MD	264	.clock_divider = 10,
93ff2598 LP	265	.lcd_modes = migor_lcd_modes,
93ff2598 LP	266	.num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b LP	267	.panel_cfg = {
afaad83b LP	268	.width = 49, /* 2.4 inch */
ce9c008c	269	.height = 37,
8b1285f1 MD	270	.setup_sys = migor_lcd_qvga_setup,
	271	},
	272	.sys_bus_cfg = {
	273	.ldmt2r = 0x06000a09,
	274	.ldmt3r = 0x180e3418,
b5868e8c MD	275	/* set 1s delay to encourage fsync() */
b5868e8c MD	276	.deferred_io_msec = 1000,
8b1285f1 MD	277	},
	278	}
	279	#endif
	280	};
	281
	282	static struct resource migor_lcdc_resources[] = {
	283	[0] = {
	284	.name = "LCDC",
	285	.start = 0xfe940000, /* P4-only space */
a6f15ade	286	.end = 0xfe942fff,
8b1285f1 MD	287	.flags = IORESOURCE_MEM,
8b1285f1 MD	288	},
07905554	289	[1] = {
26819fcb	290	.start = evt2irq(0x580),
07905554 MD	291	.flags = IORESOURCE_IRQ,
07905554 MD	292	},
8b1285f1 MD	293	};
	294
	295	static struct platform_device migor_lcdc_device = {
	296	.name = "sh_mobile_lcdc_fb",
	297	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	298	.resource = migor_lcdc_resources,
	299	.dev = {
	300	.platform_data = &sh_mobile_lcdc_info,
	301	},
	302	};
	303
1765534c	304	static struct clk *camera_clk;
deae7b86	305	static DEFINE_MUTEX(camera_lock);
1765534c	306
deae7b86	307	static void camera_power_on(int is_tw)
1765534c	308	{
deae7b86 KM	309	mutex_lock(&camera_lock);
deae7b86 KM	310
22ee3ba6 MD	311	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	312	* around signal quality issues on Panel Board V2.1.
	313	*/
1765534c	314	camera_clk = clk_get(NULL, "video_clk");
22ee3ba6	315	clk_set_rate(camera_clk, 10000000);
1765534c MD	316	clk_enable(camera_clk); /* start VIO_CKO */
1765534c MD	317
91b6f3c5	318	/* use VIO_RST to take camera out of reset */
1765534c	319	mdelay(10);
deae7b86 KM	320	if (is_tw) {
	321	gpio_set_value(GPIO_PTT2, 0);
	322	gpio_set_value(GPIO_PTT0, 0);
	323	} else {
	324	gpio_set_value(GPIO_PTT0, 1);
	325	}
91b6f3c5	326	gpio_set_value(GPIO_PTT3, 0);
1765534c	327	mdelay(10);
91b6f3c5	328	gpio_set_value(GPIO_PTT3, 1);
4545bfa0	329	mdelay(10); /* wait to let chip come out of reset */
1765534c MD	330	}
	331
	332	static void camera_power_off(void)
	333	{
	334	clk_disable(camera_clk); /* stop VIO_CKO */
	335	clk_put(camera_clk);
	336
91b6f3c5	337	gpio_set_value(GPIO_PTT3, 0);
deae7b86	338	mutex_unlock(&camera_lock);
1765534c MD	339	}
1765534c MD	340
ff04ea40 KM	341	static int ov7725_power(struct device *dev, int mode)
	342	{
	343	if (mode)
deae7b86 KM	344	camera_power_on(0);
	345	else
	346	camera_power_off();
	347
	348	return 0;
	349	}
	350
	351	static int tw9910_power(struct device *dev, int mode)
	352	{
	353	if (mode)
	354	camera_power_on(1);
ff04ea40 KM	355	else
	356	camera_power_off();
	357
	358	return 0;
	359	}
	360
1765534c	361	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
64935056	362	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
1765534c MD	363	};
	364
	365	static struct resource migor_ceu_resources[] = {
	366	[0] = {
	367	.name = "CEU",
	368	.start = 0xfe910000,
	369	.end = 0xfe91009f,
	370	.flags = IORESOURCE_MEM,
	371	},
	372	[1] = {
26819fcb	373	.start = evt2irq(0x880),
1765534c MD	374	.flags = IORESOURCE_IRQ,
	375	},
	376	[2] = {
	377	/* place holder for contiguous memory */
	378	},
	379	};
	380
	381	static struct platform_device migor_ceu_device = {
	382	.name = "sh_mobile_ceu",
a42b6dd6	383	.id = 0, /* "ceu0" clock */
1765534c MD	384	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	385	.resource = migor_ceu_resources,
	386	.dev = {
	387	.platform_data = &sh_mobile_ceu_info,
	388	},
	389	};
	390
48aff643 GL	391	/* Fixed 3.3V regulator to be used by SDHI0 */
	392	static struct regulator_consumer_supply fixed3v3_power_consumers[] =
	393	{
	394	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	395	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
	396	};
	397
2e3fc56c MD	398	static struct resource sdhi_cn9_resources[] = {
	399	[0] = {
	400	.name = "SDHI",
	401	.start = 0x04ce0000,
d80e9221	402	.end = 0x04ce00ff,
2e3fc56c MD	403	.flags = IORESOURCE_MEM,
	404	},
	405	[1] = {
26819fcb	406	.start = evt2irq(0xe80),
2e3fc56c MD	407	.flags = IORESOURCE_IRQ,
2e3fc56c MD	408	},
70e5c4f0 MD	409	};
70e5c4f0 MD	410
84f11d5b KM	411	static struct tmio_mmc_data sh7724_sdhi_data = {
	412	.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
	413	.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
	414	.capabilities = MMC_CAP_SDIO_IRQ,
65a1b034 GL	415	};
65a1b034 GL	416
2e3fc56c MD	417	static struct platform_device sdhi_cn9_device = {
	418	.name = "sh_mobile_sdhi",
	419	.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
	420	.resource = sdhi_cn9_resources,
65a1b034 GL	421	.dev = {
	422	.platform_data = &sh7724_sdhi_data,
	423	},
70e5c4f0 MD	424	};
70e5c4f0 MD	425
1765534c	426	static struct i2c_board_info migor_i2c_devices[] = {
57795867	427	{
3760f736	428	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	429	},
67908abf MD	430	{
67908abf MD	431	I2C_BOARD_INFO("migor_ts", 0x51),
26819fcb	432	.irq = evt2irq(0x6c0), /* IRQ6 */
67908abf	433	},
920925f9 GL	434	{
	435	I2C_BOARD_INFO("wm8978", 0x1a),
	436	},
2cb582ca GL	437	};
	438
	439	static struct i2c_board_info migor_i2c_camera[] = {
ff04ea40 KM	440	{
ff04ea40 KM	441	I2C_BOARD_INFO("ov772x", 0x21),
ff04ea40	442	},
deae7b86 KM	443	{
deae7b86 KM	444	I2C_BOARD_INFO("tw9910", 0x45),
deae7b86	445	},
0c6111ec MD	446	};
0c6111ec MD	447
cb626371	448	static struct ov772x_camera_info ov7725_info;
0f448294 GL	449
	450	static struct soc_camera_link ov7725_link = {
	451	.power = ov7725_power,
	452	.board_info = &migor_i2c_camera[0],
	453	.i2c_adapter_id = 0,
0f448294	454	.priv = &ov7725_info,
2cb582ca GL	455	};
	456
	457	static struct tw9910_video_info tw9910_info = {
	458	.buswidth = SOCAM_DATAWIDTH_8,
	459	.mpout = TW9910_MPO_FIELD,
0f448294 GL	460	};
	461
	462	static struct soc_camera_link tw9910_link = {
	463	.power = tw9910_power,
	464	.board_info = &migor_i2c_camera[1],
	465	.i2c_adapter_id = 0,
0f448294	466	.priv = &tw9910_info,
2cb582ca GL	467	};
	468
	469	static struct platform_device migor_camera[] = {
	470	{
	471	.name = "soc-camera-pdrv",
	472	.id = 0,
	473	.dev = {
0f448294	474	.platform_data = &ov7725_link,
2cb582ca GL	475	},
	476	}, {
	477	.name = "soc-camera-pdrv",
	478	.id = 1,
	479	.dev = {
0f448294	480	.platform_data = &tw9910_link,
2cb582ca GL	481	},
	482	},
	483	};
	484
	485	static struct platform_device *migor_devices[] __initdata = {
	486	&smc91x_eth_device,
	487	&sh_keysc_device,
	488	&migor_lcdc_device,
	489	&migor_ceu_device,
	490	&migor_nor_flash_device,
	491	&migor_nand_flash_device,
2e3fc56c	492	&sdhi_cn9_device,
2cb582ca GL	493	&migor_camera[0],
	494	&migor_camera[1],
	495	};
	496
13fa551b MD	497	extern char migor_sdram_enter_start;
	498	extern char migor_sdram_enter_end;
	499	extern char migor_sdram_leave_start;
	500	extern char migor_sdram_leave_end;
	501
70f784ec MD	502	static int __init migor_devices_setup(void)
70f784ec MD	503	{
13fa551b MD	504	/* register board specific self-refresh code */
	505	sh_mobile_register_self_refresh(SUSP_SH_STANDBY \| SUSP_SH_SF,
	506	&migor_sdram_enter_start,
	507	&migor_sdram_enter_end,
	508	&migor_sdram_leave_start,
	509	&migor_sdram_leave_end);
48aff643 GL	510
	511	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
	512	ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	513
50840714 MD	514	/* Let D11 LED show STATUS0 */
	515	gpio_request(GPIO_FN_STATUS0, NULL);
	516
	517	/* Lit D12 LED show PDSTATUS */
	518	gpio_request(GPIO_FN_PDSTATUS, NULL);
91b6f3c5	519
a30c89ad	520	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	521	gpio_request(GPIO_FN_IRQ0, NULL);
9d56dd3b PM	522	__raw_writel(0x00003400, BSC_CS4BCR);
9d56dd3b PM	523	__raw_writel(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	524
91b6f3c5 MD	525	/* KEYSC */
91b6f3c5 MD	526	gpio_request(GPIO_FN_KEYOUT0, NULL);
	527	gpio_request(GPIO_FN_KEYOUT1, NULL);
	528	gpio_request(GPIO_FN_KEYOUT2, NULL);
	529	gpio_request(GPIO_FN_KEYOUT3, NULL);
	530	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	531	gpio_request(GPIO_FN_KEYIN1, NULL);
	532	gpio_request(GPIO_FN_KEYIN2, NULL);
	533	gpio_request(GPIO_FN_KEYIN3, NULL);
	534	gpio_request(GPIO_FN_KEYIN4, NULL);
	535	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	536
	537	/* NAND Flash */
	538	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
9d56dd3b	539	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
91b6f3c5 MD	540	gpio_request(GPIO_PTA1, NULL);
	541	gpio_direction_input(GPIO_PTA1);
	542
2e3fc56c MD	543	/* SDHI */
	544	gpio_request(GPIO_FN_SDHICD, NULL);
	545	gpio_request(GPIO_FN_SDHIWP, NULL);
	546	gpio_request(GPIO_FN_SDHID3, NULL);
	547	gpio_request(GPIO_FN_SDHID2, NULL);
	548	gpio_request(GPIO_FN_SDHID1, NULL);
	549	gpio_request(GPIO_FN_SDHID0, NULL);
	550	gpio_request(GPIO_FN_SDHICMD, NULL);
	551	gpio_request(GPIO_FN_SDHICLK, NULL);
	552
91b6f3c5 MD	553	/* Touch Panel */
	554	gpio_request(GPIO_FN_IRQ6, NULL);
	555
	556	/* LCD Panel */
91b6f3c5 MD	557	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	558	gpio_request(GPIO_FN_LCDD17, NULL);
	559	gpio_request(GPIO_FN_LCDD16, NULL);
	560	gpio_request(GPIO_FN_LCDD15, NULL);
	561	gpio_request(GPIO_FN_LCDD14, NULL);
	562	gpio_request(GPIO_FN_LCDD13, NULL);
	563	gpio_request(GPIO_FN_LCDD12, NULL);
	564	gpio_request(GPIO_FN_LCDD11, NULL);
	565	gpio_request(GPIO_FN_LCDD10, NULL);
	566	gpio_request(GPIO_FN_LCDD8, NULL);
	567	gpio_request(GPIO_FN_LCDD7, NULL);
	568	gpio_request(GPIO_FN_LCDD6, NULL);
	569	gpio_request(GPIO_FN_LCDD5, NULL);
	570	gpio_request(GPIO_FN_LCDD4, NULL);
	571	gpio_request(GPIO_FN_LCDD3, NULL);
	572	gpio_request(GPIO_FN_LCDD2, NULL);
	573	gpio_request(GPIO_FN_LCDD1, NULL);
	574	gpio_request(GPIO_FN_LCDRS, NULL);
	575	gpio_request(GPIO_FN_LCDCS, NULL);
	576	gpio_request(GPIO_FN_LCDRD, NULL);
	577	gpio_request(GPIO_FN_LCDWR, NULL);
	578	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	579	gpio_direction_output(GPIO_PTH2, 1);
	580	#endif
	581	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	582	gpio_request(GPIO_FN_LCDD15, NULL);
	583	gpio_request(GPIO_FN_LCDD14, NULL);
	584	gpio_request(GPIO_FN_LCDD13, NULL);
	585	gpio_request(GPIO_FN_LCDD12, NULL);
	586	gpio_request(GPIO_FN_LCDD11, NULL);
	587	gpio_request(GPIO_FN_LCDD10, NULL);
	588	gpio_request(GPIO_FN_LCDD9, NULL);
	589	gpio_request(GPIO_FN_LCDD8, NULL);
	590	gpio_request(GPIO_FN_LCDD7, NULL);
	591	gpio_request(GPIO_FN_LCDD6, NULL);
	592	gpio_request(GPIO_FN_LCDD5, NULL);
	593	gpio_request(GPIO_FN_LCDD4, NULL);
	594	gpio_request(GPIO_FN_LCDD3, NULL);
	595	gpio_request(GPIO_FN_LCDD2, NULL);
	596	gpio_request(GPIO_FN_LCDD1, NULL);
	597	gpio_request(GPIO_FN_LCDD0, NULL);
	598	gpio_request(GPIO_FN_LCDLCLK, NULL);
	599	gpio_request(GPIO_FN_LCDDCK, NULL);
	600	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	601	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	602	gpio_request(GPIO_FN_LCDVSYN, NULL);
	603	gpio_request(GPIO_FN_LCDHSYN, NULL);
	604	gpio_request(GPIO_FN_LCDDISP, NULL);
	605	gpio_request(GPIO_FN_LCDDON, NULL);
	606	#endif
	607
	608	/* CEU */
91b6f3c5 MD	609	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	610	gpio_request(GPIO_FN_VIO_VD2, NULL);
	611	gpio_request(GPIO_FN_VIO_HD2, NULL);
	612	gpio_request(GPIO_FN_VIO_FLD, NULL);
	613	gpio_request(GPIO_FN_VIO_CKO, NULL);
	614	gpio_request(GPIO_FN_VIO_D15, NULL);
	615	gpio_request(GPIO_FN_VIO_D14, NULL);
	616	gpio_request(GPIO_FN_VIO_D13, NULL);
	617	gpio_request(GPIO_FN_VIO_D12, NULL);
	618	gpio_request(GPIO_FN_VIO_D11, NULL);
	619	gpio_request(GPIO_FN_VIO_D10, NULL);
	620	gpio_request(GPIO_FN_VIO_D9, NULL);
	621	gpio_request(GPIO_FN_VIO_D8, NULL);
	622
	623	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	624	gpio_direction_output(GPIO_PTT3, 0);
	625	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	626	gpio_direction_output(GPIO_PTT2, 1);
	627	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
	628	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	629	gpio_direction_output(GPIO_PTT0, 0);
	630	#else
	631	gpio_direction_output(GPIO_PTT0, 1);
	632	#endif
9d56dd3b	633	__raw_writew(__raw_readw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c MD	634
1765534c MD	635	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c	636
920925f9 GL	637	/* SIU: Port B */
	638	gpio_request(GPIO_FN_SIUBOLR, NULL);
	639	gpio_request(GPIO_FN_SIUBOBT, NULL);
	640	gpio_request(GPIO_FN_SIUBISLD, NULL);
	641	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	642	gpio_request(GPIO_FN_SIUMCKB, NULL);
	643
	644	/*
	645	* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	646	* output. Need only SIUB, set to output for master mode (table 34.2)
	647	*/
7d0b0a44	648	__raw_writew(__raw_readw(PORT_MSELCRA) \| 1, PORT_MSELCRA);
920925f9	649
0c6111ec MD	650	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	651	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	652
70f784ec MD	653	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
70f784ec MD	654	}
ba3a1701	655	arch_initcall(migor_devices_setup);
0ec80fdd MD	656
	657	/* Return the board specific boot mode pin configuration */
	658	static int migor_mode_pins(void)
	659	{
	660	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	661	* MD3=0: 16-bit Area0 Bus Width
	662	* MD5=1: Little Endian
	663	* TSTMD=1, MD8=0: Test Mode Disabled
	664	*/
	665	return MODE_PIN0 \| MODE_PIN1 \| MODE_PIN5;
	666	}
	667
	668	/*
	669	* The Machine Vector
	670	*/
	671	static struct sh_machine_vector mv_migor __initmv = {
	672	.mv_name = "Migo-R",
	673	.mv_mode_pins = migor_mode_pins,
	674	};