]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - arch/sh/boards/mach-migor/setup.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sh: landisk evt2irq migration.
[mirror_ubuntu-focal-kernel.git] / arch / sh / boards / mach-migor / setup.c
CommitLineData
70f784ec
MD		 1/*
2 * Renesas System Solutions Asia Pte. Ltd - Migo-R
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
92cfeb61 13#include <linux/input.h>
fc1d003d 14#include <linux/input/sh_keysc.h>
464495e5 15#include <linux/mmc/host.h>
960b9e7e 16#include <linux/mmc/sh_mobile_sdhi.h>
b8808786 17#include <linux/mtd/physmap.h>
3c803a9a 18#include <linux/mtd/nand.h>
0c6111ec 19#include <linux/i2c.h>
8a3ee0fc 20#include <linux/smc91x.h>
1765534c
MD		 21#include <linux/delay.h>
22#include <linux/clk.h>
91b6f3c5 23#include <linux/gpio.h>
a1ad8033 24#include <linux/videodev2.h>
70e5c4f0 25#include <video/sh_mobile_lcdc.h>
1765534c 26#include <media/sh_mobile_ceu.h>
ff04ea40 27#include <media/ov772x.h>
a1ad8033 28#include <media/soc_camera.h>
deae7b86 29#include <media/tw9910.h>
6c7d826c 30#include <asm/clock.h>
70f784ec
MD		 31#include <asm/machvec.h>
32#include <asm/io.h>
13fa551b 33#include <asm/suspend.h>
7639a454 34#include <mach/migor.h>
f7275650 35#include <cpu/sh7722.h>
70f784ec
MD		 36
37/* Address IRQ Size Bus Description
38 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
39 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
40 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
41 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
42 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
43 */
44
8a3ee0fc 45static struct smc91x_platdata smc91x_info = {
a30c89ad 46 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
8a3ee0fc
MD		 47};
48
70f784ec
MD		 49static struct resource smc91x_eth_resources[] = {
50 [0] = {
b026a23c
MD		 51 .name = "SMC91C111" ,
52 .start = 0x10000300,
53 .end = 0x1000030f,
70f784ec
MD		 54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
57 .start = 32, /* IRQ0 */
d280eadc 58 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
70f784ec
MD		 59 },
60};
61
62static struct platform_device smc91x_eth_device = {
63 .name = "smc91x",
64 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
65 .resource = smc91x_eth_resources,
8a3ee0fc
MD		 66 .dev = {
67 .platform_data = &smc91x_info,
68 },
70f784ec
MD		 69};
70
92cfeb61
MD		 71static struct sh_keysc_info sh_keysc_info = {
72 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
73 .scan_timing = 3,
74 .delay = 5,
75 .keycodes = {
76 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
77 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
78 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
79 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
80 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
81 },
82};
83
84static struct resource sh_keysc_resources[] = {
85 [0] = {
86 .start = 0x044b0000,
87 .end = 0x044b000f,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = 79,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device sh_keysc_device = {
97 .name = "sh_keysc",
090d951b 98 .id = 0, /* "keysc0" clock */
92cfeb61
MD		 99 .num_resources = ARRAY_SIZE(sh_keysc_resources),
100 .resource = sh_keysc_resources,
101 .dev = {
102 .platform_data = &sh_keysc_info,
103 },
104};
105
b8808786
MD		 106static struct mtd_partition migor_nor_flash_partitions[] =
107{
108 {
109 .name = "uboot",
110 .offset = 0,
111 .size = (1 * 1024 * 1024),
112 .mask_flags = MTD_WRITEABLE, /* Read-only */
113 },
114 {
115 .name = "rootfs",
116 .offset = MTDPART_OFS_APPEND,
117 .size = (15 * 1024 * 1024),
118 },
119 {
120 .name = "other",
121 .offset = MTDPART_OFS_APPEND,
122 .size = MTDPART_SIZ_FULL,
123 },
124};
125
126static struct physmap_flash_data migor_nor_flash_data = {
127 .width = 2,
128 .parts = migor_nor_flash_partitions,
129 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
130};
131
132static struct resource migor_nor_flash_resources[] = {
133 [0] = {
134 .name = "NOR Flash",
135 .start = 0x00000000,
136 .end = 0x03ffffff,
137 .flags = IORESOURCE_MEM,
138 }
139};
140
141static struct platform_device migor_nor_flash_device = {
142 .name = "physmap-flash",
143 .resource = migor_nor_flash_resources,
144 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
145 .dev = {
146 .platform_data = &migor_nor_flash_data,
147 },
148};
149
3c803a9a
MD		 150static struct mtd_partition migor_nand_flash_partitions[] = {
151 {
152 .name = "nanddata1",
153 .offset = 0x0,
154 .size = 512 * 1024 * 1024,
155 },
156 {
157 .name = "nanddata2",
158 .offset = MTDPART_OFS_APPEND,
159 .size = 512 * 1024 * 1024,
160 },
161};
162
163static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
164 unsigned int ctrl)
165{
166 struct nand_chip *chip = mtd->priv;
167
168 if (cmd == NAND_CMD_NONE)
169 return;
170
171 if (ctrl & NAND_CLE)
172 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
173 else if (ctrl & NAND_ALE)
174 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
175 else
176 writeb(cmd, chip->IO_ADDR_W);
177}
178
179static int migor_nand_flash_ready(struct mtd_info *mtd)
180{
91b6f3c5 181 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a
MD		 182}
183
30e0cc1a 184static struct platform_nand_data migor_nand_flash_data = {
3c803a9a
MD		 185 .chip = {
186 .nr_chips = 1,
187 .partitions = migor_nand_flash_partitions,
188 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
189 .chip_delay = 20,
190 .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
191 },
192 .ctrl = {
193 .dev_ready = migor_nand_flash_ready,
194 .cmd_ctrl = migor_nand_flash_cmd_ctl,
195 },
196};
197
198static struct resource migor_nand_flash_resources[] = {
199 [0] = {
200 .name = "NAND Flash",
201 .start = 0x18000000,
202 .end = 0x18ffffff,
203 .flags = IORESOURCE_MEM,
204 },
205};
206
207static struct platform_device migor_nand_flash_device = {
208 .name = "gen_nand",
209 .resource = migor_nand_flash_resources,
210 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
211 .dev = {
212 .platform_data = &migor_nand_flash_data,
213 }
214};
215
e04008eb 216static const struct fb_videomode migor_lcd_modes[] = {
44432407
GL		 217 {
218#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
219 .name = "LB070WV1",
220 .xres = 800,
221 .yres = 480,
222 .left_margin = 64,
223 .right_margin = 16,
224 .hsync_len = 120,
225 .sync = 0,
226#elif defined(CONFIG_SH_MIGOR_QVGA)
227 .name = "PH240320T",
228 .xres = 320,
229 .yres = 240,
230 .left_margin = 0,
231 .right_margin = 16,
232 .hsync_len = 8,
233 .sync = FB_SYNC_HOR_HIGH_ACT,
234#endif
235 .upper_margin = 1,
236 .lower_margin = 17,
237 .vsync_len = 2,
238 },
239};
240
8b1285f1 241static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
44432407 242#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
8b1285f1
MD		 243 .clock_source = LCDC_CLK_BUS,
244 .ch[0] = {
245 .chan = LCDC_CHAN_MAINLCD,
edd153a3 246 .fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1
MD		 247 .interface_type = RGB16,
248 .clock_divider = 2,
93ff2598
LP		 249 .lcd_modes = migor_lcd_modes,
250 .num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b 251 .panel_cfg = { /* 7.0 inch */
ce9c008c
MD		 252 .width = 152,
253 .height = 91,
254 },
8b1285f1 255 }
44432407 256#elif defined(CONFIG_SH_MIGOR_QVGA)
8b1285f1
MD		 257 .clock_source = LCDC_CLK_PERIPHERAL,
258 .ch[0] = {
259 .chan = LCDC_CHAN_MAINLCD,
edd153a3 260 .fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1
MD		 261 .interface_type = SYS16A,
262 .clock_divider = 10,
93ff2598
LP		 263 .lcd_modes = migor_lcd_modes,
264 .num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b
LP		 265 .panel_cfg = {
266 .width = 49, /* 2.4 inch */
ce9c008c 267 .height = 37,
8b1285f1
MD		 268 .setup_sys = migor_lcd_qvga_setup,
269 },
270 .sys_bus_cfg = {
271 .ldmt2r = 0x06000a09,
272 .ldmt3r = 0x180e3418,
b5868e8c
MD		 273 /* set 1s delay to encourage fsync() */
274 .deferred_io_msec = 1000,
8b1285f1
MD		 275 },
276 }
277#endif
278};
279
280static struct resource migor_lcdc_resources[] = {
281 [0] = {
282 .name = "LCDC",
283 .start = 0xfe940000, /* P4-only space */
a6f15ade 284 .end = 0xfe942fff,
8b1285f1
MD		 285 .flags = IORESOURCE_MEM,
286 },
07905554
MD		 287 [1] = {
288 .start = 28,
289 .flags = IORESOURCE_IRQ,
290 },
8b1285f1
MD		 291};
292
293static struct platform_device migor_lcdc_device = {
294 .name = "sh_mobile_lcdc_fb",
295 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
296 .resource = migor_lcdc_resources,
297 .dev = {
298 .platform_data = &sh_mobile_lcdc_info,
299 },
300};
301
1765534c 302static struct clk *camera_clk;
deae7b86 303static DEFINE_MUTEX(camera_lock);
1765534c 304
deae7b86 305static void camera_power_on(int is_tw)
1765534c 306{
deae7b86
KM		 307 mutex_lock(&camera_lock);
308
22ee3ba6
MD		 309 /* Use 10 MHz VIO_CKO instead of 24 MHz to work
310 * around signal quality issues on Panel Board V2.1.
311 */
1765534c 312 camera_clk = clk_get(NULL, "video_clk");
22ee3ba6 313 clk_set_rate(camera_clk, 10000000);
1765534c
MD		 314 clk_enable(camera_clk); /* start VIO_CKO */
315
91b6f3c5 316 /* use VIO_RST to take camera out of reset */
1765534c 317 mdelay(10);
deae7b86
KM		 318 if (is_tw) {
319 gpio_set_value(GPIO_PTT2, 0);
320 gpio_set_value(GPIO_PTT0, 0);
321 } else {
322 gpio_set_value(GPIO_PTT0, 1);
323 }
91b6f3c5 324 gpio_set_value(GPIO_PTT3, 0);
1765534c 325 mdelay(10);
91b6f3c5 326 gpio_set_value(GPIO_PTT3, 1);
4545bfa0 327 mdelay(10); /* wait to let chip come out of reset */
1765534c
MD		 328}
329
330static void camera_power_off(void)
331{
332 clk_disable(camera_clk); /* stop VIO_CKO */
333 clk_put(camera_clk);
334
91b6f3c5 335 gpio_set_value(GPIO_PTT3, 0);
deae7b86 336 mutex_unlock(&camera_lock);
1765534c
MD		 337}
338
ff04ea40
KM		 339static int ov7725_power(struct device *dev, int mode)
340{
341 if (mode)
deae7b86
KM		 342 camera_power_on(0);
343 else
344 camera_power_off();
345
346 return 0;
347}
348
349static int tw9910_power(struct device *dev, int mode)
350{
351 if (mode)
352 camera_power_on(1);
ff04ea40
KM		 353 else
354 camera_power_off();
355
356 return 0;
357}
358
1765534c 359static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
64935056 360 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
1765534c
MD		 361};
362
363static struct resource migor_ceu_resources[] = {
364 [0] = {
365 .name = "CEU",
366 .start = 0xfe910000,
367 .end = 0xfe91009f,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = 52,
372 .flags = IORESOURCE_IRQ,
373 },
374 [2] = {
375 /* place holder for contiguous memory */
376 },
377};
378
379static struct platform_device migor_ceu_device = {
380 .name = "sh_mobile_ceu",
a42b6dd6 381 .id = 0, /* "ceu0" clock */
1765534c
MD		 382 .num_resources = ARRAY_SIZE(migor_ceu_resources),
383 .resource = migor_ceu_resources,
384 .dev = {
385 .platform_data = &sh_mobile_ceu_info,
386 },
387};
388
2e3fc56c
MD		 389static struct resource sdhi_cn9_resources[] = {
390 [0] = {
391 .name = "SDHI",
392 .start = 0x04ce0000,
d80e9221 393 .end = 0x04ce00ff,
2e3fc56c
MD		 394 .flags = IORESOURCE_MEM,
395 },
396 [1] = {
8d9adaba 397 .start = 100,
2e3fc56c
MD		 398 .flags = IORESOURCE_IRQ,
399 },
70e5c4f0
MD		 400};
401
65a1b034
GL		 402static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
403 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
404 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
464495e5 405 .tmio_caps = MMC_CAP_SDIO_IRQ,
65a1b034
GL		 406};
407
2e3fc56c
MD		 408static struct platform_device sdhi_cn9_device = {
409 .name = "sh_mobile_sdhi",
410 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
411 .resource = sdhi_cn9_resources,
65a1b034
GL		 412 .dev = {
413 .platform_data = &sh7724_sdhi_data,
414 },
70e5c4f0
MD		 415};
416
1765534c 417static struct i2c_board_info migor_i2c_devices[] = {
57795867 418 {
3760f736 419 I2C_BOARD_INFO("rs5c372b", 0x32),
57795867 420 },
67908abf
MD		 421 {
422 I2C_BOARD_INFO("migor_ts", 0x51),
423 .irq = 38, /* IRQ6 */
424 },
920925f9
GL		 425 {
426 I2C_BOARD_INFO("wm8978", 0x1a),
427 },
2cb582ca
GL		 428};
429
430static struct i2c_board_info migor_i2c_camera[] = {
ff04ea40
KM		 431 {
432 I2C_BOARD_INFO("ov772x", 0x21),
ff04ea40 433 },
deae7b86
KM		 434 {
435 I2C_BOARD_INFO("tw9910", 0x45),
deae7b86 436 },
0c6111ec
MD		 437};
438
cb626371 439static struct ov772x_camera_info ov7725_info;
0f448294
GL		 440
441static struct soc_camera_link ov7725_link = {
442 .power = ov7725_power,
443 .board_info = &migor_i2c_camera[0],
444 .i2c_adapter_id = 0,
0f448294 445 .priv = &ov7725_info,
2cb582ca
GL		 446};
447
448static struct tw9910_video_info tw9910_info = {
449 .buswidth = SOCAM_DATAWIDTH_8,
450 .mpout = TW9910_MPO_FIELD,
0f448294
GL		 451};
452
453static struct soc_camera_link tw9910_link = {
454 .power = tw9910_power,
455 .board_info = &migor_i2c_camera[1],
456 .i2c_adapter_id = 0,
0f448294 457 .priv = &tw9910_info,
2cb582ca
GL		 458};
459
460static struct platform_device migor_camera[] = {
461 {
462 .name = "soc-camera-pdrv",
463 .id = 0,
464 .dev = {
0f448294 465 .platform_data = &ov7725_link,
2cb582ca
GL		 466 },
467 }, {
468 .name = "soc-camera-pdrv",
469 .id = 1,
470 .dev = {
0f448294 471 .platform_data = &tw9910_link,
2cb582ca
GL		 472 },
473 },
474};
475
476static struct platform_device *migor_devices[] __initdata = {
477 &smc91x_eth_device,
478 &sh_keysc_device,
479 &migor_lcdc_device,
480 &migor_ceu_device,
481 &migor_nor_flash_device,
482 &migor_nand_flash_device,
2e3fc56c 483 &sdhi_cn9_device,
2cb582ca
GL		 484 &migor_camera[0],
485 &migor_camera[1],
486};
487
13fa551b
MD		 488extern char migor_sdram_enter_start;
489extern char migor_sdram_enter_end;
490extern char migor_sdram_leave_start;
491extern char migor_sdram_leave_end;
492
70f784ec
MD		 493static int __init migor_devices_setup(void)
494{
13fa551b
MD		 495 /* register board specific self-refresh code */
496 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
497 &migor_sdram_enter_start,
498 &migor_sdram_enter_end,
499 &migor_sdram_leave_start,
500 &migor_sdram_leave_end);
50840714
MD		 501 /* Let D11 LED show STATUS0 */
502 gpio_request(GPIO_FN_STATUS0, NULL);
503
504 /* Lit D12 LED show PDSTATUS */
505 gpio_request(GPIO_FN_PDSTATUS, NULL);
91b6f3c5 506
a30c89ad 507 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5 508 gpio_request(GPIO_FN_IRQ0, NULL);
9d56dd3b
PM		 509 __raw_writel(0x00003400, BSC_CS4BCR);
510 __raw_writel(0x00110080, BSC_CS4WCR);
91b6f3c5
MD		 511
512 /* KEYSC */
91b6f3c5
MD		 513 gpio_request(GPIO_FN_KEYOUT0, NULL);
514 gpio_request(GPIO_FN_KEYOUT1, NULL);
515 gpio_request(GPIO_FN_KEYOUT2, NULL);
516 gpio_request(GPIO_FN_KEYOUT3, NULL);
517 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
518 gpio_request(GPIO_FN_KEYIN1, NULL);
519 gpio_request(GPIO_FN_KEYIN2, NULL);
520 gpio_request(GPIO_FN_KEYIN3, NULL);
521 gpio_request(GPIO_FN_KEYIN4, NULL);
522 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
523
524 /* NAND Flash */
525 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
9d56dd3b 526 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
91b6f3c5
MD		 527 gpio_request(GPIO_PTA1, NULL);
528 gpio_direction_input(GPIO_PTA1);
529
2e3fc56c
MD		 530 /* SDHI */
531 gpio_request(GPIO_FN_SDHICD, NULL);
532 gpio_request(GPIO_FN_SDHIWP, NULL);
533 gpio_request(GPIO_FN_SDHID3, NULL);
534 gpio_request(GPIO_FN_SDHID2, NULL);
535 gpio_request(GPIO_FN_SDHID1, NULL);
536 gpio_request(GPIO_FN_SDHID0, NULL);
537 gpio_request(GPIO_FN_SDHICMD, NULL);
538 gpio_request(GPIO_FN_SDHICLK, NULL);
539
91b6f3c5
MD		 540 /* Touch Panel */
541 gpio_request(GPIO_FN_IRQ6, NULL);
542
543 /* LCD Panel */
91b6f3c5
MD		 544#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
545 gpio_request(GPIO_FN_LCDD17, NULL);
546 gpio_request(GPIO_FN_LCDD16, NULL);
547 gpio_request(GPIO_FN_LCDD15, NULL);
548 gpio_request(GPIO_FN_LCDD14, NULL);
549 gpio_request(GPIO_FN_LCDD13, NULL);
550 gpio_request(GPIO_FN_LCDD12, NULL);
551 gpio_request(GPIO_FN_LCDD11, NULL);
552 gpio_request(GPIO_FN_LCDD10, NULL);
553 gpio_request(GPIO_FN_LCDD8, NULL);
554 gpio_request(GPIO_FN_LCDD7, NULL);
555 gpio_request(GPIO_FN_LCDD6, NULL);
556 gpio_request(GPIO_FN_LCDD5, NULL);
557 gpio_request(GPIO_FN_LCDD4, NULL);
558 gpio_request(GPIO_FN_LCDD3, NULL);
559 gpio_request(GPIO_FN_LCDD2, NULL);
560 gpio_request(GPIO_FN_LCDD1, NULL);
561 gpio_request(GPIO_FN_LCDRS, NULL);
562 gpio_request(GPIO_FN_LCDCS, NULL);
563 gpio_request(GPIO_FN_LCDRD, NULL);
564 gpio_request(GPIO_FN_LCDWR, NULL);
565 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
566 gpio_direction_output(GPIO_PTH2, 1);
567#endif
568#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
569 gpio_request(GPIO_FN_LCDD15, NULL);
570 gpio_request(GPIO_FN_LCDD14, NULL);
571 gpio_request(GPIO_FN_LCDD13, NULL);
572 gpio_request(GPIO_FN_LCDD12, NULL);
573 gpio_request(GPIO_FN_LCDD11, NULL);
574 gpio_request(GPIO_FN_LCDD10, NULL);
575 gpio_request(GPIO_FN_LCDD9, NULL);
576 gpio_request(GPIO_FN_LCDD8, NULL);
577 gpio_request(GPIO_FN_LCDD7, NULL);
578 gpio_request(GPIO_FN_LCDD6, NULL);
579 gpio_request(GPIO_FN_LCDD5, NULL);
580 gpio_request(GPIO_FN_LCDD4, NULL);
581 gpio_request(GPIO_FN_LCDD3, NULL);
582 gpio_request(GPIO_FN_LCDD2, NULL);
583 gpio_request(GPIO_FN_LCDD1, NULL);
584 gpio_request(GPIO_FN_LCDD0, NULL);
585 gpio_request(GPIO_FN_LCDLCLK, NULL);
586 gpio_request(GPIO_FN_LCDDCK, NULL);
587 gpio_request(GPIO_FN_LCDVEPWC, NULL);
588 gpio_request(GPIO_FN_LCDVCPWC, NULL);
589 gpio_request(GPIO_FN_LCDVSYN, NULL);
590 gpio_request(GPIO_FN_LCDHSYN, NULL);
591 gpio_request(GPIO_FN_LCDDISP, NULL);
592 gpio_request(GPIO_FN_LCDDON, NULL);
593#endif
594
595 /* CEU */
91b6f3c5
MD		 596 gpio_request(GPIO_FN_VIO_CLK2, NULL);
597 gpio_request(GPIO_FN_VIO_VD2, NULL);
598 gpio_request(GPIO_FN_VIO_HD2, NULL);
599 gpio_request(GPIO_FN_VIO_FLD, NULL);
600 gpio_request(GPIO_FN_VIO_CKO, NULL);
601 gpio_request(GPIO_FN_VIO_D15, NULL);
602 gpio_request(GPIO_FN_VIO_D14, NULL);
603 gpio_request(GPIO_FN_VIO_D13, NULL);
604 gpio_request(GPIO_FN_VIO_D12, NULL);
605 gpio_request(GPIO_FN_VIO_D11, NULL);
606 gpio_request(GPIO_FN_VIO_D10, NULL);
607 gpio_request(GPIO_FN_VIO_D9, NULL);
608 gpio_request(GPIO_FN_VIO_D8, NULL);
609
610 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
611 gpio_direction_output(GPIO_PTT3, 0);
612 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
613 gpio_direction_output(GPIO_PTT2, 1);
614 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
615#ifdef CONFIG_SH_MIGOR_RTA_WVGA
616 gpio_direction_output(GPIO_PTT0, 0);
617#else
618 gpio_direction_output(GPIO_PTT0, 1);
619#endif
9d56dd3b 620 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c
MD		 621
622 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c 623
920925f9
GL		 624 /* SIU: Port B */
625 gpio_request(GPIO_FN_SIUBOLR, NULL);
626 gpio_request(GPIO_FN_SIUBOBT, NULL);
627 gpio_request(GPIO_FN_SIUBISLD, NULL);
628 gpio_request(GPIO_FN_SIUBOSLD, NULL);
629 gpio_request(GPIO_FN_SIUMCKB, NULL);
630
631 /*
632 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
633 * output. Need only SIUB, set to output for master mode (table 34.2)
634 */
7d0b0a44 635 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
920925f9 636
0c6111ec
MD		 637 i2c_register_board_info(0, migor_i2c_devices,
638 ARRAY_SIZE(migor_i2c_devices));
91b6f3c5 639
70f784ec
MD		 640 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
641}
ba3a1701 642arch_initcall(migor_devices_setup);
0ec80fdd
MD		 643
644/* Return the board specific boot mode pin configuration */
645static int migor_mode_pins(void)
646{
647 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
648 * MD3=0: 16-bit Area0 Bus Width
649 * MD5=1: Little Endian
650 * TSTMD=1, MD8=0: Test Mode Disabled
651 */
652 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
653}
654
655/*
656 * The Machine Vector
657 */
658static struct sh_machine_vector mv_migor __initmv = {
659 .mv_name = "Migo-R",
660 .mv_mode_pins = migor_mode_pins,
661};
Ubuntu Focal Linux kernel mirror