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Commit | Line | Data |
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6865f0ea | 1 | /* |
5df38b9b | 2 | * Hitachi UL SolutionEngine 7722 FPGA IRQ Support. |
6865f0ea RS |
3 | * |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu | |
5df38b9b | 5 | * Copyright (C) 2012 Paul Mundt |
6865f0ea RS |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
5df38b9b PM |
11 | #define DRV_NAME "SE7722-FPGA" |
12 | #define pr_fmt(fmt) DRV_NAME ": " fmt | |
13 | ||
6865f0ea RS |
14 | #include <linux/init.h> |
15 | #include <linux/irq.h> | |
16 | #include <linux/interrupt.h> | |
5df38b9b PM |
17 | #include <linux/irqdomain.h> |
18 | #include <linux/io.h> | |
19 | #include <linux/err.h> | |
20 | #include <asm/sizes.h> | |
939a24a6 | 21 | #include <mach-se/mach/se7722.h> |
6865f0ea | 22 | |
5df38b9b PM |
23 | #define IRQ01_BASE_ADDR 0x11800000 |
24 | #define IRQ01_MODE_REG 0 | |
25 | #define IRQ01_STS_REG 4 | |
26 | #define IRQ01_MASK_REG 8 | |
a37c6c7a | 27 | |
5df38b9b PM |
28 | static void __iomem *se7722_irq_regs; |
29 | struct irq_domain *se7722_irq_domain; | |
6865f0ea | 30 | |
5df38b9b | 31 | static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) |
6865f0ea | 32 | { |
8228a048 | 33 | struct irq_data *data = irq_desc_get_irq_data(desc); |
5df38b9b PM |
34 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
35 | unsigned long mask; | |
36 | int bit; | |
6865f0ea | 37 | |
5df38b9b | 38 | chip->irq_mask_ack(data); |
6865f0ea | 39 | |
5df38b9b PM |
40 | mask = ioread16(se7722_irq_regs + IRQ01_STS_REG); |
41 | ||
42 | for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR) | |
43 | generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit)); | |
44 | ||
45 | chip->irq_unmask(data); | |
46 | } | |
47 | ||
48 | static void __init se7722_domain_init(void) | |
6865f0ea | 49 | { |
5df38b9b | 50 | int i; |
493a358e | 51 | |
5df38b9b PM |
52 | se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR, |
53 | &irq_domain_simple_ops, NULL); | |
54 | if (unlikely(!se7722_irq_domain)) { | |
55 | printk("Failed to get IRQ domain\n"); | |
56 | return; | |
57 | } | |
6865f0ea | 58 | |
5df38b9b PM |
59 | for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { |
60 | int irq = irq_create_mapping(se7722_irq_domain, i); | |
a37c6c7a | 61 | |
5df38b9b PM |
62 | if (unlikely(irq == 0)) { |
63 | printk("Failed to allocate IRQ %d\n", i); | |
64 | return; | |
65 | } | |
6865f0ea | 66 | } |
6865f0ea | 67 | } |
493a358e | 68 | |
5df38b9b | 69 | static void __init se7722_gc_init(void) |
6865f0ea | 70 | { |
5df38b9b PM |
71 | struct irq_chip_generic *gc; |
72 | struct irq_chip_type *ct; | |
73 | unsigned int irq_base; | |
493a358e | 74 | |
5df38b9b | 75 | irq_base = irq_linear_revmap(se7722_irq_domain, 0); |
6865f0ea | 76 | |
5df38b9b PM |
77 | gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs, |
78 | handle_level_irq); | |
79 | if (unlikely(!gc)) | |
80 | return; | |
a37c6c7a | 81 | |
5df38b9b PM |
82 | ct = gc->chip_types; |
83 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
84 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
493a358e | 85 | |
5df38b9b PM |
86 | ct->regs.mask = IRQ01_MASK_REG; |
87 | ||
88 | irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR), | |
89 | IRQ_GC_INIT_MASK_CACHE, | |
90 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
a37c6c7a | 91 | |
fcb8918f TG |
92 | irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); |
93 | irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); | |
493a358e | 94 | |
fcb8918f TG |
95 | irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); |
96 | irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); | |
6865f0ea | 97 | } |
5df38b9b PM |
98 | |
99 | /* | |
100 | * Initialize FPGA IRQs | |
101 | */ | |
102 | void __init init_se7722_IRQ(void) | |
103 | { | |
104 | se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16); | |
105 | if (unlikely(!se7722_irq_regs)) { | |
106 | printk("Failed to remap IRQ01 regs\n"); | |
107 | return; | |
108 | } | |
109 | ||
110 | /* | |
111 | * All FPGA IRQs disabled by default | |
112 | */ | |
113 | iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG); | |
114 | ||
115 | __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ | |
116 | ||
117 | se7722_domain_init(); | |
118 | se7722_gc_init(); | |
119 | } |