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287c1297 KM |
1 | /* |
2 | * linux/arch/sh/boards/se/7724/setup.c | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * | |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/mtd/physmap.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/smc91x.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/input.h> | |
fc1d003d | 22 | #include <linux/input/sh_keysc.h> |
9731f4a2 | 23 | #include <linux/usb/r8a66597.h> |
287c1297 KM |
24 | #include <video/sh_mobile_lcdc.h> |
25 | #include <media/sh_mobile_ceu.h> | |
3e9ad52b | 26 | #include <sound/sh_fsi.h> |
287c1297 KM |
27 | #include <asm/io.h> |
28 | #include <asm/heartbeat.h> | |
a80cad95 KM |
29 | #include <asm/sh_eth.h> |
30 | #include <asm/clock.h> | |
3b9f2952 | 31 | #include <asm/suspend.h> |
287c1297 KM |
32 | #include <cpu/sh7724.h> |
33 | #include <mach-se/mach/se7724.h> | |
34 | ||
35 | /* | |
36 | * SWx 1234 5678 | |
37 | * ------------------------------------ | |
38 | * SW31 : 1001 1100 : default | |
39 | * SW32 : 0111 1111 : use on board flash | |
40 | * | |
41 | * SW41 : abxx xxxx -> a = 0 : Analog monitor | |
42 | * 1 : Digital monitor | |
43 | * b = 0 : VGA | |
4f324311 KM |
44 | * 1 : 720p |
45 | */ | |
46 | ||
47 | /* | |
48 | * about 720p | |
49 | * | |
50 | * When you use 1280 x 720 lcdc output, | |
51 | * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz, | |
52 | * and change SW41 to use 720p | |
287c1297 KM |
53 | */ |
54 | ||
bec9fb07 KM |
55 | /* |
56 | * about sound | |
57 | * | |
58 | * This setup.c supports FSI slave mode. | |
59 | * Please change J20, J21, J22 pin to 1-2 connection. | |
60 | */ | |
61 | ||
287c1297 | 62 | /* Heartbeat */ |
a09d2831 PM |
63 | static struct resource heartbeat_resource = { |
64 | .start = PA_LED, | |
65 | .end = PA_LED, | |
66 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, | |
287c1297 KM |
67 | }; |
68 | ||
69 | static struct platform_device heartbeat_device = { | |
70 | .name = "heartbeat", | |
71 | .id = -1, | |
a09d2831 PM |
72 | .num_resources = 1, |
73 | .resource = &heartbeat_resource, | |
287c1297 KM |
74 | }; |
75 | ||
76 | /* LAN91C111 */ | |
77 | static struct smc91x_platdata smc91x_info = { | |
78 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | |
79 | }; | |
80 | ||
81 | static struct resource smc91x_eth_resources[] = { | |
82 | [0] = { | |
83 | .name = "SMC91C111" , | |
84 | .start = 0x1a300300, | |
85 | .end = 0x1a30030f, | |
86 | .flags = IORESOURCE_MEM, | |
87 | }, | |
88 | [1] = { | |
89 | .start = IRQ0_SMC, | |
90 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
91 | }, | |
92 | }; | |
93 | ||
94 | static struct platform_device smc91x_eth_device = { | |
95 | .name = "smc91x", | |
96 | .num_resources = ARRAY_SIZE(smc91x_eth_resources), | |
97 | .resource = smc91x_eth_resources, | |
98 | .dev = { | |
99 | .platform_data = &smc91x_info, | |
100 | }, | |
101 | }; | |
102 | ||
103 | /* MTD */ | |
104 | static struct mtd_partition nor_flash_partitions[] = { | |
105 | { | |
106 | .name = "uboot", | |
107 | .offset = 0, | |
108 | .size = (1 * 1024 * 1024), | |
109 | .mask_flags = MTD_WRITEABLE, /* Read-only */ | |
110 | }, { | |
111 | .name = "kernel", | |
112 | .offset = MTDPART_OFS_APPEND, | |
113 | .size = (2 * 1024 * 1024), | |
114 | }, { | |
115 | .name = "free-area", | |
116 | .offset = MTDPART_OFS_APPEND, | |
117 | .size = MTDPART_SIZ_FULL, | |
118 | }, | |
119 | }; | |
120 | ||
121 | static struct physmap_flash_data nor_flash_data = { | |
122 | .width = 2, | |
123 | .parts = nor_flash_partitions, | |
124 | .nr_parts = ARRAY_SIZE(nor_flash_partitions), | |
125 | }; | |
126 | ||
127 | static struct resource nor_flash_resources[] = { | |
128 | [0] = { | |
129 | .name = "NOR Flash", | |
130 | .start = 0x00000000, | |
131 | .end = 0x01ffffff, | |
132 | .flags = IORESOURCE_MEM, | |
133 | } | |
134 | }; | |
135 | ||
136 | static struct platform_device nor_flash_device = { | |
137 | .name = "physmap-flash", | |
138 | .resource = nor_flash_resources, | |
139 | .num_resources = ARRAY_SIZE(nor_flash_resources), | |
140 | .dev = { | |
141 | .platform_data = &nor_flash_data, | |
142 | }, | |
143 | }; | |
144 | ||
145 | /* LCDC */ | |
146 | static struct sh_mobile_lcdc_info lcdc_info = { | |
147 | .clock_source = LCDC_CLK_EXTERNAL, | |
148 | .ch[0] = { | |
149 | .chan = LCDC_CHAN_MAINLCD, | |
150 | .bpp = 16, | |
151 | .clock_divider = 1, | |
152 | .lcd_cfg = { | |
153 | .name = "LB070WV1", | |
154 | .sync = 0, /* hsync and vsync are active low */ | |
155 | }, | |
156 | .lcd_size_cfg = { /* 7.0 inch */ | |
157 | .width = 152, | |
158 | .height = 91, | |
159 | }, | |
160 | .board_cfg = { | |
161 | }, | |
162 | } | |
163 | }; | |
164 | ||
165 | static struct resource lcdc_resources[] = { | |
166 | [0] = { | |
167 | .name = "LCDC", | |
168 | .start = 0xfe940000, | |
a6f15ade | 169 | .end = 0xfe942fff, |
287c1297 KM |
170 | .flags = IORESOURCE_MEM, |
171 | }, | |
172 | [1] = { | |
173 | .start = 106, | |
174 | .flags = IORESOURCE_IRQ, | |
175 | }, | |
176 | }; | |
177 | ||
178 | static struct platform_device lcdc_device = { | |
179 | .name = "sh_mobile_lcdc_fb", | |
180 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
181 | .resource = lcdc_resources, | |
182 | .dev = { | |
183 | .platform_data = &lcdc_info, | |
184 | }, | |
df47cd09 MD |
185 | .archdata = { |
186 | .hwblk_id = HWBLK_LCDC, | |
187 | }, | |
287c1297 KM |
188 | }; |
189 | ||
190 | /* CEU0 */ | |
191 | static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { | |
192 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
193 | }; | |
194 | ||
195 | static struct resource ceu0_resources[] = { | |
196 | [0] = { | |
197 | .name = "CEU0", | |
198 | .start = 0xfe910000, | |
199 | .end = 0xfe91009f, | |
200 | .flags = IORESOURCE_MEM, | |
201 | }, | |
202 | [1] = { | |
203 | .start = 52, | |
204 | .flags = IORESOURCE_IRQ, | |
205 | }, | |
206 | [2] = { | |
207 | /* place holder for contiguous memory */ | |
208 | }, | |
209 | }; | |
210 | ||
211 | static struct platform_device ceu0_device = { | |
212 | .name = "sh_mobile_ceu", | |
213 | .id = 0, /* "ceu0" clock */ | |
214 | .num_resources = ARRAY_SIZE(ceu0_resources), | |
215 | .resource = ceu0_resources, | |
216 | .dev = { | |
217 | .platform_data = &sh_mobile_ceu0_info, | |
218 | }, | |
df47cd09 MD |
219 | .archdata = { |
220 | .hwblk_id = HWBLK_CEU0, | |
221 | }, | |
287c1297 KM |
222 | }; |
223 | ||
224 | /* CEU1 */ | |
225 | static struct sh_mobile_ceu_info sh_mobile_ceu1_info = { | |
226 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | |
227 | }; | |
228 | ||
229 | static struct resource ceu1_resources[] = { | |
230 | [0] = { | |
231 | .name = "CEU1", | |
232 | .start = 0xfe914000, | |
233 | .end = 0xfe91409f, | |
234 | .flags = IORESOURCE_MEM, | |
235 | }, | |
236 | [1] = { | |
237 | .start = 63, | |
238 | .flags = IORESOURCE_IRQ, | |
239 | }, | |
240 | [2] = { | |
241 | /* place holder for contiguous memory */ | |
242 | }, | |
243 | }; | |
244 | ||
245 | static struct platform_device ceu1_device = { | |
246 | .name = "sh_mobile_ceu", | |
247 | .id = 1, /* "ceu1" clock */ | |
248 | .num_resources = ARRAY_SIZE(ceu1_resources), | |
249 | .resource = ceu1_resources, | |
250 | .dev = { | |
251 | .platform_data = &sh_mobile_ceu1_info, | |
252 | }, | |
df47cd09 MD |
253 | .archdata = { |
254 | .hwblk_id = HWBLK_CEU1, | |
255 | }, | |
287c1297 KM |
256 | }; |
257 | ||
3e9ad52b KM |
258 | /* FSI */ |
259 | /* | |
260 | * FSI-A use external clock which came from ak464x. | |
261 | * So, we should change parent of fsi | |
262 | */ | |
263 | #define FCLKACR 0xa4150008 | |
264 | static void fsimck_init(struct clk *clk) | |
265 | { | |
9d56dd3b | 266 | u32 status = __raw_readl(clk->enable_reg); |
3e9ad52b KM |
267 | |
268 | /* use external clock */ | |
269 | status &= ~0x000000ff; | |
270 | status |= 0x00000080; | |
9d56dd3b | 271 | __raw_writel(status, clk->enable_reg); |
3e9ad52b KM |
272 | } |
273 | ||
274 | static struct clk_ops fsimck_clk_ops = { | |
275 | .init = fsimck_init, | |
276 | }; | |
277 | ||
278 | static struct clk fsimcka_clk = { | |
3e9ad52b KM |
279 | .ops = &fsimck_clk_ops, |
280 | .enable_reg = (void __iomem *)FCLKACR, | |
281 | .rate = 0, /* unknown */ | |
282 | }; | |
283 | ||
bec9fb07 | 284 | /* change J20, J21, J22 pin to 1-2 connection to use slave mode */ |
3e9ad52b KM |
285 | struct sh_fsi_platform_info fsi_info = { |
286 | .porta_flags = SH_FSI_BRS_INV | | |
287 | SH_FSI_OUT_SLAVE_MODE | | |
288 | SH_FSI_IN_SLAVE_MODE | | |
289 | SH_FSI_OFMT(PCM) | | |
290 | SH_FSI_IFMT(PCM), | |
291 | }; | |
292 | ||
293 | static struct resource fsi_resources[] = { | |
294 | [0] = { | |
295 | .name = "FSI", | |
296 | .start = 0xFE3C0000, | |
297 | .end = 0xFE3C021d, | |
298 | .flags = IORESOURCE_MEM, | |
299 | }, | |
300 | [1] = { | |
301 | .start = 108, | |
302 | .flags = IORESOURCE_IRQ, | |
303 | }, | |
304 | }; | |
305 | ||
306 | static struct platform_device fsi_device = { | |
307 | .name = "sh_fsi", | |
308 | .id = 0, | |
309 | .num_resources = ARRAY_SIZE(fsi_resources), | |
310 | .resource = fsi_resources, | |
311 | .dev = { | |
312 | .platform_data = &fsi_info, | |
313 | }, | |
d53bd80c KM |
314 | .archdata = { |
315 | .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ | |
316 | }, | |
3e9ad52b KM |
317 | }; |
318 | ||
9747e78b | 319 | /* KEYSC in SoC (Needs SW33-2 set to ON) */ |
287c1297 KM |
320 | static struct sh_keysc_info keysc_info = { |
321 | .mode = SH_KEYSC_MODE_1, | |
29463c28 | 322 | .scan_timing = 3, |
287c1297 KM |
323 | .delay = 50, |
324 | .keycodes = { | |
325 | KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, | |
326 | KEY_6, KEY_7, KEY_8, KEY_9, KEY_A, | |
327 | KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, | |
328 | KEY_G, KEY_H, KEY_I, KEY_K, KEY_L, | |
329 | KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q, | |
330 | KEY_R, KEY_S, KEY_T, KEY_U, KEY_V, | |
331 | }, | |
332 | }; | |
333 | ||
334 | static struct resource keysc_resources[] = { | |
335 | [0] = { | |
9747e78b MD |
336 | .name = "KEYSC", |
337 | .start = 0x044b0000, | |
338 | .end = 0x044b000f, | |
287c1297 KM |
339 | .flags = IORESOURCE_MEM, |
340 | }, | |
341 | [1] = { | |
9747e78b | 342 | .start = 79, |
287c1297 KM |
343 | .flags = IORESOURCE_IRQ, |
344 | }, | |
345 | }; | |
346 | ||
347 | static struct platform_device keysc_device = { | |
348 | .name = "sh_keysc", | |
349 | .id = 0, /* "keysc0" clock */ | |
350 | .num_resources = ARRAY_SIZE(keysc_resources), | |
351 | .resource = keysc_resources, | |
352 | .dev = { | |
353 | .platform_data = &keysc_info, | |
354 | }, | |
df47cd09 MD |
355 | .archdata = { |
356 | .hwblk_id = HWBLK_KEYSC, | |
357 | }, | |
287c1297 KM |
358 | }; |
359 | ||
a80cad95 KM |
360 | /* SH Eth */ |
361 | static struct resource sh_eth_resources[] = { | |
362 | [0] = { | |
363 | .start = SH_ETH_ADDR, | |
364 | .end = SH_ETH_ADDR + 0x1FC, | |
365 | .flags = IORESOURCE_MEM, | |
366 | }, | |
367 | [1] = { | |
368 | .start = 91, | |
369 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
370 | }, | |
371 | }; | |
372 | ||
373 | struct sh_eth_plat_data sh_eth_plat = { | |
374 | .phy = 0x1f, /* SMSC LAN8187 */ | |
375 | .edmac_endian = EDMAC_LITTLE_ENDIAN, | |
376 | }; | |
377 | ||
378 | static struct platform_device sh_eth_device = { | |
379 | .name = "sh-eth", | |
380 | .id = 0, | |
381 | .dev = { | |
382 | .platform_data = &sh_eth_plat, | |
383 | }, | |
384 | .num_resources = ARRAY_SIZE(sh_eth_resources), | |
385 | .resource = sh_eth_resources, | |
df47cd09 MD |
386 | .archdata = { |
387 | .hwblk_id = HWBLK_ETHER, | |
388 | }, | |
a80cad95 KM |
389 | }; |
390 | ||
9731f4a2 | 391 | static struct r8a66597_platdata sh7724_usb0_host_data = { |
719a72b7 | 392 | .on_chip = 1, |
9731f4a2 MD |
393 | }; |
394 | ||
395 | static struct resource sh7724_usb0_host_resources[] = { | |
396 | [0] = { | |
397 | .start = 0xa4d80000, | |
1bc265d0 | 398 | .end = 0xa4d80124 - 1, |
9731f4a2 MD |
399 | .flags = IORESOURCE_MEM, |
400 | }, | |
401 | [1] = { | |
402 | .start = 65, | |
403 | .end = 65, | |
404 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
405 | }, | |
406 | }; | |
407 | ||
408 | static struct platform_device sh7724_usb0_host_device = { | |
409 | .name = "r8a66597_hcd", | |
410 | .id = 0, | |
411 | .dev = { | |
412 | .dma_mask = NULL, /* not use dma */ | |
413 | .coherent_dma_mask = 0xffffffff, | |
414 | .platform_data = &sh7724_usb0_host_data, | |
415 | }, | |
416 | .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), | |
417 | .resource = sh7724_usb0_host_resources, | |
df47cd09 MD |
418 | .archdata = { |
419 | .hwblk_id = HWBLK_USB0, | |
420 | }, | |
9731f4a2 MD |
421 | }; |
422 | ||
f8f8c079 MD |
423 | static struct r8a66597_platdata sh7724_usb1_gadget_data = { |
424 | .on_chip = 1, | |
425 | }; | |
426 | ||
427 | static struct resource sh7724_usb1_gadget_resources[] = { | |
428 | [0] = { | |
429 | .start = 0xa4d90000, | |
430 | .end = 0xa4d90123, | |
431 | .flags = IORESOURCE_MEM, | |
432 | }, | |
433 | [1] = { | |
434 | .start = 66, | |
435 | .end = 66, | |
436 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
437 | }, | |
438 | }; | |
439 | ||
440 | static struct platform_device sh7724_usb1_gadget_device = { | |
441 | .name = "r8a66597_udc", | |
442 | .id = 1, /* USB1 */ | |
443 | .dev = { | |
444 | .dma_mask = NULL, /* not use dma */ | |
445 | .coherent_dma_mask = 0xffffffff, | |
446 | .platform_data = &sh7724_usb1_gadget_data, | |
447 | }, | |
448 | .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources), | |
449 | .resource = sh7724_usb1_gadget_resources, | |
450 | }; | |
451 | ||
0f79af60 MD |
452 | static struct resource sdhi0_cn7_resources[] = { |
453 | [0] = { | |
454 | .name = "SDHI0", | |
455 | .start = 0x04ce0000, | |
456 | .end = 0x04ce01ff, | |
457 | .flags = IORESOURCE_MEM, | |
458 | }, | |
459 | [1] = { | |
3844eadc | 460 | .start = 100, |
0f79af60 MD |
461 | .flags = IORESOURCE_IRQ, |
462 | }, | |
463 | }; | |
464 | ||
465 | static struct platform_device sdhi0_cn7_device = { | |
466 | .name = "sh_mobile_sdhi", | |
5b380ec1 | 467 | .id = 0, |
0f79af60 MD |
468 | .num_resources = ARRAY_SIZE(sdhi0_cn7_resources), |
469 | .resource = sdhi0_cn7_resources, | |
470 | .archdata = { | |
471 | .hwblk_id = HWBLK_SDHI0, | |
472 | }, | |
473 | }; | |
474 | ||
5b380ec1 MD |
475 | static struct resource sdhi1_cn8_resources[] = { |
476 | [0] = { | |
477 | .name = "SDHI1", | |
478 | .start = 0x04cf0000, | |
479 | .end = 0x04cf01ff, | |
480 | .flags = IORESOURCE_MEM, | |
481 | }, | |
482 | [1] = { | |
3844eadc | 483 | .start = 23, |
5b380ec1 MD |
484 | .flags = IORESOURCE_IRQ, |
485 | }, | |
486 | }; | |
487 | ||
488 | static struct platform_device sdhi1_cn8_device = { | |
489 | .name = "sh_mobile_sdhi", | |
490 | .id = 1, | |
491 | .num_resources = ARRAY_SIZE(sdhi1_cn8_resources), | |
492 | .resource = sdhi1_cn8_resources, | |
493 | .archdata = { | |
494 | .hwblk_id = HWBLK_SDHI1, | |
495 | }, | |
496 | }; | |
497 | ||
bbb892aa KM |
498 | /* IrDA */ |
499 | static struct resource irda_resources[] = { | |
500 | [0] = { | |
501 | .name = "IrDA", | |
502 | .start = 0xA45D0000, | |
503 | .end = 0xA45D0049, | |
504 | .flags = IORESOURCE_MEM, | |
505 | }, | |
506 | [1] = { | |
507 | .start = 20, | |
508 | .flags = IORESOURCE_IRQ, | |
509 | }, | |
510 | }; | |
511 | ||
512 | static struct platform_device irda_device = { | |
513 | .name = "sh_sir", | |
514 | .num_resources = ARRAY_SIZE(irda_resources), | |
515 | .resource = irda_resources, | |
516 | }; | |
517 | ||
287c1297 KM |
518 | static struct platform_device *ms7724se_devices[] __initdata = { |
519 | &heartbeat_device, | |
520 | &smc91x_eth_device, | |
521 | &lcdc_device, | |
522 | &nor_flash_device, | |
523 | &ceu0_device, | |
524 | &ceu1_device, | |
525 | &keysc_device, | |
a80cad95 | 526 | &sh_eth_device, |
9731f4a2 | 527 | &sh7724_usb0_host_device, |
f8f8c079 | 528 | &sh7724_usb1_gadget_device, |
3e9ad52b | 529 | &fsi_device, |
0f79af60 | 530 | &sdhi0_cn7_device, |
5b380ec1 | 531 | &sdhi1_cn8_device, |
bbb892aa | 532 | &irda_device, |
287c1297 KM |
533 | }; |
534 | ||
9f815a17 KM |
535 | /* I2C device */ |
536 | static struct i2c_board_info i2c0_devices[] = { | |
537 | { | |
538 | I2C_BOARD_INFO("ak4642", 0x12), | |
539 | }, | |
540 | }; | |
541 | ||
a80cad95 KM |
542 | #define EEPROM_OP 0xBA206000 |
543 | #define EEPROM_ADR 0xBA206004 | |
544 | #define EEPROM_DATA 0xBA20600C | |
545 | #define EEPROM_STAT 0xBA206010 | |
546 | #define EEPROM_STRT 0xBA206014 | |
547 | static int __init sh_eth_is_eeprom_ready(void) | |
548 | { | |
549 | int t = 10000; | |
550 | ||
551 | while (t--) { | |
9d56dd3b | 552 | if (!__raw_readw(EEPROM_STAT)) |
a80cad95 | 553 | return 1; |
c718aff2 | 554 | udelay(1); |
a80cad95 KM |
555 | } |
556 | ||
557 | printk(KERN_ERR "ms7724se can not access to eeprom\n"); | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static void __init sh_eth_init(void) | |
562 | { | |
563 | int i; | |
8013cc9a | 564 | u16 mac; |
a80cad95 KM |
565 | |
566 | /* check EEPROM status */ | |
567 | if (!sh_eth_is_eeprom_ready()) | |
568 | return; | |
569 | ||
570 | /* read MAC addr from EEPROM */ | |
571 | for (i = 0 ; i < 3 ; i++) { | |
9d56dd3b PM |
572 | __raw_writew(0x0, EEPROM_OP); /* read */ |
573 | __raw_writew(i*2, EEPROM_ADR); | |
574 | __raw_writew(0x1, EEPROM_STRT); | |
a80cad95 KM |
575 | if (!sh_eth_is_eeprom_ready()) |
576 | return; | |
577 | ||
9d56dd3b | 578 | mac = __raw_readw(EEPROM_DATA); |
8013cc9a MD |
579 | sh_eth_plat.mac_addr[i << 1] = mac & 0xff; |
580 | sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; | |
a80cad95 | 581 | } |
a80cad95 KM |
582 | } |
583 | ||
287c1297 KM |
584 | #define SW4140 0xBA201000 |
585 | #define FPGA_OUT 0xBA200400 | |
586 | #define PORT_HIZA 0xA4050158 | |
9731f4a2 | 587 | #define PORT_MSELCRB 0xA4050182 |
287c1297 KM |
588 | |
589 | #define SW41_A 0x0100 | |
590 | #define SW41_B 0x0200 | |
591 | #define SW41_C 0x0400 | |
592 | #define SW41_D 0x0800 | |
593 | #define SW41_E 0x1000 | |
594 | #define SW41_F 0x2000 | |
595 | #define SW41_G 0x4000 | |
596 | #define SW41_H 0x8000 | |
9731f4a2 | 597 | |
3b9f2952 MD |
598 | extern char ms7724se_sdram_enter_start; |
599 | extern char ms7724se_sdram_enter_end; | |
600 | extern char ms7724se_sdram_leave_start; | |
601 | extern char ms7724se_sdram_leave_end; | |
602 | ||
9f815a17 KM |
603 | |
604 | static int __init arch_setup(void) | |
605 | { | |
606 | /* enable I2C device */ | |
607 | i2c_register_board_info(0, i2c0_devices, | |
608 | ARRAY_SIZE(i2c0_devices)); | |
609 | return 0; | |
610 | } | |
611 | arch_initcall(arch_setup); | |
612 | ||
287c1297 KM |
613 | static int __init devices_setup(void) |
614 | { | |
9d56dd3b | 615 | u16 sw = __raw_readw(SW4140); /* select camera, monitor */ |
16afc9fb | 616 | struct clk *clk; |
287c1297 | 617 | |
3b9f2952 | 618 | /* register board specific self-refresh code */ |
b67cf284 MD |
619 | sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | |
620 | SUSP_SH_RSTANDBY, | |
3b9f2952 MD |
621 | &ms7724se_sdram_enter_start, |
622 | &ms7724se_sdram_enter_end, | |
623 | &ms7724se_sdram_leave_start, | |
624 | &ms7724se_sdram_leave_end); | |
287c1297 | 625 | /* Reset Release */ |
9d56dd3b | 626 | __raw_writew(__raw_readw(FPGA_OUT) & |
287c1297 KM |
627 | ~((1 << 1) | /* LAN */ |
628 | (1 << 6) | /* VIDEO DAC */ | |
3e9ad52b | 629 | (1 << 7) | /* AK4643 */ |
bbb892aa | 630 | (1 << 8) | /* IrDA */ |
a80cad95 KM |
631 | (1 << 12) | /* USB0 */ |
632 | (1 << 14)), /* RMII */ | |
287c1297 KM |
633 | FPGA_OUT); |
634 | ||
9731f4a2 | 635 | /* turn on USB clocks, use external clock */ |
9d56dd3b | 636 | __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); |
9731f4a2 | 637 | |
7766e16b MD |
638 | /* Let LED9 show STATUS2 */ |
639 | gpio_request(GPIO_FN_STATUS2, NULL); | |
640 | ||
641 | /* Lit LED10 show STATUS0 */ | |
642 | gpio_request(GPIO_FN_STATUS0, NULL); | |
643 | ||
644 | /* Lit LED11 show PDSTATUS */ | |
645 | gpio_request(GPIO_FN_PDSTATUS, NULL); | |
7766e16b | 646 | |
9731f4a2 | 647 | /* enable USB0 port */ |
9d56dd3b | 648 | __raw_writew(0x0600, 0xa40501d4); |
9731f4a2 | 649 | |
f8f8c079 | 650 | /* enable USB1 port */ |
9d56dd3b | 651 | __raw_writew(0x0600, 0xa4050192); |
f8f8c079 | 652 | |
287c1297 KM |
653 | /* enable IRQ 0,1,2 */ |
654 | gpio_request(GPIO_FN_INTC_IRQ0, NULL); | |
655 | gpio_request(GPIO_FN_INTC_IRQ1, NULL); | |
656 | gpio_request(GPIO_FN_INTC_IRQ2, NULL); | |
657 | ||
658 | /* enable SCIFA3 */ | |
659 | gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); | |
660 | gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); | |
661 | gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); | |
662 | gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); | |
663 | gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); | |
664 | ||
665 | /* enable LCDC */ | |
666 | gpio_request(GPIO_FN_LCDD23, NULL); | |
667 | gpio_request(GPIO_FN_LCDD22, NULL); | |
668 | gpio_request(GPIO_FN_LCDD21, NULL); | |
669 | gpio_request(GPIO_FN_LCDD20, NULL); | |
670 | gpio_request(GPIO_FN_LCDD19, NULL); | |
671 | gpio_request(GPIO_FN_LCDD18, NULL); | |
672 | gpio_request(GPIO_FN_LCDD17, NULL); | |
673 | gpio_request(GPIO_FN_LCDD16, NULL); | |
674 | gpio_request(GPIO_FN_LCDD15, NULL); | |
675 | gpio_request(GPIO_FN_LCDD14, NULL); | |
676 | gpio_request(GPIO_FN_LCDD13, NULL); | |
677 | gpio_request(GPIO_FN_LCDD12, NULL); | |
678 | gpio_request(GPIO_FN_LCDD11, NULL); | |
679 | gpio_request(GPIO_FN_LCDD10, NULL); | |
680 | gpio_request(GPIO_FN_LCDD9, NULL); | |
681 | gpio_request(GPIO_FN_LCDD8, NULL); | |
682 | gpio_request(GPIO_FN_LCDD7, NULL); | |
683 | gpio_request(GPIO_FN_LCDD6, NULL); | |
684 | gpio_request(GPIO_FN_LCDD5, NULL); | |
685 | gpio_request(GPIO_FN_LCDD4, NULL); | |
686 | gpio_request(GPIO_FN_LCDD3, NULL); | |
687 | gpio_request(GPIO_FN_LCDD2, NULL); | |
688 | gpio_request(GPIO_FN_LCDD1, NULL); | |
689 | gpio_request(GPIO_FN_LCDD0, NULL); | |
690 | gpio_request(GPIO_FN_LCDDISP, NULL); | |
691 | gpio_request(GPIO_FN_LCDHSYN, NULL); | |
692 | gpio_request(GPIO_FN_LCDDCK, NULL); | |
693 | gpio_request(GPIO_FN_LCDVSYN, NULL); | |
694 | gpio_request(GPIO_FN_LCDDON, NULL); | |
695 | gpio_request(GPIO_FN_LCDVEPWC, NULL); | |
696 | gpio_request(GPIO_FN_LCDVCPWC, NULL); | |
697 | gpio_request(GPIO_FN_LCDRD, NULL); | |
698 | gpio_request(GPIO_FN_LCDLCLK, NULL); | |
9d56dd3b | 699 | __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); |
287c1297 KM |
700 | |
701 | /* enable CEU0 */ | |
702 | gpio_request(GPIO_FN_VIO0_D15, NULL); | |
703 | gpio_request(GPIO_FN_VIO0_D14, NULL); | |
704 | gpio_request(GPIO_FN_VIO0_D13, NULL); | |
705 | gpio_request(GPIO_FN_VIO0_D12, NULL); | |
706 | gpio_request(GPIO_FN_VIO0_D11, NULL); | |
707 | gpio_request(GPIO_FN_VIO0_D10, NULL); | |
708 | gpio_request(GPIO_FN_VIO0_D9, NULL); | |
709 | gpio_request(GPIO_FN_VIO0_D8, NULL); | |
710 | gpio_request(GPIO_FN_VIO0_D7, NULL); | |
711 | gpio_request(GPIO_FN_VIO0_D6, NULL); | |
712 | gpio_request(GPIO_FN_VIO0_D5, NULL); | |
713 | gpio_request(GPIO_FN_VIO0_D4, NULL); | |
714 | gpio_request(GPIO_FN_VIO0_D3, NULL); | |
715 | gpio_request(GPIO_FN_VIO0_D2, NULL); | |
716 | gpio_request(GPIO_FN_VIO0_D1, NULL); | |
717 | gpio_request(GPIO_FN_VIO0_D0, NULL); | |
718 | gpio_request(GPIO_FN_VIO0_VD, NULL); | |
719 | gpio_request(GPIO_FN_VIO0_CLK, NULL); | |
720 | gpio_request(GPIO_FN_VIO0_FLD, NULL); | |
721 | gpio_request(GPIO_FN_VIO0_HD, NULL); | |
84f7597c | 722 | platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); |
287c1297 KM |
723 | |
724 | /* enable CEU1 */ | |
725 | gpio_request(GPIO_FN_VIO1_D7, NULL); | |
726 | gpio_request(GPIO_FN_VIO1_D6, NULL); | |
727 | gpio_request(GPIO_FN_VIO1_D5, NULL); | |
728 | gpio_request(GPIO_FN_VIO1_D4, NULL); | |
729 | gpio_request(GPIO_FN_VIO1_D3, NULL); | |
730 | gpio_request(GPIO_FN_VIO1_D2, NULL); | |
731 | gpio_request(GPIO_FN_VIO1_D1, NULL); | |
732 | gpio_request(GPIO_FN_VIO1_D0, NULL); | |
733 | gpio_request(GPIO_FN_VIO1_FLD, NULL); | |
734 | gpio_request(GPIO_FN_VIO1_HD, NULL); | |
735 | gpio_request(GPIO_FN_VIO1_VD, NULL); | |
736 | gpio_request(GPIO_FN_VIO1_CLK, NULL); | |
84f7597c | 737 | platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); |
287c1297 KM |
738 | |
739 | /* KEYSC */ | |
740 | gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); | |
741 | gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); | |
742 | gpio_request(GPIO_FN_KEYIN4, NULL); | |
743 | gpio_request(GPIO_FN_KEYIN3, NULL); | |
744 | gpio_request(GPIO_FN_KEYIN2, NULL); | |
745 | gpio_request(GPIO_FN_KEYIN1, NULL); | |
746 | gpio_request(GPIO_FN_KEYIN0, NULL); | |
747 | gpio_request(GPIO_FN_KEYOUT3, NULL); | |
748 | gpio_request(GPIO_FN_KEYOUT2, NULL); | |
749 | gpio_request(GPIO_FN_KEYOUT1, NULL); | |
750 | gpio_request(GPIO_FN_KEYOUT0, NULL); | |
751 | ||
3e9ad52b KM |
752 | /* enable FSI */ |
753 | gpio_request(GPIO_FN_FSIMCKB, NULL); | |
754 | gpio_request(GPIO_FN_FSIMCKA, NULL); | |
755 | gpio_request(GPIO_FN_FSIOASD, NULL); | |
756 | gpio_request(GPIO_FN_FSIIABCK, NULL); | |
757 | gpio_request(GPIO_FN_FSIIALRCK, NULL); | |
758 | gpio_request(GPIO_FN_FSIOABCK, NULL); | |
759 | gpio_request(GPIO_FN_FSIOALRCK, NULL); | |
760 | gpio_request(GPIO_FN_CLKAUDIOAO, NULL); | |
761 | gpio_request(GPIO_FN_FSIIBSD, NULL); | |
762 | gpio_request(GPIO_FN_FSIOBSD, NULL); | |
763 | gpio_request(GPIO_FN_FSIIBBCK, NULL); | |
764 | gpio_request(GPIO_FN_FSIIBLRCK, NULL); | |
765 | gpio_request(GPIO_FN_FSIOBBCK, NULL); | |
766 | gpio_request(GPIO_FN_FSIOBLRCK, NULL); | |
767 | gpio_request(GPIO_FN_CLKAUDIOBO, NULL); | |
768 | gpio_request(GPIO_FN_FSIIASD, NULL); | |
769 | ||
16afc9fb KM |
770 | /* set SPU2 clock to 83.4 MHz */ |
771 | clk = clk_get(NULL, "spu_clk"); | |
03c5ecd1 KM |
772 | if (clk) { |
773 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); | |
774 | clk_put(clk); | |
775 | } | |
16afc9fb | 776 | |
3e9ad52b | 777 | /* change parent of FSI A */ |
16afc9fb | 778 | clk = clk_get(NULL, "fsia_clk"); |
03c5ecd1 KM |
779 | if (clk) { |
780 | clk_register(&fsimcka_clk); | |
781 | clk_set_parent(clk, &fsimcka_clk); | |
782 | clk_set_rate(clk, 11000); | |
783 | clk_set_rate(&fsimcka_clk, 11000); | |
784 | clk_put(clk); | |
785 | } | |
3e9ad52b | 786 | |
0f79af60 MD |
787 | /* SDHI0 connected to cn7 */ |
788 | gpio_request(GPIO_FN_SDHI0CD, NULL); | |
789 | gpio_request(GPIO_FN_SDHI0WP, NULL); | |
790 | gpio_request(GPIO_FN_SDHI0D3, NULL); | |
791 | gpio_request(GPIO_FN_SDHI0D2, NULL); | |
792 | gpio_request(GPIO_FN_SDHI0D1, NULL); | |
793 | gpio_request(GPIO_FN_SDHI0D0, NULL); | |
794 | gpio_request(GPIO_FN_SDHI0CMD, NULL); | |
795 | gpio_request(GPIO_FN_SDHI0CLK, NULL); | |
796 | ||
5b380ec1 MD |
797 | /* SDHI1 connected to cn8 */ |
798 | gpio_request(GPIO_FN_SDHI1CD, NULL); | |
799 | gpio_request(GPIO_FN_SDHI1WP, NULL); | |
800 | gpio_request(GPIO_FN_SDHI1D3, NULL); | |
801 | gpio_request(GPIO_FN_SDHI1D2, NULL); | |
802 | gpio_request(GPIO_FN_SDHI1D1, NULL); | |
803 | gpio_request(GPIO_FN_SDHI1D0, NULL); | |
804 | gpio_request(GPIO_FN_SDHI1CMD, NULL); | |
805 | gpio_request(GPIO_FN_SDHI1CLK, NULL); | |
806 | ||
bbb892aa KM |
807 | /* enable IrDA */ |
808 | gpio_request(GPIO_FN_IRDA_OUT, NULL); | |
809 | gpio_request(GPIO_FN_IRDA_IN, NULL); | |
810 | ||
a80cad95 KM |
811 | /* |
812 | * enable SH-Eth | |
813 | * | |
814 | * please remove J33 pin from your board !! | |
815 | * | |
816 | * ms7724 board should not use GPIO_FN_LNKSTA pin | |
817 | * So, This time PTX5 is set to input pin | |
818 | */ | |
819 | gpio_request(GPIO_FN_RMII_RXD0, NULL); | |
820 | gpio_request(GPIO_FN_RMII_RXD1, NULL); | |
821 | gpio_request(GPIO_FN_RMII_TXD0, NULL); | |
822 | gpio_request(GPIO_FN_RMII_TXD1, NULL); | |
823 | gpio_request(GPIO_FN_RMII_REF_CLK, NULL); | |
824 | gpio_request(GPIO_FN_RMII_TX_EN, NULL); | |
825 | gpio_request(GPIO_FN_RMII_RX_ER, NULL); | |
826 | gpio_request(GPIO_FN_RMII_CRS_DV, NULL); | |
827 | gpio_request(GPIO_FN_MDIO, NULL); | |
828 | gpio_request(GPIO_FN_MDC, NULL); | |
829 | gpio_request(GPIO_PTX5, NULL); | |
830 | gpio_direction_input(GPIO_PTX5); | |
831 | sh_eth_init(); | |
832 | ||
287c1297 | 833 | if (sw & SW41_B) { |
4f324311 KM |
834 | /* 720p */ |
835 | lcdc_info.ch[0].lcd_cfg.xres = 1280; | |
836 | lcdc_info.ch[0].lcd_cfg.yres = 720; | |
837 | lcdc_info.ch[0].lcd_cfg.left_margin = 220; | |
838 | lcdc_info.ch[0].lcd_cfg.right_margin = 110; | |
839 | lcdc_info.ch[0].lcd_cfg.hsync_len = 40; | |
840 | lcdc_info.ch[0].lcd_cfg.upper_margin = 20; | |
841 | lcdc_info.ch[0].lcd_cfg.lower_margin = 5; | |
842 | lcdc_info.ch[0].lcd_cfg.vsync_len = 5; | |
287c1297 KM |
843 | } else { |
844 | /* VGA */ | |
845 | lcdc_info.ch[0].lcd_cfg.xres = 640; | |
846 | lcdc_info.ch[0].lcd_cfg.yres = 480; | |
847 | lcdc_info.ch[0].lcd_cfg.left_margin = 105; | |
848 | lcdc_info.ch[0].lcd_cfg.right_margin = 50; | |
849 | lcdc_info.ch[0].lcd_cfg.hsync_len = 96; | |
850 | lcdc_info.ch[0].lcd_cfg.upper_margin = 33; | |
851 | lcdc_info.ch[0].lcd_cfg.lower_margin = 10; | |
852 | lcdc_info.ch[0].lcd_cfg.vsync_len = 2; | |
853 | } | |
854 | ||
855 | if (sw & SW41_A) { | |
856 | /* Digital monitor */ | |
857 | lcdc_info.ch[0].interface_type = RGB18; | |
858 | lcdc_info.ch[0].flags = 0; | |
859 | } else { | |
860 | /* Analog monitor */ | |
861 | lcdc_info.ch[0].interface_type = RGB24; | |
862 | lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; | |
863 | } | |
864 | ||
865 | return platform_add_devices(ms7724se_devices, | |
a80cad95 | 866 | ARRAY_SIZE(ms7724se_devices)); |
287c1297 KM |
867 | } |
868 | device_initcall(devices_setup); | |
869 | ||
870 | static struct sh_machine_vector mv_ms7724se __initmv = { | |
871 | .mv_name = "ms7724se", | |
872 | .mv_init_irq = init_se7724_IRQ, | |
873 | .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR, | |
874 | }; |