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4705b2e8 MD |
1 | /* |
2 | * sh7724 MMCIF loader | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #include <linux/mmc/sh_mmcif.h> | |
12 | #include <mach/romimage.h> | |
13 | ||
14 | #define MMCIF_BASE (void __iomem *)0xa4ca0000 | |
15 | ||
16 | #define MSTPCR2 0xa4150038 | |
17 | #define PTWCR 0xa4050146 | |
18 | #define PTXCR 0xa4050148 | |
19 | #define PSELA 0xa405014e | |
20 | #define PSELE 0xa4050156 | |
21 | #define HIZCRC 0xa405015c | |
22 | #define DRVCRA 0xa405018a | |
23 | ||
4705b2e8 MD |
24 | /* SH7724 specific MMCIF loader |
25 | * | |
26 | * loads the romImage from an MMC card starting from block 512 | |
27 | * use the following line to write the romImage to an MMC card | |
28 | * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512 | |
29 | */ | |
30 | asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes) | |
31 | { | |
32 | mmcif_update_progress(MMCIF_PROGRESS_ENTER); | |
33 | ||
34 | /* enable clock to the MMCIF hardware block */ | |
35 | __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); | |
36 | ||
37 | /* setup pins D7-D0 */ | |
38 | __raw_writew(0x0000, PTWCR); | |
39 | ||
40 | /* setup pins MMC_CLK, MMC_CMD */ | |
41 | __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR); | |
42 | ||
43 | /* select D3-D0 pin function */ | |
44 | __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA); | |
45 | ||
46 | /* select D7-D4 pin function */ | |
47 | __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE); | |
48 | ||
49 | /* disable Hi-Z for the MMC pins */ | |
50 | __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC); | |
51 | ||
52 | /* high drive capability for MMC pins */ | |
53 | __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); | |
54 | ||
55 | mmcif_update_progress(MMCIF_PROGRESS_INIT); | |
56 | ||
57 | /* setup MMCIF hardware */ | |
58 | sh_mmcif_boot_init(MMCIF_BASE); | |
59 | ||
60 | mmcif_update_progress(MMCIF_PROGRESS_LOAD); | |
61 | ||
62 | /* load kernel via MMCIF interface */ | |
63 | sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes); | |
64 | ||
65 | /* disable clock to the MMCIF hardware block */ | |
66 | __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); | |
67 | ||
68 | mmcif_update_progress(MMCIF_PROGRESS_DONE); | |
69 | } |