[mirror_ubuntu-zesty-kernel.git] / arch / sh / cchips / hd6446x / hd64461.c

/*
 *	Copyright (C) 2000 YAEGASHI Takeshi
 *	Hitachi HD64461 companion chip support
 */

#include <linux/sched.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hd64461.h>

/* This belongs in cpu specific */
#define INTC_ICR1 0xA4140010UL

static void hd64461_mask_irq(unsigned int irq)
{
	unsigned short nimr;
	unsigned short mask = 1 << (irq - HD64461_IRQBASE);

	nimr = __raw_readw(HD64461_NIMR);
	nimr |= mask;
	__raw_writew(nimr, HD64461_NIMR);
}

static void hd64461_unmask_irq(unsigned int irq)
{
	unsigned short nimr;
	unsigned short mask = 1 << (irq - HD64461_IRQBASE);

	nimr = __raw_readw(HD64461_NIMR);
	nimr &= ~mask;
	__raw_writew(nimr, HD64461_NIMR);
}

static void hd64461_mask_and_ack_irq(unsigned int irq)
{
	hd64461_mask_irq(irq);
#ifdef CONFIG_HD64461_ENABLER
	if (irq == HD64461_IRQBASE + 13)
		__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif
}

static struct irq_chip hd64461_irq_chip = {
	.name		= "HD64461-IRQ",
	.mask		= hd64461_mask_irq,
	.mask_ack	= hd64461_mask_and_ack_irq,
	.unmask		= hd64461_unmask_irq,
};

static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	unsigned short intv = __raw_readw(HD64461_NIRR);
	struct irq_desc *ext_desc;
	unsigned int ext_irq = HD64461_IRQBASE;

	intv &= (1 << HD64461_IRQ_NUM) - 1;

	while (intv) {
		if (intv & 1) {
			ext_desc = irq_desc + ext_irq;
			handle_level_irq(ext_irq, ext_desc);
		}
		intv >>= 1;
		ext_irq++;
	}
}

int __init setup_hd64461(void)
{
	int i;

	if (!MACH_HD64461)
		return 0;

	printk(KERN_INFO
	       "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
	       HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
	       HD64461_IRQBASE + 15);

/* Should be at processor specific part.. */
#if defined(CONFIG_CPU_SUBTYPE_SH7709)
	__raw_writew(0x2240, INTC_ICR1);
#endif
	__raw_writew(0xffff, HD64461_NIMR);

	/*  IRQ 80 -> 95 belongs to HD64461  */
	for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
		set_irq_chip_and_handler(i, &hd64461_irq_chip,
					 handle_level_irq);

	set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
	set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);

#ifdef CONFIG_HD64461_ENABLER
	printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
	__raw_writeb(0x4c, HD64461_PCC1CSCIER);
	__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif

	return 0;
}

module_init(setup_hd64461);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 2000 YAEGASHI Takeshi
	3	* Hitachi HD64461 companion chip support
	4	*/
	5
1da177e4 LT	6	#include <linux/sched.h>
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
	9	#include <linux/param.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/init.h>
	12	#include <linux/irq.h>
135210b3	13	#include <linux/io.h>
1da177e4	14	#include <asm/irq.h>
6d75e650	15	#include <asm/hd64461.h>
1da177e4	16
f1382305 KE	17	/* This belongs in cpu specific */
	18	#define INTC_ICR1 0xA4140010UL
	19
135210b3	20	static void hd64461_mask_irq(unsigned int irq)
1da177e4	21	{
1da177e4 LT	22	unsigned short nimr;
	23	unsigned short mask = 1 << (irq - HD64461_IRQBASE);
	24
135210b3	25	nimr = __raw_readw(HD64461_NIMR);
1da177e4	26	nimr \|= mask;
135210b3	27	__raw_writew(nimr, HD64461_NIMR);
1da177e4 LT	28	}
1da177e4 LT	29
135210b3	30	static void hd64461_unmask_irq(unsigned int irq)
1da177e4	31	{
1da177e4 LT	32	unsigned short nimr;
	33	unsigned short mask = 1 << (irq - HD64461_IRQBASE);
	34
135210b3	35	nimr = __raw_readw(HD64461_NIMR);
1da177e4	36	nimr &= ~mask;
135210b3	37	__raw_writew(nimr, HD64461_NIMR);
1da177e4 LT	38	}
1da177e4 LT	39
135210b3	40	static void hd64461_mask_and_ack_irq(unsigned int irq)
1da177e4	41	{
135210b3	42	hd64461_mask_irq(irq);
1da177e4 LT	43	#ifdef CONFIG_HD64461_ENABLER
1da177e4 LT	44	if (irq == HD64461_IRQBASE + 13)
135210b3	45	__raw_writeb(0x00, HD64461_PCC1CSCR);
1da177e4 LT	46	#endif
	47	}
	48
135210b3 MF	49	static struct irq_chip hd64461_irq_chip = {
	50	.name = "HD64461-IRQ",
	51	.mask = hd64461_mask_irq,
	52	.mask_ack = hd64461_mask_and_ack_irq,
	53	.unmask = hd64461_unmask_irq,
1da177e4 LT	54	};
1da177e4 LT	55
3bf50923	56	static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
1da177e4	57	{
9d56dd3b	58	unsigned short intv = __raw_readw(HD64461_NIRR);
3bf50923 RIZ	59	struct irq_desc *ext_desc;
	60	unsigned int ext_irq = HD64461_IRQBASE;
	61
	62	intv &= (1 << HD64461_IRQ_NUM) - 1;
	63
	64	while (intv) {
	65	if (intv & 1) {
	66	ext_desc = irq_desc + ext_irq;
	67	handle_level_irq(ext_irq, ext_desc);
	68	}
	69	intv >>= 1;
	70	ext_irq++;
1da177e4	71	}
1da177e4 LT	72	}
1da177e4 LT	73
1da177e4 LT	74	int __init setup_hd64461(void)
	75	{
	76	int i;
	77
	78	if (!MACH_HD64461)
	79	return 0;
	80
	81	printk(KERN_INFO
	82	"HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
62669e61	83	HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
1da177e4 LT	84	HD64461_IRQBASE + 15);
1da177e4 LT	85
135210b3 MF	86	/* Should be at processor specific part.. */
	87	#if defined(CONFIG_CPU_SUBTYPE_SH7709)
	88	__raw_writew(0x2240, INTC_ICR1);
1da177e4	89	#endif
135210b3	90	__raw_writew(0xffff, HD64461_NIMR);
1da177e4	91
f1382305	92	/* IRQ 80 -> 95 belongs to HD64461 */
135210b3 MF	93	for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
	94	set_irq_chip_and_handler(i, &hd64461_irq_chip,
	95	handle_level_irq);
1da177e4	96
3bf50923 RIZ	97	set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
	98	set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
	99
1da177e4 LT	100	#ifdef CONFIG_HD64461_ENABLER
1da177e4 LT	101	printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
135210b3 MF	102	__raw_writeb(0x4c, HD64461_PCC1CSCIER);
135210b3 MF	103	__raw_writeb(0x00, HD64461_PCC1CSCR);
1da177e4 LT	104	#endif
	105
	106	return 0;
	107	}
	108
	109	module_init(setup_hd64461);