[mirror_ubuntu-zesty-kernel.git] / arch / sh / cchips / hd6446x / hd64461.c

/*
 *	Copyright (C) 2000 YAEGASHI Takeshi
 *	Hitachi HD64461 companion chip support
 */

#include <linux/sched.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hd64461.h>

/* This belongs in cpu specific */
#define INTC_ICR1 0xA4140010UL

static void hd64461_mask_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned short nimr;
	unsigned short mask = 1 << (irq - HD64461_IRQBASE);

	nimr = __raw_readw(HD64461_NIMR);
	nimr |= mask;
	__raw_writew(nimr, HD64461_NIMR);
}

static void hd64461_unmask_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned short nimr;
	unsigned short mask = 1 << (irq - HD64461_IRQBASE);

	nimr = __raw_readw(HD64461_NIMR);
	nimr &= ~mask;
	__raw_writew(nimr, HD64461_NIMR);
}

static void hd64461_mask_and_ack_irq(struct irq_data *data)
{
	hd64461_mask_irq(data);

#ifdef CONFIG_HD64461_ENABLER
	if (data->irq == HD64461_IRQBASE + 13)
		__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif
}

static struct irq_chip hd64461_irq_chip = {
	.name		= "HD64461-IRQ",
	.irq_mask	= hd64461_mask_irq,
	.irq_mask_ack	= hd64461_mask_and_ack_irq,
	.irq_unmask	= hd64461_unmask_irq,
};

static void hd64461_irq_demux(struct irq_desc *desc)
{
	unsigned short intv = __raw_readw(HD64461_NIRR);
	unsigned int ext_irq = HD64461_IRQBASE;

	intv &= (1 << HD64461_IRQ_NUM) - 1;

	for (; intv; intv >>= 1, ext_irq++) {
		if (!(intv & 1))
			continue;

		generic_handle_irq(ext_irq);
	}
}

int __init setup_hd64461(void)
{
	int irq_base, i;

	printk(KERN_INFO
	       "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
	       HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
	       HD64461_IRQBASE + 15);

/* Should be at processor specific part.. */
#if defined(CONFIG_CPU_SUBTYPE_SH7709)
	__raw_writew(0x2240, INTC_ICR1);
#endif
	__raw_writew(0xffff, HD64461_NIMR);

	irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
	if (IS_ERR_VALUE(irq_base)) {
		pr_err("%s: failed hooking irqs for HD64461\n", __func__);
		return irq_base;
	}

	for (i = 0; i < 16; i++)
		irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
					 handle_level_irq);

	irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
	irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);

#ifdef CONFIG_HD64461_ENABLER
	printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
	__raw_writeb(0x4c, HD64461_PCC1CSCIER);
	__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif

	return 0;
}

module_init(setup_hd64461);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 2000 YAEGASHI Takeshi
	3	* Hitachi HD64461 companion chip support
	4	*/
	5
1da177e4 LT	6	#include <linux/sched.h>
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
	9	#include <linux/param.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/init.h>
	12	#include <linux/irq.h>
135210b3	13	#include <linux/io.h>
1da177e4	14	#include <asm/irq.h>
6d75e650	15	#include <asm/hd64461.h>
1da177e4	16
f1382305 KE	17	/* This belongs in cpu specific */
	18	#define INTC_ICR1 0xA4140010UL
	19
19add7e1	20	static void hd64461_mask_irq(struct irq_data *data)
1da177e4	21	{
19add7e1	22	unsigned int irq = data->irq;
1da177e4 LT	23	unsigned short nimr;
	24	unsigned short mask = 1 << (irq - HD64461_IRQBASE);
	25
135210b3	26	nimr = __raw_readw(HD64461_NIMR);
1da177e4	27	nimr \|= mask;
135210b3	28	__raw_writew(nimr, HD64461_NIMR);
1da177e4 LT	29	}
1da177e4 LT	30
19add7e1	31	static void hd64461_unmask_irq(struct irq_data *data)
1da177e4	32	{
19add7e1	33	unsigned int irq = data->irq;
1da177e4 LT	34	unsigned short nimr;
	35	unsigned short mask = 1 << (irq - HD64461_IRQBASE);
	36
135210b3	37	nimr = __raw_readw(HD64461_NIMR);
1da177e4	38	nimr &= ~mask;
135210b3	39	__raw_writew(nimr, HD64461_NIMR);
1da177e4 LT	40	}
1da177e4 LT	41
19add7e1	42	static void hd64461_mask_and_ack_irq(struct irq_data *data)
1da177e4	43	{
19add7e1 PM	44	hd64461_mask_irq(data);
19add7e1 PM	45
1da177e4	46	#ifdef CONFIG_HD64461_ENABLER
19add7e1	47	if (data->irq == HD64461_IRQBASE + 13)
135210b3	48	__raw_writeb(0x00, HD64461_PCC1CSCR);
1da177e4 LT	49	#endif
	50	}
	51
135210b3 MF	52	static struct irq_chip hd64461_irq_chip = {
135210b3 MF	53	.name = "HD64461-IRQ",
19add7e1 PM	54	.irq_mask = hd64461_mask_irq,
	55	.irq_mask_ack = hd64461_mask_and_ack_irq,
	56	.irq_unmask = hd64461_unmask_irq,
1da177e4 LT	57	};
1da177e4 LT	58
bd0b9ac4	59	static void hd64461_irq_demux(struct irq_desc *desc)
1da177e4	60	{
9d56dd3b	61	unsigned short intv = __raw_readw(HD64461_NIRR);
3bf50923 RIZ	62	unsigned int ext_irq = HD64461_IRQBASE;
	63
	64	intv &= (1 << HD64461_IRQ_NUM) - 1;
	65
b06ede84 PM	66	for (; intv; intv >>= 1, ext_irq++) {
	67	if (!(intv & 1))
	68	continue;
	69
	70	generic_handle_irq(ext_irq);
1da177e4	71	}
1da177e4 LT	72	}
1da177e4 LT	73
1da177e4 LT	74	int __init setup_hd64461(void)
1da177e4 LT	75	{
051f923d	76	int irq_base, i;
1da177e4 LT	77
	78	printk(KERN_INFO
	79	"HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
62669e61	80	HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
1da177e4 LT	81	HD64461_IRQBASE + 15);
1da177e4 LT	82
135210b3 MF	83	/* Should be at processor specific part.. */
	84	#if defined(CONFIG_CPU_SUBTYPE_SH7709)
	85	__raw_writew(0x2240, INTC_ICR1);
1da177e4	86	#endif
135210b3	87	__raw_writew(0xffff, HD64461_NIMR);
1da177e4	88
051f923d PM	89	irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
	90	if (IS_ERR_VALUE(irq_base)) {
	91	pr_err("%s: failed hooking irqs for HD64461\n", __func__);
	92	return irq_base;
6eb6f983	93	}
1da177e4	94
051f923d PM	95	for (i = 0; i < 16; i++)
	96	irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
	97	handle_level_irq);
	98
fcb8918f TG	99	irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
fcb8918f TG	100	irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
3bf50923	101
1da177e4 LT	102	#ifdef CONFIG_HD64461_ENABLER
1da177e4 LT	103	printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
135210b3 MF	104	__raw_writeb(0x4c, HD64461_PCC1CSCIER);
135210b3 MF	105	__raw_writeb(0x00, HD64461_PCC1CSCR);
1da177e4 LT	106	#endif
	107
	108	return 0;
	109	}
	110
	111	module_init(setup_hd64461);