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36d57ac4 L |
1 | #ifndef __ASM_SH_AUXVEC_H |
2 | #define __ASM_SH_AUXVEC_H | |
3 | ||
19f9a34f PM |
4 | /* |
5 | * Architecture-neutral AT_ values in 0-17, leave some room | |
6 | * for more of them. | |
7 | */ | |
8 | ||
98c4ecde PM |
9 | /* |
10 | * This entry gives some information about the FPU initialization | |
11 | * performed by the kernel. | |
12 | */ | |
13 | #define AT_FPUCW 18 /* Used FPU control word. */ | |
14 | ||
c170f86e | 15 | #if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__) |
19f9a34f PM |
16 | /* |
17 | * Only define this in the vsyscall case, the entry point to | |
18 | * the vsyscall page gets placed here. The kernel will attempt | |
19 | * to build a gate VMA we don't care about otherwise.. | |
20 | */ | |
21 | #define AT_SYSINFO_EHDR 33 | |
22 | #endif | |
23 | ||
cd01204b PM |
24 | /* |
25 | * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the | |
26 | * value is -1, then the cache doesn't exist. Otherwise: | |
27 | * | |
28 | * bit 0-3: Cache set-associativity; 0 means fully associative. | |
29 | * bit 4-7: Log2 of cacheline size. | |
30 | * bit 8-31: Size of the entire cache >> 8. | |
31 | */ | |
32 | #define AT_L1I_CACHESHAPE 34 | |
33 | #define AT_L1D_CACHESHAPE 35 | |
34 | #define AT_L2_CACHESHAPE 36 | |
35 | ||
e839ca52 DH |
36 | #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ |
37 | ||
36d57ac4 | 38 | #endif /* __ASM_SH_AUXVEC_H */ |