projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e839ca52 DH |
1 | /* |
| 2 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
| 3 | * Copyright (C) 2002 Paul Mundt | |
| 4 | */ | |
| 5 | #ifndef __ASM_SH_BARRIER_H | |
| 6 | #define __ASM_SH_BARRIER_H | |
| 7 | ||
| 8 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) | |
| 9 | #include <asm/cache_insns.h> | |
| 10 | #endif | |
| 11 | ||
| 12 | /* | |
| 13 | * A brief note on ctrl_barrier(), the control register write barrier. | |
| 14 | * | |
| 15 | * Legacy SH cores typically require a sequence of 8 nops after | |
| 16 | * modification of a control register in order for the changes to take | |
| 17 | * effect. On newer cores (like the sh4a and sh5) this is accomplished | |
| 18 | * with icbi. | |
| 19 | * | |
| 20 | * Also note that on sh4a in the icbi case we can forego a synco for the | |
| 21 | * write barrier, as it's not necessary for control registers. | |
| 22 | * | |
| 23 | * Historically we have only done this type of barrier for the MMUCR, but | |
| 24 | * it's also necessary for the CCR, so we make it generic here instead. | |
| 25 | */ | |
| 26 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) | |
| 27 | #define mb() __asm__ __volatile__ ("synco": : :"memory") | |
| 28 | #define rmb() mb() | |
| 93ea02bb | 29 | #define wmb() mb() |
| e839ca52 | 30 | #define ctrl_barrier() __icbi(PAGE_OFFSET) |
| e839ca52 | 31 | #else |
| e839ca52 | 32 | #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") |
| e839ca52 DH |
33 | #endif |
| 34 | ||
| b92b8b35 | 35 | #define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) |
| e839ca52 | 36 | |
| 93ea02bb PZ |
37 | #include <asm-generic/barrier.h> |
| 38 | ||
| e839ca52 | 39 | #endif /* __ASM_SH_BARRIER_H */ |