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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ |
3 | * | |
4 | * include/asm-sh/cache.h | |
5 | * | |
6 | * Copyright 1999 (C) Niibe Yutaka | |
7 | * Copyright 2002, 2003 (C) Paul Mundt | |
8 | */ | |
9 | #ifndef __ASM_SH_CACHE_H | |
10 | #define __ASM_SH_CACHE_H | |
11 | #ifdef __KERNEL__ | |
12 | ||
357d5946 | 13 | #include <linux/init.h> |
f15cbe6f | 14 | #include <cpu/cache.h> |
1da177e4 | 15 | |
1da177e4 | 16 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
1da177e4 | 17 | |
54cb27a7 | 18 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
121fc47d | 19 | |
87e29cac | 20 | #ifndef __ASSEMBLY__ |
1da177e4 | 21 | struct cache_info { |
b638d0b9 RC |
22 | unsigned int ways; /* Number of cache ways */ |
23 | unsigned int sets; /* Number of cache sets */ | |
24 | unsigned int linesz; /* Cache line size (bytes) */ | |
1da177e4 | 25 | |
b638d0b9 | 26 | unsigned int way_size; /* sets * line size */ |
1da177e4 | 27 | |
b638d0b9 RC |
28 | /* |
29 | * way_incr is the address offset for accessing the next way | |
30 | * in memory mapped cache array ops. | |
31 | */ | |
32 | unsigned int way_incr; | |
1da177e4 LT |
33 | unsigned int entry_shift; |
34 | unsigned int entry_mask; | |
35 | ||
b638d0b9 RC |
36 | /* |
37 | * Compute a mask which selects the address bits which overlap between | |
38 | * 1. those used to select the cache set during indexing | |
39 | * 2. those in the physical page number. | |
40 | */ | |
41 | unsigned int alias_mask; | |
b638d0b9 RC |
42 | unsigned int n_aliases; /* Number of aliases */ |
43 | ||
1da177e4 LT |
44 | unsigned long flags; |
45 | }; | |
87e29cac | 46 | #endif /* __ASSEMBLY__ */ |
1da177e4 LT |
47 | #endif /* __KERNEL__ */ |
48 | #endif /* __ASM_SH_CACHE_H */ |