[mirror_ubuntu-bionic-kernel.git] / arch / sh / include / asm / hd64461.h

#ifndef __ASM_SH_HD64461
#define __ASM_SH_HD64461
/*
 *	Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
 *	Copyright (C) 2004 Paul Mundt
 *	Copyright (C) 2000 YAEGASHI Takeshi
 *
 *		Hitachi HD64461 companion chip support
 *	(please note manual reference 0x10000000 = 0xb0000000)
 */

/* Constants for PCMCIA mappings */
#define	HD64461_PCC_WINDOW	0x01000000

/* Area 6 - Slot 0 - memory and/or IO card */
#define HD64461_IOBASE		0xb0000000
#define HD64461_IO_OFFSET(x)	(HD64461_IOBASE + (x))
#define	HD64461_PCC0_BASE	HD64461_IO_OFFSET(0x8000000)
#define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */
#define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */
#define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */

/* Area 5 - Slot 1 - memory card only */
#define	HD64461_PCC1_BASE	HD64461_IO_OFFSET(0x4000000)
#define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */
#define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */

/* Standby Control Register for HD64461 */
#define	HD64461_STBCR			HD64461_IO_OFFSET(0x00000000)
#define	HD64461_STBCR_CKIO_STBY		0x2000
#define	HD64461_STBCR_SAFECKE_IST	0x1000
#define	HD64461_STBCR_SLCKE_IST		0x0800
#define	HD64461_STBCR_SAFECKE_OST	0x0400
#define	HD64461_STBCR_SLCKE_OST		0x0200
#define	HD64461_STBCR_SMIAST		0x0100
#define	HD64461_STBCR_SLCDST		0x0080
#define	HD64461_STBCR_SPC0ST		0x0040
#define	HD64461_STBCR_SPC1ST		0x0020
#define	HD64461_STBCR_SAFEST		0x0010
#define	HD64461_STBCR_STM0ST		0x0008
#define	HD64461_STBCR_STM1ST		0x0004
#define	HD64461_STBCR_SIRST		0x0002
#define	HD64461_STBCR_SURTST		0x0001

/* System Configuration Register */
#define	HD64461_SYSCR		HD64461_IO_OFFSET(0x02)

/* CPU Data Bus Control Register */
#define	HD64461_SCPUCR		HD64461_IO_OFFSET(0x04)

/* Base Address Register */
#define	HD64461_LCDCBAR		HD64461_IO_OFFSET(0x1000)

/* Line increment address */
#define	HD64461_LCDCLOR		HD64461_IO_OFFSET(0x1002)

/* Controls LCD controller */
#define	HD64461_LCDCCR		HD64461_IO_OFFSET(0x1004)

/* LCCDR control bits */
#define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */
#define	HD64461_LCDCCR_STREQ	0x0100	/* Standby Request */
#define	HD64461_LCDCCR_MOFF	0x0080	/* Memory Off */
#define	HD64461_LCDCCR_REFSEL	0x0040	/* Refresh Select */
#define	HD64461_LCDCCR_EPON	0x0020	/* End Power On */
#define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */

/* Controls LCD (1) */
#define	HD64461_LDR1		HD64461_IO_OFFSET(0x1010)
#define	HD64461_LDR1_DON	0x01	/* Display On */
#define	HD64461_LDR1_DINV	0x80	/* Display Invert */

/* Controls LCD (2) */
#define	HD64461_LDR2		HD64461_IO_OFFSET(0x1012)
#define	HD64461_LDHNCR		HD64461_IO_OFFSET(0x1014)	/* Number of horizontal characters */
#define	HD64461_LDHNSR		HD64461_IO_OFFSET(0x1016)	/* Specify output start position + width of CL1 */
#define	HD64461_LDVNTR		HD64461_IO_OFFSET(0x1018)	/* Specify total vertical lines */
#define	HD64461_LDVNDR		HD64461_IO_OFFSET(0x101a)	/* specify number of display vertical lines */
#define	HD64461_LDVSPR		HD64461_IO_OFFSET(0x101c)	/* specify vertical synchronization pos and AC nr */

/* Controls LCD (3) */
#define	HD64461_LDR3		HD64461_IO_OFFSET(0x101e)

/* Palette Registers */
#define	HD64461_CPTWAR		HD64461_IO_OFFSET(0x1030)	/* Color Palette Write Address Register */
#define	HD64461_CPTWDR		HD64461_IO_OFFSET(0x1032)	/* Color Palette Write Data Register */
#define	HD64461_CPTRAR		HD64461_IO_OFFSET(0x1034)	/* Color Palette Read Address Register */
#define	HD64461_CPTRDR		HD64461_IO_OFFSET(0x1036)	/* Color Palette Read Data Register */

#define	HD64461_GRDOR		HD64461_IO_OFFSET(0x1040)	/* Display Resolution Offset Register */
#define	HD64461_GRSCR		HD64461_IO_OFFSET(0x1042)	/* Solid Color Register */
#define	HD64461_GRCFGR		HD64461_IO_OFFSET(0x1044)	/* Accelerator Configuration Register */

#define	HD64461_GRCFGR_ACCSTATUS	0x10	/* Accelerator Status */
#define	HD64461_GRCFGR_ACCRESET		0x08	/* Accelerator Reset */
#define	HD64461_GRCFGR_ACCSTART_BITBLT	0x06	/* Accelerator Start BITBLT */
#define	HD64461_GRCFGR_ACCSTART_LINE	0x04	/* Accelerator Start Line Drawing */
#define	HD64461_GRCFGR_COLORDEPTH16	0x01	/* Sets Colordepth 16 for Accelerator */
#define	HD64461_GRCFGR_COLORDEPTH8	0x01	/* Sets Colordepth 8 for Accelerator */

/* Line Drawing Registers */
#define	HD64461_LNSARH		HD64461_IO_OFFSET(0x1046)	/* Line Start Address Register (H) */
#define	HD64461_LNSARL		HD64461_IO_OFFSET(0x1048)	/* Line Start Address Register (L) */
#define	HD64461_LNAXLR		HD64461_IO_OFFSET(0x104a)	/* Axis Pixel Length Register */
#define	HD64461_LNDGR		HD64461_IO_OFFSET(0x104c)	/* Diagonal Register */
#define	HD64461_LNAXR		HD64461_IO_OFFSET(0x104e)	/* Axial Register */
#define	HD64461_LNERTR		HD64461_IO_OFFSET(0x1050)	/* Start Error Term Register */
#define	HD64461_LNMDR		HD64461_IO_OFFSET(0x1052)	/* Line Mode Register */

/* BitBLT Registers */
#define	HD64461_BBTSSARH	HD64461_IO_OFFSET(0x1054)	/* Source Start Address Register (H) */
#define	HD64461_BBTSSARL	HD64461_IO_OFFSET(0x1056)	/* Source Start Address Register (L) */
#define	HD64461_BBTDSARH	HD64461_IO_OFFSET(0x1058)	/* Destination Start Address Register (H) */
#define	HD64461_BBTDSARL	HD64461_IO_OFFSET(0x105a)	/* Destination Start Address Register (L) */
#define	HD64461_BBTDWR		HD64461_IO_OFFSET(0x105c)	/* Destination Block Width Register */
#define	HD64461_BBTDHR		HD64461_IO_OFFSET(0x105e)	/* Destination Block Height Register */
#define	HD64461_BBTPARH		HD64461_IO_OFFSET(0x1060)	/* Pattern Start Address Register (H) */
#define	HD64461_BBTPARL		HD64461_IO_OFFSET(0x1062)	/* Pattern Start Address Register (L) */
#define	HD64461_BBTMARH		HD64461_IO_OFFSET(0x1064)	/* Mask Start Address Register (H) */
#define	HD64461_BBTMARL		HD64461_IO_OFFSET(0x1066)	/* Mask Start Address Register (L) */
#define	HD64461_BBTROPR		HD64461_IO_OFFSET(0x1068)	/* ROP Register */
#define	HD64461_BBTMDR		HD64461_IO_OFFSET(0x106a)	/* BitBLT Mode Register */

/* PC Card Controller Registers */
/* Maps to Physical Area 6 */
#define	HD64461_PCC0ISR		HD64461_IO_OFFSET(0x2000)	/* socket 0 interface status */
#define	HD64461_PCC0GCR		HD64461_IO_OFFSET(0x2002)	/* socket 0 general control */
#define	HD64461_PCC0CSCR	HD64461_IO_OFFSET(0x2004)	/* socket 0 card status change */
#define	HD64461_PCC0CSCIER	HD64461_IO_OFFSET(0x2006)	/* socket 0 card status change interrupt enable */
#define	HD64461_PCC0SCR		HD64461_IO_OFFSET(0x2008)	/* socket 0 software control */
/* Maps to Physical Area 5 */
#define	HD64461_PCC1ISR		HD64461_IO_OFFSET(0x2010)	/* socket 1 interface status */
#define	HD64461_PCC1GCR		HD64461_IO_OFFSET(0x2012)	/* socket 1 general control */
#define	HD64461_PCC1CSCR	HD64461_IO_OFFSET(0x2014)	/* socket 1 card status change */
#define	HD64461_PCC1CSCIER	HD64461_IO_OFFSET(0x2016)	/* socket 1 card status change interrupt enable */
#define	HD64461_PCC1SCR		HD64461_IO_OFFSET(0x2018)	/* socket 1 software control */

/* PCC Interface Status Register */
#define	HD64461_PCCISR_READY		0x80	/* card ready */
#define	HD64461_PCCISR_MWP		0x40	/* card write-protected */
#define	HD64461_PCCISR_VS2		0x20	/* voltage select pin 2 */
#define	HD64461_PCCISR_VS1		0x10	/* voltage select pin 1 */
#define	HD64461_PCCISR_CD2		0x08	/* card detect 2 */
#define	HD64461_PCCISR_CD1		0x04	/* card detect 1 */
#define	HD64461_PCCISR_BVD2		0x02	/* battery 1 */
#define	HD64461_PCCISR_BVD1		0x01	/* battery 1 */

#define	HD64461_PCCISR_PCD_MASK		0x0c	/* card detect */
#define	HD64461_PCCISR_BVD_MASK		0x03	/* battery voltage */
#define	HD64461_PCCISR_BVD_BATGOOD	0x03	/* battery good */
#define	HD64461_PCCISR_BVD_BATWARN	0x01	/* battery low warning */
#define	HD64461_PCCISR_BVD_BATDEAD1	0x02	/* battery dead */
#define	HD64461_PCCISR_BVD_BATDEAD2	0x00	/* battery dead */

/* PCC General Control Register */
#define	HD64461_PCCGCR_DRVE		0x80	/* output drive */
#define	HD64461_PCCGCR_PCCR		0x40	/* PC card reset */
#define	HD64461_PCCGCR_PCCT		0x20	/* PC card type, 1=IO&mem, 0=mem */
#define	HD64461_PCCGCR_VCC0		0x10	/* voltage control pin VCC0SEL0 */
#define	HD64461_PCCGCR_PMMOD		0x08	/* memory mode */
#define	HD64461_PCCGCR_PA25		0x04	/* pin A25 */
#define	HD64461_PCCGCR_PA24		0x02	/* pin A24 */
#define	HD64461_PCCGCR_REG		0x01	/* pin PCC0REG# */

/* PCC Card Status Change Register */
#define	HD64461_PCCCSCR_SCDI		0x80	/* sw card detect intr */
#define	HD64461_PCCCSCR_SRV1		0x40	/* reserved */
#define	HD64461_PCCCSCR_IREQ		0x20	/* IREQ intr req */
#define	HD64461_PCCCSCR_SC		0x10	/* STSCHG (status change) pin */
#define	HD64461_PCCCSCR_CDC		0x08	/* CD (card detect) change */
#define	HD64461_PCCCSCR_RC		0x04	/* READY change */
#define	HD64461_PCCCSCR_BW		0x02	/* battery warning change */
#define	HD64461_PCCCSCR_BD		0x01	/* battery dead change */

/* PCC Card Status Change Interrupt Enable Register */
#define	HD64461_PCCCSCIER_CRE		0x80	/* change reset enable */
#define	HD64461_PCCCSCIER_IREQE_MASK	0x60	/* IREQ enable */
#define	HD64461_PCCCSCIER_IREQE_DISABLED 0x00	/* IREQ disabled */
#define	HD64461_PCCCSCIER_IREQE_LEVEL	0x20	/* IREQ level-triggered */
#define	HD64461_PCCCSCIER_IREQE_FALLING	0x40	/* IREQ falling-edge-trig */
#define	HD64461_PCCCSCIER_IREQE_RISING	0x60	/* IREQ rising-edge-trig */

#define	HD64461_PCCCSCIER_SCE		0x10	/* status change enable */
#define	HD64461_PCCCSCIER_CDE		0x08	/* card detect change enable */
#define	HD64461_PCCCSCIER_RE		0x04	/* ready change enable */
#define	HD64461_PCCCSCIER_BWE		0x02	/* battery warn change enable */
#define	HD64461_PCCCSCIER_BDE		0x01	/* battery dead change enable*/

/* PCC Software Control Register */
#define	HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */
#define	HD64461_PCCSCR_SWP		0x01	/* write protect */

/* PCC0 Output Pins Control Register */
#define	HD64461_P0OCR		HD64461_IO_OFFSET(0x202a)

/* PCC1 Output Pins Control Register */
#define	HD64461_P1OCR		HD64461_IO_OFFSET(0x202c)

/* PC Card General Control Register */
#define	HD64461_PGCR		HD64461_IO_OFFSET(0x202e)

/* Port Control Registers */
#define	HD64461_GPACR		HD64461_IO_OFFSET(0x4000)	/* Port A - Handles IRDA/TIMER */
#define	HD64461_GPBCR		HD64461_IO_OFFSET(0x4002)	/* Port B - Handles UART */
#define	HD64461_GPCCR		HD64461_IO_OFFSET(0x4004)	/* Port C - Handles PCMCIA 1 */
#define	HD64461_GPDCR		HD64461_IO_OFFSET(0x4006)	/* Port D - Handles PCMCIA 1 */

/* Port Control Data Registers */
#define	HD64461_GPADR		HD64461_IO_OFFSET(0x4010)	/* A */
#define	HD64461_GPBDR		HD64461_IO_OFFSET(0x4012)	/* B */
#define	HD64461_GPCDR		HD64461_IO_OFFSET(0x4014)	/* C */
#define	HD64461_GPDDR		HD64461_IO_OFFSET(0x4016)	/* D */

/* Interrupt Control Registers */
#define	HD64461_GPAICR		HD64461_IO_OFFSET(0x4020)	/* A */
#define	HD64461_GPBICR		HD64461_IO_OFFSET(0x4022)	/* B */
#define	HD64461_GPCICR		HD64461_IO_OFFSET(0x4024)	/* C */
#define	HD64461_GPDICR		HD64461_IO_OFFSET(0x4026)	/* D */

/* Interrupt Status Registers */
#define	HD64461_GPAISR		HD64461_IO_OFFSET(0x4040)	/* A */
#define	HD64461_GPBISR		HD64461_IO_OFFSET(0x4042)	/* B */
#define	HD64461_GPCISR		HD64461_IO_OFFSET(0x4044)	/* C */
#define	HD64461_GPDISR		HD64461_IO_OFFSET(0x4046)	/* D */

/* Interrupt Request Register & Interrupt Mask Register */
#define	HD64461_NIRR		HD64461_IO_OFFSET(0x5000)
#define	HD64461_NIMR		HD64461_IO_OFFSET(0x5002)

#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE
#define	OFFCHIP_IRQ_BASE	64
#define	HD64461_IRQ_NUM		16

#define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)
#define	HD64461_IRQ_IRDA	(HD64461_IRQBASE+6)
#define	HD64461_IRQ_TMU1	(HD64461_IRQBASE+9)
#define	HD64461_IRQ_TMU0	(HD64461_IRQBASE+10)
#define	HD64461_IRQ_GPIO	(HD64461_IRQBASE+11)
#define	HD64461_IRQ_AFE		(HD64461_IRQBASE+12)
#define	HD64461_IRQ_PCC1	(HD64461_IRQBASE+13)
#define	HD64461_IRQ_PCC0	(HD64461_IRQBASE+14)

#define __IO_PREFIX	hd64461
#include <asm/io_generic.h>

/* arch/sh/cchips/hd6446x/hd64461/setup.c */
void hd64461_register_irq_demux(int irq,
				int (*demux) (int irq, void *dev), void *dev);
void hd64461_unregister_irq_demux(int irq);

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_HD64461
	2	#define __ASM_SH_HD64461
	3	/*
be15d65d KE	4	* Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
be15d65d KE	5	* Copyright (C) 2004 Paul Mundt
1da177e4	6	* Copyright (C) 2000 YAEGASHI Takeshi
be15d65d KE	7	*
	8	* Hitachi HD64461 companion chip support
	9	* (please note manual reference 0x10000000 = 0xb0000000)
1da177e4	10	*/
1da177e4 LT	11
1da177e4 LT	12	/* Constants for PCMCIA mappings */
be15d65d KE	13	#define HD64461_PCC_WINDOW 0x01000000
	14
	15	/* Area 6 - Slot 0 - memory and/or IO card */
bec36eca PM	16	#define HD64461_IOBASE 0xb0000000
	17	#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
	18	#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
be15d65d KE	19	#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
	20	#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
	21	#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2HD64461_PCC_WINDOW) / 0xba0000000 */
	22
	23	/* Area 5 - Slot 1 - memory card only */
bec36eca	24	#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
be15d65d KE	25	#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
	26	#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
	27
	28	/* Standby Control Register for HD64461 */
62669e61	29	#define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
be15d65d KE	30	#define HD64461_STBCR_CKIO_STBY 0x2000
	31	#define HD64461_STBCR_SAFECKE_IST 0x1000
	32	#define HD64461_STBCR_SLCKE_IST 0x0800
	33	#define HD64461_STBCR_SAFECKE_OST 0x0400
	34	#define HD64461_STBCR_SLCKE_OST 0x0200
	35	#define HD64461_STBCR_SMIAST 0x0100
	36	#define HD64461_STBCR_SLCDST 0x0080
	37	#define HD64461_STBCR_SPC0ST 0x0040
	38	#define HD64461_STBCR_SPC1ST 0x0020
	39	#define HD64461_STBCR_SAFEST 0x0010
	40	#define HD64461_STBCR_STM0ST 0x0008
	41	#define HD64461_STBCR_STM1ST 0x0004
	42	#define HD64461_STBCR_SIRST 0x0002
	43	#define HD64461_STBCR_SURTST 0x0001
	44
	45	/* System Configuration Register */
bec36eca	46	#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
be15d65d KE	47
be15d65d KE	48	/* CPU Data Bus Control Register */
bec36eca	49	#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
be15d65d	50
0095d58b	51	/* Base Address Register */
bec36eca	52	#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
be15d65d	53
0095d58b	54	/* Line increment address */
bec36eca	55	#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
be15d65d KE	56
be15d65d KE	57	/* Controls LCD controller */
bec36eca	58	#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
be15d65d KE	59
	60	/* LCCDR control bits */
	61	#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
	62	#define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
	63	#define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
	64	#define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
	65	#define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
	66	#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
	67
	68	/* Controls LCD (1) */
bec36eca	69	#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
be15d65d KE	70	#define HD64461_LDR1_DON 0x01 /* Display On */
	71	#define HD64461_LDR1_DINV 0x80 /* Display Invert */
	72
	73	/* Controls LCD (2) */
bec36eca PM	74	#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
	75	#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
	76	#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
	77	#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
	78	#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
	79	#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
be15d65d KE	80
be15d65d KE	81	/* Controls LCD (3) */
bec36eca	82	#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
be15d65d KE	83
be15d65d KE	84	/* Palette Registers */
bec36eca PM	85	#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
	86	#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
	87	#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
	88	#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
be15d65d	89
bec36eca PM	90	#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
	91	#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
	92	#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
be15d65d KE	93
	94	#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
	95	#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
	96	#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
	97	#define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
	98	#define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
	99	#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
	100
	101	/* Line Drawing Registers */
bec36eca PM	102	#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
	103	#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
	104	#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
	105	#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
	106	#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
	107	#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
	108	#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
be15d65d KE	109
be15d65d KE	110	/* BitBLT Registers */
bec36eca PM	111	#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
	112	#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
	113	#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
	114	#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
	115	#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
	116	#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
	117	#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
	118	#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
	119	#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
	120	#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
	121	#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
	122	#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
1da177e4 LT	123
1da177e4 LT	124	/* PC Card Controller Registers */
be15d65d	125	/* Maps to Physical Area 6 */
bec36eca PM	126	#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
	127	#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
	128	#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
	129	#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
	130	#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
be15d65d	131	/* Maps to Physical Area 5 */
bec36eca PM	132	#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
	133	#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
	134	#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
	135	#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
	136	#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
1da177e4 LT	137
1da177e4 LT	138	/* PCC Interface Status Register */
be15d65d KE	139	#define HD64461_PCCISR_READY 0x80 /* card ready */
	140	#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
	141	#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
	142	#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
	143	#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
	144	#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
	145	#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
	146	#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
	147
	148	#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
	149	#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
	150	#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
	151	#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
	152	#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
	153	#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
1da177e4 LT	154
1da177e4 LT	155	/* PCC General Control Register */
be15d65d KE	156	#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
	157	#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
	158	#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
	159	#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
	160	#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
	161	#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
	162	#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
	163	#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
1da177e4 LT	164
1da177e4 LT	165	/* PCC Card Status Change Register */
be15d65d KE	166	#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
	167	#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
	168	#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
	169	#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
	170	#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
	171	#define HD64461_PCCCSCR_RC 0x04 /* READY change */
	172	#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
	173	#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
1da177e4 LT	174
1da177e4 LT	175	/* PCC Card Status Change Interrupt Enable Register */
be15d65d KE	176	#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
	177	#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
	178	#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
	179	#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
	180	#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
	181	#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
	182
	183	#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
	184	#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
	185	#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
	186	#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
	187	#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
1da177e4 LT	188
1da177e4 LT	189	/* PCC Software Control Register */
be15d65d KE	190	#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
	191	#define HD64461_PCCSCR_SWP 0x01 /* write protect */
	192
	193	/* PCC0 Output Pins Control Register */
bec36eca	194	#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
be15d65d KE	195
be15d65d KE	196	/* PCC1 Output Pins Control Register */
bec36eca	197	#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
be15d65d KE	198
be15d65d KE	199	/* PC Card General Control Register */
bec36eca	200	#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
be15d65d KE	201
be15d65d KE	202	/* Port Control Registers */
bec36eca PM	203	#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
	204	#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
	205	#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
	206	#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
be15d65d KE	207
be15d65d KE	208	/* Port Control Data Registers */
bec36eca PM	209	#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
	210	#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
	211	#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
	212	#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
be15d65d KE	213
be15d65d KE	214	/* Interrupt Control Registers */
bec36eca PM	215	#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
	216	#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
	217	#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
	218	#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
be15d65d KE	219
be15d65d KE	220	/* Interrupt Status Registers */
bec36eca PM	221	#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
	222	#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
	223	#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
	224	#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
be15d65d KE	225
be15d65d KE	226	/* Interrupt Request Register & Interrupt Mask Register */
bec36eca PM	227	#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
bec36eca PM	228	#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
be15d65d KE	229
be15d65d KE	230	#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
f12468a6	231	#define OFFCHIP_IRQ_BASE 64
be15d65d KE	232	#define HD64461_IRQ_NUM 16
	233
	234	#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
	235	#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
	236	#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
	237	#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
	238	#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
	239	#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
	240	#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
	241	#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
6d75e650 PM	242
	243	#define __IO_PREFIX hd64461
	244	#include <asm/io_generic.h>
	245
	246	/* arch/sh/cchips/hd6446x/hd64461/setup.c */
6d75e650 PM	247	void hd64461_register_irq_demux(int irq,
	248	int (demux) (int irq, void dev), void *dev);
	249	void hd64461_unregister_irq_demux(int irq);
1da177e4 LT	250
1da177e4 LT	251	#endif