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sh: Use the now generic SH-4 clear/copy page ops for all MMU platforms.
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1da177e4 1/*
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2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
4 *
1da177e4 5 * Copyright (C) 1999 Niibe Yutaka
249cfea9 6 * Copyright (C) 2002 - 2007 Paul Mundt
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7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
1da177e4 11 */
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12#ifndef __ASM_SH_PGTABLE_H
13#define __ASM_SH_PGTABLE_H
1da177e4 14
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15#include <asm-generic/pgtable-nopmd.h>
16#include <asm/page.h>
17
1da177e4 18#ifndef __ASSEMBLY__
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LT
19#include <asm/addrspace.h>
20#include <asm/fixmap.h>
1da177e4 21
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22/*
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
25 */
26ff6c11 26extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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27#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
28
29#endif /* !__ASSEMBLY__ */
30
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31/*
32 * Effective and physical address definitions, to aid with sign
33 * extension.
34 */
35#define NEFF 32
36#define NEFF_SIGN (1LL << (NEFF - 1))
37#define NEFF_MASK (-1LL << NEFF)
38
39#ifdef CONFIG_29BIT
40#define NPHYS 29
41#else
42#define NPHYS 32
43#endif
44
45#define NPHYS_SIGN (1LL << (NPHYS - 1))
46#define NPHYS_MASK (-1LL << NPHYS)
47
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48/*
49 * traditional two-level paging structure
50 */
51/* PTE bits */
55183e9b 52#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
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53# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
54#else
55# define PTE_MAGNITUDE 2 /* 32-bit PTEs */
56#endif
57#define PTE_SHIFT PAGE_SHIFT
58#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
59
60/* PGD bits */
61#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
db2e1fa3 62#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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63#define PGDIR_MASK (~(PGDIR_SIZE-1))
64
21440cf0 65/* Entries per level */
7a847f81 66#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
d04a0f79 67#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
21440cf0 68
1da177e4 69#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
d455a369 70#define FIRST_USER_ADDRESS 0
1da177e4 71
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72#ifdef CONFIG_32BIT
73#define PHYS_ADDR_MASK 0xffffffff
74#else
75#define PHYS_ADDR_MASK 0x1fffffff
76#endif
77
78#define PTE_PHYS_MASK (PHYS_ADDR_MASK & PAGE_MASK)
cb700aa4 79#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
1da177e4 80
0468b4bb 81#ifdef CONFIG_SUPERH32
f0b859e3 82#define VMALLOC_START (P3SEG)
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83#else
84#define VMALLOC_START (0xf0000000)
85#endif
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86#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
87
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88#if defined(CONFIG_SUPERH32)
89#include <asm/pgtable_32.h>
21440cf0 90#else
249cfea9 91#include <asm/pgtable_64.h>
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92#endif
93
94/*
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95 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
96 * protection for execute, and considers it the same as a read. Also, write
97 * permission implies read permission. This is the closest we can get..
98 *
99 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
100 * not only supporting separate execute, read, and write bits, but having
101 * completely separate permission bits for user and kernel space.
1da177e4 102 */
21440cf0 103 /*xwr*/
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104#define __P000 PAGE_NONE
105#define __P001 PAGE_READONLY
106#define __P010 PAGE_COPY
107#define __P011 PAGE_COPY
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108#define __P100 PAGE_EXECREAD
109#define __P101 PAGE_EXECREAD
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110#define __P110 PAGE_COPY
111#define __P111 PAGE_COPY
112
113#define __S000 PAGE_NONE
114#define __S001 PAGE_READONLY
21440cf0 115#define __S010 PAGE_WRITEONLY
1da177e4 116#define __S011 PAGE_SHARED
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117#define __S100 PAGE_EXECREAD
118#define __S101 PAGE_EXECREAD
119#define __S110 PAGE_RWX
120#define __S111 PAGE_RWX
1da177e4 121
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122typedef pte_t *pte_addr_t;
123
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124#define kern_addr_valid(addr) (1)
125
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126#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
127 remap_pfn_range(vma, vaddr, pfn, size, prot)
128
249cfea9 129#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
8c65b4a6 130
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131/*
132 * No page table caches to initialise
133 */
134#define pgtable_cache_init() do { } while (0)
135
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136struct vm_area_struct;
137extern void update_mmu_cache(struct vm_area_struct * vma,
138 unsigned long address, pte_t pte);
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139extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
140extern void paging_init(void);
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141extern void page_table_range_init(unsigned long start, unsigned long end,
142 pgd_t *pgd);
21440cf0 143
0dfae7d5 144#if defined(CONFIG_MMU) && !defined(CONFIG_CPU_SH5)
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145extern void kmap_coherent_init(void);
146#else
147#define kmap_coherent_init() do { } while (0)
148#endif
149
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150/* arch/sh/mm/mmap.c */
151#define HAVE_ARCH_UNMAPPED_AREA
152#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
153
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154#include <asm-generic/pgtable.h>
155
249cfea9 156#endif /* __ASM_SH_PGTABLE_H */