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1 | #ifndef __ASM_SH_SMC37C93X_H |
2 | #define __ASM_SH_SMC37C93X_H | |
3 | ||
4 | /* | |
5 | * linux/include/asm-sh/smc37c93x.h | |
6 | * | |
7 | * Copyright (C) 2000 Kazumoto Kojima | |
8 | * | |
9 | * SMSC 37C93x Super IO Chip support | |
10 | */ | |
11 | ||
12 | /* Default base I/O address */ | |
13 | #define FDC_PRIMARY_BASE 0x3f0 | |
14 | #define IDE1_PRIMARY_BASE 0x1f0 | |
15 | #define IDE1_SECONDARY_BASE 0x170 | |
16 | #define PARPORT_PRIMARY_BASE 0x378 | |
17 | #define COM1_PRIMARY_BASE 0x2f8 | |
18 | #define COM2_PRIMARY_BASE 0x3f8 | |
19 | #define RTC_PRIMARY_BASE 0x070 | |
20 | #define KBC_PRIMARY_BASE 0x060 | |
21 | #define AUXIO_PRIMARY_BASE 0x000 /* XXX */ | |
22 | ||
23 | /* Logical device number */ | |
24 | #define LDN_FDC 0 | |
25 | #define LDN_IDE1 1 | |
26 | #define LDN_IDE2 2 | |
27 | #define LDN_PARPORT 3 | |
28 | #define LDN_COM1 4 | |
29 | #define LDN_COM2 5 | |
30 | #define LDN_RTC 6 | |
31 | #define LDN_KBC 7 | |
32 | #define LDN_AUXIO 8 | |
33 | ||
34 | /* Configuration port and key */ | |
35 | #define CONFIG_PORT 0x3f0 | |
36 | #define INDEX_PORT CONFIG_PORT | |
37 | #define DATA_PORT 0x3f1 | |
38 | #define CONFIG_ENTER 0x55 | |
39 | #define CONFIG_EXIT 0xaa | |
40 | ||
41 | /* Configuration index */ | |
42 | #define CURRENT_LDN_INDEX 0x07 | |
43 | #define POWER_CONTROL_INDEX 0x22 | |
44 | #define ACTIVATE_INDEX 0x30 | |
45 | #define IO_BASE_HI_INDEX 0x60 | |
46 | #define IO_BASE_LO_INDEX 0x61 | |
47 | #define IRQ_SELECT_INDEX 0x70 | |
48 | #define DMA_SELECT_INDEX 0x74 | |
49 | ||
50 | #define GPIO46_INDEX 0xc6 | |
51 | #define GPIO47_INDEX 0xc7 | |
52 | ||
53 | /* UART stuff. Only for debugging. */ | |
54 | /* UART Register */ | |
55 | ||
56 | #define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ | |
57 | #define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ | |
58 | #define UART_IER 0x2 /* Interrupt Enable Register */ | |
59 | #define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ | |
60 | #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ | |
61 | #define UART_LCR 0x6 /* Line Control Register */ | |
62 | #define UART_MCR 0x8 /* MODEM Control Register */ | |
63 | #define UART_LSR 0xa /* Line Status Register */ | |
64 | #define UART_MSR 0xc /* MODEM Status Register */ | |
65 | #define UART_SCR 0xe /* Scratch Register */ | |
66 | #define UART_DLL 0x0 /* Divisor Latch (LS) */ | |
67 | #define UART_DLM 0x2 /* Divisor Latch (MS) */ | |
68 | ||
69 | #ifndef __ASSEMBLY__ | |
70 | typedef struct uart_reg { | |
71 | volatile __u16 rbr; | |
72 | volatile __u16 ier; | |
73 | volatile __u16 iir; | |
74 | volatile __u16 lcr; | |
75 | volatile __u16 mcr; | |
76 | volatile __u16 lsr; | |
77 | volatile __u16 msr; | |
78 | volatile __u16 scr; | |
79 | } uart_reg; | |
80 | #endif /* ! __ASSEMBLY__ */ | |
81 | ||
82 | /* Alias for Write Only Register */ | |
83 | ||
84 | #define thr rbr | |
85 | #define tcr iir | |
86 | ||
87 | /* Alias for Divisor Latch Register */ | |
88 | ||
89 | #define dll rbr | |
90 | #define dlm ier | |
91 | #define fcr iir | |
92 | ||
93 | /* Interrupt Enable Register */ | |
94 | ||
95 | #define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ | |
96 | #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ | |
97 | #define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ | |
98 | #define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ | |
99 | ||
100 | /* Interrupt Ident Register */ | |
101 | ||
102 | #define IIR_IP 0x0100 /* "0" if Interrupt Pending */ | |
103 | #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ | |
104 | #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ | |
105 | #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ | |
106 | #define IIR_FIFO 0xc000 /* FIFOs enabled */ | |
107 | ||
108 | /* FIFO Control Register */ | |
109 | ||
110 | #define FCR_FEN 0x0100 /* FIFO enable */ | |
111 | #define FCR_RFRES 0x0200 /* Receiver FIFO reset */ | |
112 | #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ | |
113 | #define FCR_DMA 0x0800 /* DMA mode select */ | |
114 | #define FCR_RTL 0x4000 /* Receiver triger (LSB) */ | |
115 | #define FCR_RTM 0x8000 /* Receiver triger (MSB) */ | |
116 | ||
117 | /* Line Control Register */ | |
118 | ||
119 | #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ | |
120 | #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ | |
121 | #define LCR_STB 0x0400 /* Number of Stop Bits */ | |
122 | #define LCR_PEN 0x0800 /* Parity Enable */ | |
123 | #define LCR_EPS 0x1000 /* Even Parity Select */ | |
124 | #define LCR_SP 0x2000 /* Stick Parity */ | |
125 | #define LCR_SB 0x4000 /* Set Break */ | |
126 | #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ | |
127 | ||
128 | /* MODEM Control Register */ | |
129 | ||
130 | #define MCR_DTR 0x0100 /* Data Terminal Ready */ | |
131 | #define MCR_RTS 0x0200 /* Request to Send */ | |
132 | #define MCR_OUT1 0x0400 /* Out 1 */ | |
133 | #define MCR_IRQEN 0x0800 /* IRQ Enable */ | |
134 | #define MCR_LOOP 0x1000 /* Loop */ | |
135 | ||
136 | /* Line Status Register */ | |
137 | ||
138 | #define LSR_DR 0x0100 /* Data Ready */ | |
139 | #define LSR_OE 0x0200 /* Overrun Error */ | |
140 | #define LSR_PE 0x0400 /* Parity Error */ | |
141 | #define LSR_FE 0x0800 /* Framing Error */ | |
142 | #define LSR_BI 0x1000 /* Break Interrupt */ | |
143 | #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ | |
144 | #define LSR_TEMT 0x4000 /* Transmitter Empty */ | |
145 | #define LSR_FIFOE 0x8000 /* Receiver FIFO error */ | |
146 | ||
147 | /* MODEM Status Register */ | |
148 | ||
149 | #define MSR_DCTS 0x0100 /* Delta Clear to Send */ | |
150 | #define MSR_DDSR 0x0200 /* Delta Data Set Ready */ | |
151 | #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ | |
152 | #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ | |
153 | #define MSR_CTS 0x1000 /* Clear to Send */ | |
154 | #define MSR_DSR 0x2000 /* Data Set Ready */ | |
155 | #define MSR_RI 0x4000 /* Ring Indicator */ | |
156 | #define MSR_DCD 0x8000 /* Data Carrier Detect */ | |
157 | ||
158 | /* Baud Rate Divisor */ | |
159 | ||
160 | #define UART_CLK (1843200) /* 1.8432 MHz */ | |
161 | #define UART_BAUD(x) (UART_CLK / (16 * (x))) | |
162 | ||
163 | /* RTC register definition */ | |
164 | #define RTC_SECONDS 0 | |
165 | #define RTC_SECONDS_ALARM 1 | |
166 | #define RTC_MINUTES 2 | |
167 | #define RTC_MINUTES_ALARM 3 | |
168 | #define RTC_HOURS 4 | |
169 | #define RTC_HOURS_ALARM 5 | |
170 | #define RTC_DAY_OF_WEEK 6 | |
171 | #define RTC_DAY_OF_MONTH 7 | |
172 | #define RTC_MONTH 8 | |
173 | #define RTC_YEAR 9 | |
174 | #define RTC_FREQ_SELECT 10 | |
175 | # define RTC_UIP 0x80 | |
176 | # define RTC_DIV_CTL 0x70 | |
177 | /* This RTC can work under 32.768KHz clock only. */ | |
178 | # define RTC_OSC_ENABLE 0x20 | |
179 | # define RTC_OSC_DISABLE 0x00 | |
180 | #define RTC_CONTROL 11 | |
181 | # define RTC_SET 0x80 | |
182 | # define RTC_PIE 0x40 | |
183 | # define RTC_AIE 0x20 | |
184 | # define RTC_UIE 0x10 | |
185 | # define RTC_SQWE 0x08 | |
186 | # define RTC_DM_BINARY 0x04 | |
187 | # define RTC_24H 0x02 | |
188 | # define RTC_DST_EN 0x01 | |
189 | ||
190 | #endif /* __ASM_SH_SMC37C93X_H */ |