[mirror_ubuntu-zesty-kernel.git] / arch / sh / include / cpu-sh3 / cpu / cache.h

/*
 * include/asm-sh/cpu-sh3/cache.h
 *
 * Copyright (C) 1999 Niibe Yutaka
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef __ASM_CPU_SH3_CACHE_H
#define __ASM_CPU_SH3_CACHE_H

#define L1_CACHE_SHIFT	4

#define SH_CACHE_VALID		1
#define SH_CACHE_UPDATED	2
#define SH_CACHE_COMBINED	4
#define SH_CACHE_ASSOC		8

#define SH_CCR		0xffffffec	/* Address of Cache Control Register */

#define CCR_CACHE_CE	0x01	/* Cache Enable */
#define CCR_CACHE_WT	0x02	/* Write-Through (for P0,U0,P3) (else writeback) */
#define CCR_CACHE_CB	0x04	/* Write-Back (for P1) (else writethrough) */
#define CCR_CACHE_CF	0x08	/* Cache Flush */
#define CCR_CACHE_ORA	0x20	/* RAM mode */

#define CACHE_OC_ADDRESS_ARRAY	0xf0000000
#define CACHE_PHYSADDR_MASK	0x1ffffc00

#define CCR_CACHE_ENABLE	CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE	CCR_CACHE_CF

#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
    defined(CONFIG_CPU_SUBTYPE_SH7721)
#define CCR3_REG	0xa40000b4
#define CCR_CACHE_16KB  0x00010000
#define CCR_CACHE_32KB	0x00020000
#endif

#endif /* __ASM_CPU_SH3_CACHE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-sh/cpu-sh3/cache.h
	3	*
	4	* Copyright (C) 1999 Niibe Yutaka
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#ifndef __ASM_CPU_SH3_CACHE_H
	11	#define __ASM_CPU_SH3_CACHE_H
	12
	13	#define L1_CACHE_SHIFT 4
	14
8d5fb297 PM	15	#define SH_CACHE_VALID 1
	16	#define SH_CACHE_UPDATED 2
	17	#define SH_CACHE_COMBINED 4
	18	#define SH_CACHE_ASSOC 8
	19
a5f6ea29	20	#define SH_CCR 0xffffffec /* Address of Cache Control Register */
1da177e4 LT	21
	22	#define CCR_CACHE_CE 0x01 /* Cache Enable */
	23	#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
	24	#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
	25	#define CCR_CACHE_CF 0x08 /* Cache Flush */
	26	#define CCR_CACHE_ORA 0x20 /* RAM mode */
	27
	28	#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
	29	#define CACHE_PHYSADDR_MASK 0x1ffffc00
	30
	31	#define CCR_CACHE_ENABLE CCR_CACHE_CE
	32	#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
	33
3ea6bc3d MB	34	#if defined(CONFIG_CPU_SUBTYPE_SH7705) \|\| \
3ea6bc3d MB	35	defined(CONFIG_CPU_SUBTYPE_SH7710) \|\| \
31a49c4b YS	36	defined(CONFIG_CPU_SUBTYPE_SH7720) \|\| \
31a49c4b YS	37	defined(CONFIG_CPU_SUBTYPE_SH7721)
cc645a02	38	#define CCR3_REG 0xa40000b4
1da177e4 LT	39	#define CCR_CACHE_16KB 0x00010000
	40	#define CCR_CACHE_32KB 0x00020000
	41	#endif
	42
1da177e4	43	#endif /* __ASM_CPU_SH3_CACHE_H */