projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * arch/sh/kernel/cpu/sh2/probe.c | |
| 3 | * | |
| 4 | * CPU Subtype Probing for SH-2. | |
| 5 | * | |
| 6 | * Copyright (C) 2002 Paul Mundt | |
| 7 | * | |
| 8 | * This file is subject to the terms and conditions of the GNU General Public | |
| 9 | * License. See the file "COPYING" in the main directory of this archive | |
| 10 | * for more details. | |
| 11 | */ | |
| 1da177e4 | 12 | #include <linux/init.h> |
| 5a846aba RF |
13 | #include <linux/of_fdt.h> |
| 14 | #include <linux/smp.h> | |
| 15 | #include <linux/io.h> | |
| 1da177e4 LT |
16 | #include <asm/processor.h> |
| 17 | #include <asm/cache.h> | |
| 18 | ||
| 5a846aba RF |
19 | #if defined(CONFIG_CPU_J2) |
| 20 | extern u32 __iomem *j2_ccr_base; | |
| 21 | static int __init scan_cache(unsigned long node, const char *uname, | |
| 22 | int depth, void *data) | |
| 23 | { | |
| 24 | if (!of_flat_dt_is_compatible(node, "jcore,cache")) | |
| 25 | return 0; | |
| 26 | ||
| 27 | j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node); | |
| 28 | ||
| 29 | return 1; | |
| 30 | } | |
| 31 | #endif | |
| 32 | ||
| 33 | void __ref cpu_probe(void) | |
| 1da177e4 | 34 | { |
| b9601c5e | 35 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) |
| cb7af21f PM |
36 | boot_cpu_data.type = CPU_SH7619; |
| 37 | boot_cpu_data.dcache.ways = 4; | |
| 38 | boot_cpu_data.dcache.way_incr = (1<<12); | |
| 39 | boot_cpu_data.dcache.sets = 256; | |
| 40 | boot_cpu_data.dcache.entry_shift = 4; | |
| 41 | boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; | |
| 42 | boot_cpu_data.dcache.flags = 0; | |
| 9d4436a6 | 43 | #endif |
| 5a846aba RF |
44 | |
| 45 | #if defined(CONFIG_CPU_J2) | |
| 35373d0e | 46 | #if defined(CONFIG_SMP) |
| 5a846aba | 47 | unsigned cpu = hard_smp_processor_id(); |
| 35373d0e RF |
48 | #else |
| 49 | unsigned cpu = 0; | |
| 50 | #endif | |
| 5a846aba RF |
51 | if (cpu == 0) of_scan_flat_dt(scan_cache, NULL); |
| 52 | if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu); | |
| 53 | if (cpu != 0) return; | |
| 54 | boot_cpu_data.type = CPU_J2; | |
| 55 | ||
| 56 | /* These defaults are appropriate for the original/current | |
| 57 | * J2 cache. Once there is a proper framework for getting cache | |
| 58 | * info from device tree, we should switch to that. */ | |
| 59 | boot_cpu_data.dcache.ways = 1; | |
| 60 | boot_cpu_data.dcache.sets = 256; | |
| 61 | boot_cpu_data.dcache.entry_shift = 5; | |
| 62 | boot_cpu_data.dcache.linesz = 32; | |
| 63 | boot_cpu_data.dcache.flags = 0; | |
| 834da197 RF |
64 | |
| 65 | boot_cpu_data.flags |= CPU_HAS_CAS_L; | |
| 5a846aba | 66 | #else |
| 1da177e4 LT |
67 | /* |
| 68 | * SH-2 doesn't have separate caches | |
| 69 | */ | |
| cb7af21f | 70 | boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; |
| 5a846aba | 71 | #endif |
| cb7af21f | 72 | boot_cpu_data.icache = boot_cpu_data.dcache; |
| e82da214 | 73 | boot_cpu_data.family = CPU_FAMILY_SH2; |
| 1da177e4 | 74 | } |