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Merge branch 'akpm' (patches from Andrew)
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47d11326 1// SPDX-License-Identifier: GPL-2.0
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2/*
3 * SH7619 Setup
4 *
5 * Copyright (C) 2006 Yoshinori Sato
5dece2bb 6 * Copyright (C) 2009 Paul Mundt
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7 */
8#include <linux/platform_device.h>
9#include <linux/init.h>
10#include <linux/serial.h>
96de1a8f 11#include <linux/serial_sci.h>
06a64f91 12#include <linux/sh_eth.h>
46a12f74 13#include <linux/sh_timer.h>
698aa99d 14#include <linux/io.h>
9d4436a6 15
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16enum {
17 UNUSED = 0,
18
19 /* interrupt sources */
20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
21 WDT, EDMAC, CMT0, CMT1,
5dece2bb 22 SCIF0, SCIF1, SCIF2,
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23 HIF_HIFI, HIF_HIFBI,
24 DMAC0, DMAC1, DMAC2, DMAC3,
25 SIOF,
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26};
27
28static struct intc_vect vectors[] __initdata = {
29 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
30 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
31 INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
32 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
33 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
34 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
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35 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
36 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
37 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
38 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
39 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
40 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
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41 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
42 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
43 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
44 INTC_IRQ(SIOF, 108),
45};
46
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47static struct intc_prio_reg prio_registers[] __initdata = {
48 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
49 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
50 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
51 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
52 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
53 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
54 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
55};
56
5dece2bb 57static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
7f3edee8 58 NULL, prio_registers, NULL);
0dc3fc04 59
632fd800 60static struct plat_sci_port scif0_platform_data = {
c3fa400b 61 .scscr = SCSCR_REIE,
632fd800 62 .type = PORT_SCIF,
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63};
64
65static struct resource scif0_resources[] = {
66 DEFINE_RES_MEM(0xf8400000, 0x100),
67 DEFINE_RES_IRQ(88),
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68};
69
70static struct platform_device scif0_device = {
71 .name = "sh-sci",
72 .id = 0,
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73 .resource = scif0_resources,
74 .num_resources = ARRAY_SIZE(scif0_resources),
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75 .dev = {
76 .platform_data = &scif0_platform_data,
77 },
78};
79
80static struct plat_sci_port scif1_platform_data = {
c3fa400b 81 .scscr = SCSCR_REIE,
632fd800 82 .type = PORT_SCIF,
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83};
84
85static struct resource scif1_resources[] = {
86 DEFINE_RES_MEM(0xf8410000, 0x100),
87 DEFINE_RES_IRQ(92),
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88};
89
90static struct platform_device scif1_device = {
91 .name = "sh-sci",
92 .id = 1,
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93 .resource = scif1_resources,
94 .num_resources = ARRAY_SIZE(scif1_resources),
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95 .dev = {
96 .platform_data = &scif1_platform_data,
97 },
98};
99
100static struct plat_sci_port scif2_platform_data = {
c3fa400b 101 .scscr = SCSCR_REIE,
632fd800 102 .type = PORT_SCIF,
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103};
104
105static struct resource scif2_resources[] = {
106 DEFINE_RES_MEM(0xf8420000, 0x100),
107 DEFINE_RES_IRQ(96),
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108};
109
110static struct platform_device scif2_device = {
9d4436a6 111 .name = "sh-sci",
632fd800 112 .id = 2,
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113 .resource = scif2_resources,
114 .num_resources = ARRAY_SIZE(scif2_resources),
9d4436a6 115 .dev = {
632fd800 116 .platform_data = &scif2_platform_data,
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117 },
118};
119
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120static struct sh_eth_plat_data eth_platform_data = {
121 .phy = 1,
0bf2bbd2 122 .phy_interface = PHY_INTERFACE_MODE_MII,
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123};
124
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125static struct resource eth_resources[] = {
126 [0] = {
127 .start = 0xfb000000,
06a64f91 128 .end = 0xfb0001c7,
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129 .flags = IORESOURCE_MEM,
130 },
131 [1] = {
132 .start = 85,
133 .end = 85,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device eth_device = {
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139 .name = "sh7619-ether",
140 .id = -1,
d88a3ea6 141 .dev = {
06a64f91 142 .platform_data = &eth_platform_data,
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143 },
144 .num_resources = ARRAY_SIZE(eth_resources),
145 .resource = eth_resources,
146};
147
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148static struct sh_timer_config cmt_platform_data = {
149 .channels_mask = 3,
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150};
151
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152static struct resource cmt_resources[] = {
153 DEFINE_RES_MEM(0xf84a0070, 0x10),
154 DEFINE_RES_IRQ(86),
155 DEFINE_RES_IRQ(87),
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156};
157
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158static struct platform_device cmt_device = {
159 .name = "sh-cmt-16",
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160 .id = 0,
161 .dev = {
9b17e48c 162 .platform_data = &cmt_platform_data,
698aa99d 163 },
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164 .resource = cmt_resources,
165 .num_resources = ARRAY_SIZE(cmt_resources),
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166};
167
9d4436a6 168static struct platform_device *sh7619_devices[] __initdata = {
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169 &scif0_device,
170 &scif1_device,
171 &scif2_device,
d88a3ea6 172 &eth_device,
9b17e48c 173 &cmt_device,
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174};
175
176static int __init sh7619_devices_setup(void)
177{
178 return platform_add_devices(sh7619_devices,
179 ARRAY_SIZE(sh7619_devices));
180}
ba9a6337 181arch_initcall(sh7619_devices_setup);
780a1568 182
90015c89 183void __init plat_irq_setup(void)
780a1568 184{
0dc3fc04 185 register_intc_controller(&intc_desc);
780a1568 186}
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187
188static struct platform_device *sh7619_early_devices[] __initdata = {
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189 &scif0_device,
190 &scif1_device,
191 &scif2_device,
9b17e48c 192 &cmt_device,
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193};
194
195#define STBCR3 0xf80a0000
196
197void __init plat_early_device_setup(void)
198{
199 /* enable CMT clock */
200 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
201
202 early_platform_add_devices(sh7619_early_devices,
203 ARRAY_SIZE(sh7619_early_devices));
204}