[mirror_ubuntu-jammy-kernel.git] / arch / sh / kernel / cpu / sh2a / setup-sh7201.c

/*
 *  SH7201 setup
 *
 *  Copyright (C) 2008  Peter Griffin pgriffin@mpc-data.co.uk
 *  Copyright (C) 2009  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_mtu2.h>
#include <linux/io.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,

	ADC_ADI,

	MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
	MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,

	RTC, WDT,

	IIC30, IIC31, IIC32,

	DMAC0_DMINT0, DMAC1_DMINT1,
	DMAC2_DMINT2, DMAC3_DMINT3,

	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,

	DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
	DMAC7_DMINT7,

	RCAN0, RCAN1,

	SSI0_SSII, SSI1_SSII,

	TMR0, TMR1,

	/* interrupt groups */
	PINT,
};

static struct intc_vect vectors[] __initdata = {
	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),

	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),

	INTC_IRQ(ADC_ADI, 92),

	INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
	INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),

	INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
	INTC_IRQ(MTU20_VEF, 114),

	INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
	INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),

	INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
	INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),

	INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
	INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),

	INTC_IRQ(MTU2_TCI3V, 136),

	INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
	INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),

	INTC_IRQ(MTU2_TCI4V, 144),

	INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
	INTC_IRQ(MTU25_UVW, 150),

	INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
	INTC_IRQ(RTC, 154),

	INTC_IRQ(WDT, 156),

	INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
	INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
	INTC_IRQ(IIC30, 161),

	INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
	INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
	INTC_IRQ(IIC31, 168),

	INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
	INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
	INTC_IRQ(IIC32, 174),

	INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
	INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),

	INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
	INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
	INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
	INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
	INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
	INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
	INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
	INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
	INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
	INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
	INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
	INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
	INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
	INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
	INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
	INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),

	INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
	INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
	INTC_IRQ(DMAC7_DMINT7, 219),

	INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
	INTC_IRQ(RCAN0, 230),
	INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),

	INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
	INTC_IRQ(RCAN1, 236),
	INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),

	INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),

	INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
	INTC_IRQ(TMR0, 248),

	INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
	INTC_IRQ(TMR1, 254),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
		   PINT4, PINT5, PINT6, PINT7),
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
	{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
	{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU,  MTU23_ABCD } },
	{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },

	{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
	{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
	{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
	{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
	{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4  } },
	{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
	{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
	{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfffe9408, 0, 16, /* PINTER */
	  { 0, 0, 0, 0, 0, 0, 0, 0,
	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
			 mask_registers, prio_registers, NULL);

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xfffe8000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 180, 180, 180, 180 }
	}, {
		.mapbase	= 0xfffe8800,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 184, 184, 184, 184 }
	}, {
		.mapbase	= 0xfffe9000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 188, 188, 188, 188 }
	}, {
		.mapbase	= 0xfffe9800,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 192, 192, 192, 192 }
	}, {
		.mapbase	= 0xfffea000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 196, 196, 196, 196 }
	}, {
		.mapbase	= 0xfffea800,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 200, 200, 200, 200 }
	}, {
		.mapbase	= 0xfffeb000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 204, 204, 204, 204 }
	}, {
		.mapbase	= 0xfffeb800,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 208, 208, 208, 208 }
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xffff0800,
		.end	= 0xffff2000 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Shared Period/Carry/Alarm IRQ */
		.start	= 152,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct sh_mtu2_config mtu2_0_platform_data = {
	.name = "MTU2_0",
	.channel_offset = -0x80,
	.timer_bit = 0,
	.clk = "module_clk",
	.clockevent_rating = 200,
};

static struct resource mtu2_0_resources[] = {
	[0] = {
		.name	= "MTU2_0",
		.start	= 0xfffe4300,
		.end	= 0xfffe4326,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 108,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_0_device = {
	.name		= "sh_mtu2",
	.id		= 0,
	.dev = {
		.platform_data	= &mtu2_0_platform_data,
	},
	.resource	= mtu2_0_resources,
	.num_resources	= ARRAY_SIZE(mtu2_0_resources),
};

static struct sh_mtu2_config mtu2_1_platform_data = {
	.name = "MTU2_1",
	.channel_offset = -0x100,
	.timer_bit = 1,
	.clk = "module_clk",
	.clockevent_rating = 200,
};

static struct resource mtu2_1_resources[] = {
	[0] = {
		.name	= "MTU2_1",
		.start	= 0xfffe4380,
		.end	= 0xfffe4390,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 116,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_1_device = {
	.name		= "sh_mtu2",
	.id		= 1,
	.dev = {
		.platform_data	= &mtu2_1_platform_data,
	},
	.resource	= mtu2_1_resources,
	.num_resources	= ARRAY_SIZE(mtu2_1_resources),
};

static struct sh_mtu2_config mtu2_2_platform_data = {
	.name = "MTU2_2",
	.channel_offset = 0x80,
	.timer_bit = 2,
	.clk = "module_clk",
	.clockevent_rating = 200,
};

static struct resource mtu2_2_resources[] = {
	[0] = {
		.name	= "MTU2_2",
		.start	= 0xfffe4000,
		.end	= 0xfffe400a,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 124,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_2_device = {
	.name		= "sh_mtu2",
	.id		= 2,
	.dev = {
		.platform_data	= &mtu2_2_platform_data,
	},
	.resource	= mtu2_2_resources,
	.num_resources	= ARRAY_SIZE(mtu2_2_resources),
};

static struct platform_device *sh7201_devices[] __initdata = {
	&sci_device,
	&rtc_device,
	&mtu2_0_device,
	&mtu2_1_device,
	&mtu2_2_device,
};

static int __init sh7201_devices_setup(void)
{
	return platform_add_devices(sh7201_devices,
				    ARRAY_SIZE(sh7201_devices));
}
__initcall(sh7201_devices_setup);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

static struct platform_device *sh7201_early_devices[] __initdata = {
	&mtu2_0_device,
	&mtu2_1_device,
	&mtu2_2_device,
};

#define STBCR3 0xfffe0408

void __init plat_early_device_setup(void)
{
	/* enable MTU2 clock */
	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

	early_platform_add_devices(sh7201_early_devices,
				   ARRAY_SIZE(sh7201_early_devices));
}
Commit	Line	Data
2825999e PG	1	/*
	2	* SH7201 setup
	3	*
	4	* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
d55eedd5	5	* Copyright (C) 2009 Paul Mundt
2825999e PG	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11	#include <linux/platform_device.h>
	12	#include <linux/init.h>
	13	#include <linux/serial.h>
	14	#include <linux/serial_sci.h>
da107c6e MD	15	#include <linux/sh_mtu2.h>
da107c6e MD	16	#include <linux/io.h>
2825999e PG	17
	18	enum {
	19	UNUSED = 0,
	20
	21	/* interrupt sources */
	22	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	23	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
d55eedd5	24
2825999e	25	ADC_ADI,
d55eedd5 PM	26
	27	MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
	28	MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
	29
	30	RTC, WDT,
	31
	32	IIC30, IIC31, IIC32,
2825999e PG	33
	34	DMAC0_DMINT0, DMAC1_DMINT1,
	35	DMAC2_DMINT2, DMAC3_DMINT3,
	36
d55eedd5	37	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
2825999e PG	38
	39	DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
	40	DMAC7_DMINT7,
	41
d55eedd5	42	RCAN0, RCAN1,
2825999e PG	43
	44	SSI0_SSII, SSI1_SSII,
	45
d55eedd5	46	TMR0, TMR1,
2825999e PG	47
2825999e PG	48	/* interrupt groups */
d55eedd5	49	PINT,
2825999e PG	50	};
	51
	52	static struct intc_vect vectors[] __initdata = {
	53	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	54	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	55	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	56	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
d55eedd5	57
2825999e PG	58	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	59	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	60	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	61	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
	62
	63	INTC_IRQ(ADC_ADI, 92),
	64
d55eedd5 PM	65	INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
	66	INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
	67
	68	INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
	69	INTC_IRQ(MTU20_VEF, 114),
	70
	71	INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
	72	INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
2825999e	73
d55eedd5 PM	74	INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
d55eedd5 PM	75	INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
2825999e	76
d55eedd5 PM	77	INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
d55eedd5 PM	78	INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
2825999e	79
2825999e PG	80	INTC_IRQ(MTU2_TCI3V, 136),
2825999e PG	81
d55eedd5 PM	82	INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
	83	INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
	84
2825999e PG	85	INTC_IRQ(MTU2_TCI4V, 144),
2825999e PG	86
d55eedd5 PM	87	INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
	88	INTC_IRQ(MTU25_UVW, 150),
	89
	90	INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
	91	INTC_IRQ(RTC, 154),
2825999e	92
d55eedd5	93	INTC_IRQ(WDT, 156),
2825999e	94
d55eedd5 PM	95	INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
	96	INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
	97	INTC_IRQ(IIC30, 161),
2825999e	98
d55eedd5 PM	99	INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
	100	INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
	101	INTC_IRQ(IIC31, 168),
2825999e	102
d55eedd5 PM	103	INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
	104	INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
	105	INTC_IRQ(IIC32, 174),
2825999e PG	106
	107	INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
	108	INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
	109
d55eedd5 PM	110	INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
	111	INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
	112	INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
	113	INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
	114	INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
	115	INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
	116	INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
	117	INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
	118	INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
	119	INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
	120	INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
	121	INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
	122	INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
	123	INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
	124	INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
	125	INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
2825999e PG	126
	127	INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
	128	INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
	129	INTC_IRQ(DMAC7_DMINT7, 219),
	130
d55eedd5 PM	131	INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
	132	INTC_IRQ(RCAN0, 230),
	133	INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
2825999e	134
d55eedd5 PM	135	INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
	136	INTC_IRQ(RCAN1, 236),
	137	INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
2825999e PG	138
	139	INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
	140
d55eedd5 PM	141	INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
d55eedd5 PM	142	INTC_IRQ(TMR0, 248),
2825999e	143
d55eedd5 PM	144	INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
d55eedd5 PM	145	INTC_IRQ(TMR1, 254),
2825999e PG	146	};
	147
	148	static struct intc_group groups[] __initdata = {
	149	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
	150	PINT4, PINT5, PINT6, PINT7),
2825999e PG	151	};
	152
	153	static struct intc_prio_reg prio_registers[] __initdata = {
	154	{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	155	{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	156	{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
	157	{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
	158	{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
	159	{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
	160
	161	{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
	162	{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
d55eedd5	163	{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
2825999e PG	164	{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
	165	{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
	166	{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
	167	{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
	168	{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
	169	};
	170
	171	static struct intc_mask_reg mask_registers[] __initdata = {
	172	{ 0xfffe9408, 0, 16, /* PINTER */
	173	{ 0, 0, 0, 0, 0, 0, 0, 0,
	174	PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
	175	};
	176
	177	static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
	178	mask_registers, prio_registers, NULL);
	179
	180	static struct plat_sci_port sci_platform_data[] = {
	181	{
	182	.mapbase = 0xfffe8000,
	183	.flags = UPF_BOOT_AUTOCONF,
	184	.type = PORT_SCIF,
d55eedd5	185	.irqs = { 180, 180, 180, 180 }
2825999e PG	186	}, {
	187	.mapbase = 0xfffe8800,
	188	.flags = UPF_BOOT_AUTOCONF,
	189	.type = PORT_SCIF,
d55eedd5	190	.irqs = { 184, 184, 184, 184 }
2825999e PG	191	}, {
	192	.mapbase = 0xfffe9000,
	193	.flags = UPF_BOOT_AUTOCONF,
	194	.type = PORT_SCIF,
d55eedd5	195	.irqs = { 188, 188, 188, 188 }
2825999e PG	196	}, {
	197	.mapbase = 0xfffe9800,
	198	.flags = UPF_BOOT_AUTOCONF,
	199	.type = PORT_SCIF,
d55eedd5	200	.irqs = { 192, 192, 192, 192 }
2825999e PG	201	}, {
	202	.mapbase = 0xfffea000,
	203	.flags = UPF_BOOT_AUTOCONF,
	204	.type = PORT_SCIF,
d55eedd5	205	.irqs = { 196, 196, 196, 196 }
2825999e PG	206	}, {
	207	.mapbase = 0xfffea800,
	208	.flags = UPF_BOOT_AUTOCONF,
	209	.type = PORT_SCIF,
d55eedd5	210	.irqs = { 200, 200, 200, 200 }
2825999e PG	211	}, {
	212	.mapbase = 0xfffeb000,
	213	.flags = UPF_BOOT_AUTOCONF,
	214	.type = PORT_SCIF,
d55eedd5	215	.irqs = { 204, 204, 204, 204 }
2825999e PG	216	}, {
	217	.mapbase = 0xfffeb800,
	218	.flags = UPF_BOOT_AUTOCONF,
	219	.type = PORT_SCIF,
d55eedd5	220	.irqs = { 208, 208, 208, 208 }
2825999e PG	221	}, {
	222	.flags = 0,
	223	}
	224	};
	225
	226	static struct platform_device sci_device = {
	227	.name = "sh-sci",
	228	.id = -1,
	229	.dev = {
	230	.platform_data = sci_platform_data,
	231	},
	232	};
	233
	234	static struct resource rtc_resources[] = {
	235	[0] = {
	236	.start = 0xffff0800,
	237	.end = 0xffff2000 + 0x58 - 1,
	238	.flags = IORESOURCE_IO,
	239	},
	240	[1] = {
d55eedd5	241	/* Shared Period/Carry/Alarm IRQ */
2825999e PG	242	.start = 152,
	243	.flags = IORESOURCE_IRQ,
	244	},
	245	};
	246
	247	static struct platform_device rtc_device = {
	248	.name = "sh-rtc",
	249	.id = -1,
	250	.num_resources = ARRAY_SIZE(rtc_resources),
	251	.resource = rtc_resources,
	252	};
	253
da107c6e MD	254	static struct sh_mtu2_config mtu2_0_platform_data = {
	255	.name = "MTU2_0",
	256	.channel_offset = -0x80,
	257	.timer_bit = 0,
	258	.clk = "module_clk",
	259	.clockevent_rating = 200,
	260	};
	261
	262	static struct resource mtu2_0_resources[] = {
	263	[0] = {
	264	.name = "MTU2_0",
	265	.start = 0xfffe4300,
	266	.end = 0xfffe4326,
	267	.flags = IORESOURCE_MEM,
	268	},
	269	[1] = {
	270	.start = 108,
	271	.flags = IORESOURCE_IRQ,
	272	},
	273	};
	274
	275	static struct platform_device mtu2_0_device = {
	276	.name = "sh_mtu2",
	277	.id = 0,
	278	.dev = {
	279	.platform_data = &mtu2_0_platform_data,
	280	},
	281	.resource = mtu2_0_resources,
	282	.num_resources = ARRAY_SIZE(mtu2_0_resources),
	283	};
	284
	285	static struct sh_mtu2_config mtu2_1_platform_data = {
	286	.name = "MTU2_1",
	287	.channel_offset = -0x100,
	288	.timer_bit = 1,
	289	.clk = "module_clk",
	290	.clockevent_rating = 200,
	291	};
	292
	293	static struct resource mtu2_1_resources[] = {
	294	[0] = {
	295	.name = "MTU2_1",
	296	.start = 0xfffe4380,
	297	.end = 0xfffe4390,
	298	.flags = IORESOURCE_MEM,
	299	},
	300	[1] = {
	301	.start = 116,
	302	.flags = IORESOURCE_IRQ,
	303	},
	304	};
	305
	306	static struct platform_device mtu2_1_device = {
	307	.name = "sh_mtu2",
	308	.id = 1,
	309	.dev = {
	310	.platform_data = &mtu2_1_platform_data,
	311	},
	312	.resource = mtu2_1_resources,
	313	.num_resources = ARRAY_SIZE(mtu2_1_resources),
	314	};
	315
	316	static struct sh_mtu2_config mtu2_2_platform_data = {
	317	.name = "MTU2_2",
318	.channel_offset = 0x80,
319	.timer_bit = 2,
320	.clk = "module_clk",
321	.clockevent_rating = 200,
322	};
323
324	static struct resource mtu2_2_resources[] = {
325	[0] = {
326	.name = "MTU2_2",
327	.start = 0xfffe4000,
328	.end = 0xfffe400a,
329	.flags = IORESOURCE_MEM,
330	},
331	[1] = {
332	.start = 124,
333	.flags = IORESOURCE_IRQ,
334	},
335	};
336
337	static struct platform_device mtu2_2_device = {
338	.name = "sh_mtu2",
339	.id = 2,
340	.dev = {
341	.platform_data = &mtu2_2_platform_data,
342	},
343	.resource = mtu2_2_resources,
344	.num_resources = ARRAY_SIZE(mtu2_2_resources),
345	};
346
2825999e PG	347	static struct platform_device *sh7201_devices[] __initdata = {
	348	&sci_device,
	349	&rtc_device,
da107c6e MD	350	&mtu2_0_device,
	351	&mtu2_1_device,
	352	&mtu2_2_device,
2825999e PG	353	};
	354
	355	static int __init sh7201_devices_setup(void)
	356	{
	357	return platform_add_devices(sh7201_devices,
	358	ARRAY_SIZE(sh7201_devices));
	359	}
	360	__initcall(sh7201_devices_setup);
	361
	362	void __init plat_irq_setup(void)
	363	{
	364	register_intc_controller(&intc_desc);
	365	}
da107c6e MD	366
	367	static struct platform_device *sh7201_early_devices[] __initdata = {
	368	&mtu2_0_device,
	369	&mtu2_1_device,
	370	&mtu2_2_device,
	371	};
	372
	373	#define STBCR3 0xfffe0408
	374
	375	void __init plat_early_device_setup(void)
	376	{
	377	/* enable MTU2 clock */
	378	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
	379
	380	early_platform_add_devices(sh7201_early_devices,
	381	ARRAY_SIZE(sh7201_early_devices));
	382	}