[mirror_ubuntu-jammy-kernel.git] / arch / sh / kernel / cpu / sh2a / setup-sh7201.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  SH7201 setup
 *
 *  Copyright (C) 2008  Peter Griffin pgriffin@mpc-data.co.uk
 *  Copyright (C) 2009  Paul Mundt
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <linux/io.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,

	ADC_ADI,

	MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
	MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,

	RTC, WDT,

	IIC30, IIC31, IIC32,

	DMAC0_DMINT0, DMAC1_DMINT1,
	DMAC2_DMINT2, DMAC3_DMINT3,

	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,

	DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
	DMAC7_DMINT7,

	RCAN0, RCAN1,

	SSI0_SSII, SSI1_SSII,

	TMR0, TMR1,

	/* interrupt groups */
	PINT,
};

static struct intc_vect vectors[] __initdata = {
	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),

	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),

	INTC_IRQ(ADC_ADI, 92),

	INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
	INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),

	INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
	INTC_IRQ(MTU20_VEF, 114),

	INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
	INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),

	INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
	INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),

	INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
	INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),

	INTC_IRQ(MTU2_TCI3V, 136),

	INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
	INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),

	INTC_IRQ(MTU2_TCI4V, 144),

	INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
	INTC_IRQ(MTU25_UVW, 150),

	INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
	INTC_IRQ(RTC, 154),

	INTC_IRQ(WDT, 156),

	INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
	INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
	INTC_IRQ(IIC30, 161),

	INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
	INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
	INTC_IRQ(IIC31, 168),

	INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
	INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
	INTC_IRQ(IIC32, 174),

	INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
	INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),

	INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
	INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
	INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
	INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
	INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
	INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
	INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
	INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
	INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
	INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
	INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
	INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
	INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
	INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
	INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
	INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),

	INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
	INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
	INTC_IRQ(DMAC7_DMINT7, 219),

	INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
	INTC_IRQ(RCAN0, 230),
	INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),

	INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
	INTC_IRQ(RCAN1, 236),
	INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),

	INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),

	INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
	INTC_IRQ(TMR0, 248),

	INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
	INTC_IRQ(TMR1, 254),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
		   PINT4, PINT5, PINT6, PINT7),
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
	{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
	{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU,  MTU23_ABCD } },
	{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },

	{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
	{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
	{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
	{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
	{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4  } },
	{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
	{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
	{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfffe9408, 0, 16, /* PINTER */
	  { 0, 0, 0, 0, 0, 0, 0, 0,
	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
			 mask_registers, prio_registers, NULL);

static struct plat_sci_port scif0_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif0_resources[] = {
	DEFINE_RES_MEM(0xfffe8000, 0x100),
	DEFINE_RES_IRQ(180),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.resource	= scif0_resources,
	.num_resources	= ARRAY_SIZE(scif0_resources),
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif1_resources[] = {
	DEFINE_RES_MEM(0xfffe8800, 0x100),
	DEFINE_RES_IRQ(184),
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.resource	= scif1_resources,
	.num_resources	= ARRAY_SIZE(scif1_resources),
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif2_resources[] = {
	DEFINE_RES_MEM(0xfffe9000, 0x100),
	DEFINE_RES_IRQ(188),
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.resource	= scif2_resources,
	.num_resources	= ARRAY_SIZE(scif2_resources),
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif3_resources[] = {
	DEFINE_RES_MEM(0xfffe9800, 0x100),
	DEFINE_RES_IRQ(192),
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.resource	= scif3_resources,
	.num_resources	= ARRAY_SIZE(scif3_resources),
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct plat_sci_port scif4_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif4_resources[] = {
	DEFINE_RES_MEM(0xfffea000, 0x100),
	DEFINE_RES_IRQ(196),
};

static struct platform_device scif4_device = {
	.name		= "sh-sci",
	.id		= 4,
	.resource	= scif4_resources,
	.num_resources	= ARRAY_SIZE(scif4_resources),
	.dev		= {
		.platform_data	= &scif4_platform_data,
	},
};

static struct plat_sci_port scif5_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif5_resources[] = {
	DEFINE_RES_MEM(0xfffea800, 0x100),
	DEFINE_RES_IRQ(200),
};

static struct platform_device scif5_device = {
	.name		= "sh-sci",
	.id		= 5,
	.resource	= scif5_resources,
	.num_resources	= ARRAY_SIZE(scif5_resources),
	.dev		= {
		.platform_data	= &scif5_platform_data,
	},
};

static struct plat_sci_port scif6_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif6_resources[] = {
	DEFINE_RES_MEM(0xfffeb000, 0x100),
	DEFINE_RES_IRQ(204),
};

static struct platform_device scif6_device = {
	.name		= "sh-sci",
	.id		= 6,
	.resource	= scif6_resources,
	.num_resources	= ARRAY_SIZE(scif6_resources),
	.dev		= {
		.platform_data	= &scif6_platform_data,
	},
};

static struct plat_sci_port scif7_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif7_resources[] = {
	DEFINE_RES_MEM(0xfffeb800, 0x100),
	DEFINE_RES_IRQ(208),
};

static struct platform_device scif7_device = {
	.name		= "sh-sci",
	.id		= 7,
	.resource	= scif7_resources,
	.num_resources	= ARRAY_SIZE(scif7_resources),
	.dev		= {
		.platform_data	= &scif7_platform_data,
	},
};

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xffff0800,
		.end	= 0xffff2000 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Shared Period/Carry/Alarm IRQ */
		.start	= 152,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct resource mtu2_resources[] = {
	DEFINE_RES_MEM(0xfffe4000, 0x400),
	DEFINE_RES_IRQ_NAMED(108, "tgi0a"),
	DEFINE_RES_IRQ_NAMED(116, "tgi1a"),
	DEFINE_RES_IRQ_NAMED(124, "tgi1b"),
};

static struct platform_device mtu2_device = {
	.name		= "sh-mtu2",
	.id		= -1,
	.resource	= mtu2_resources,
	.num_resources	= ARRAY_SIZE(mtu2_resources),
};

static struct platform_device *sh7201_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&scif6_device,
	&scif7_device,
	&rtc_device,
	&mtu2_device,
};

static int __init sh7201_devices_setup(void)
{
	return platform_add_devices(sh7201_devices,
				    ARRAY_SIZE(sh7201_devices));
}
arch_initcall(sh7201_devices_setup);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

static struct platform_device *sh7201_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&scif6_device,
	&scif7_device,
	&mtu2_device,
};

#define STBCR3 0xfffe0408

void __init plat_early_device_setup(void)
{
	/* enable MTU2 clock */
	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

	early_platform_add_devices(sh7201_early_devices,
				   ARRAY_SIZE(sh7201_early_devices));
}
Commit	Line	Data
234a0538	1	// SPDX-License-Identifier: GPL-2.0
2825999e PG	2	/*
	3	* SH7201 setup
	4	*
	5	* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
d55eedd5	6	* Copyright (C) 2009 Paul Mundt
2825999e PG	7	*/
	8	#include <linux/platform_device.h>
	9	#include <linux/init.h>
	10	#include <linux/serial.h>
	11	#include <linux/serial_sci.h>
46a12f74	12	#include <linux/sh_timer.h>
da107c6e	13	#include <linux/io.h>
2825999e PG	14
	15	enum {
	16	UNUSED = 0,
	17
	18	/* interrupt sources */
	19	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	20	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
d55eedd5	21
2825999e	22	ADC_ADI,
d55eedd5 PM	23
	24	MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
	25	MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
	26
	27	RTC, WDT,
	28
	29	IIC30, IIC31, IIC32,
2825999e PG	30
	31	DMAC0_DMINT0, DMAC1_DMINT1,
	32	DMAC2_DMINT2, DMAC3_DMINT3,
	33
d55eedd5	34	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
2825999e PG	35
	36	DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
	37	DMAC7_DMINT7,
	38
d55eedd5	39	RCAN0, RCAN1,
2825999e PG	40
	41	SSI0_SSII, SSI1_SSII,
	42
d55eedd5	43	TMR0, TMR1,
2825999e PG	44
2825999e PG	45	/* interrupt groups */
d55eedd5	46	PINT,
2825999e PG	47	};
	48
	49	static struct intc_vect vectors[] __initdata = {
	50	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	51	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	52	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	53	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
d55eedd5	54
2825999e PG	55	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	56	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	57	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	58	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
	59
	60	INTC_IRQ(ADC_ADI, 92),
	61
d55eedd5 PM	62	INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
	63	INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
	64
	65	INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
	66	INTC_IRQ(MTU20_VEF, 114),
	67
	68	INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
	69	INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
2825999e	70
d55eedd5 PM	71	INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
d55eedd5 PM	72	INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
2825999e	73
d55eedd5 PM	74	INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
d55eedd5 PM	75	INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
2825999e	76
2825999e PG	77	INTC_IRQ(MTU2_TCI3V, 136),
2825999e PG	78
d55eedd5 PM	79	INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
	80	INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
	81
2825999e PG	82	INTC_IRQ(MTU2_TCI4V, 144),
2825999e PG	83
d55eedd5 PM	84	INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
	85	INTC_IRQ(MTU25_UVW, 150),
	86
	87	INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
	88	INTC_IRQ(RTC, 154),
2825999e	89
d55eedd5	90	INTC_IRQ(WDT, 156),
2825999e	91
d55eedd5 PM	92	INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
	93	INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
	94	INTC_IRQ(IIC30, 161),
2825999e	95
d55eedd5 PM	96	INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
	97	INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
	98	INTC_IRQ(IIC31, 168),
2825999e	99
d55eedd5 PM	100	INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
	101	INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
	102	INTC_IRQ(IIC32, 174),
2825999e PG	103
	104	INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
	105	INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
	106
d55eedd5 PM	107	INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
	108	INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
	109	INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
	110	INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
	111	INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
	112	INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
	113	INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
	114	INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
	115	INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
	116	INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
	117	INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
	118	INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
	119	INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
	120	INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
	121	INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
	122	INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
2825999e PG	123
	124	INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
	125	INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
	126	INTC_IRQ(DMAC7_DMINT7, 219),
	127
d55eedd5 PM	128	INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
	129	INTC_IRQ(RCAN0, 230),
	130	INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
2825999e	131
d55eedd5 PM	132	INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
	133	INTC_IRQ(RCAN1, 236),
	134	INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
2825999e PG	135
	136	INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
	137
d55eedd5 PM	138	INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
d55eedd5 PM	139	INTC_IRQ(TMR0, 248),
2825999e	140
d55eedd5 PM	141	INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
d55eedd5 PM	142	INTC_IRQ(TMR1, 254),
2825999e PG	143	};
	144
	145	static struct intc_group groups[] __initdata = {
	146	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
	147	PINT4, PINT5, PINT6, PINT7),
2825999e PG	148	};
	149
	150	static struct intc_prio_reg prio_registers[] __initdata = {
	151	{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	152	{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	153	{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
	154	{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
	155	{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
	156	{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
	157
	158	{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
	159	{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
d55eedd5	160	{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
2825999e PG	161	{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
	162	{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
	163	{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
	164	{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
	165	{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
	166	};
	167
	168	static struct intc_mask_reg mask_registers[] __initdata = {
	169	{ 0xfffe9408, 0, 16, /* PINTER */
	170	{ 0, 0, 0, 0, 0, 0, 0, 0,
	171	PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
	172	};
	173
	174	static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
	175	mask_registers, prio_registers, NULL);
	176
be091d20	177	static struct plat_sci_port scif0_platform_data = {
c3fa400b	178	.scscr = SCSCR_REIE,
be091d20	179	.type = PORT_SCIF,
d850acf9 LP	180	};
	181
	182	static struct resource scif0_resources[] = {
	183	DEFINE_RES_MEM(0xfffe8000, 0x100),
	184	DEFINE_RES_IRQ(180),
be091d20 MD	185	};
	186
	187	static struct platform_device scif0_device = {
2825999e	188	.name = "sh-sci",
be091d20	189	.id = 0,
d850acf9 LP	190	.resource = scif0_resources,
d850acf9 LP	191	.num_resources = ARRAY_SIZE(scif0_resources),
be091d20 MD	192	.dev = {
	193	.platform_data = &scif0_platform_data,
	194	},
	195	};
	196
	197	static struct plat_sci_port scif1_platform_data = {
c3fa400b	198	.scscr = SCSCR_REIE,
be091d20	199	.type = PORT_SCIF,
d850acf9 LP	200	};
	201
	202	static struct resource scif1_resources[] = {
	203	DEFINE_RES_MEM(0xfffe8800, 0x100),
	204	DEFINE_RES_IRQ(184),
be091d20 MD	205	};
	206
	207	static struct platform_device scif1_device = {
	208	.name = "sh-sci",
	209	.id = 1,
d850acf9 LP	210	.resource = scif1_resources,
d850acf9 LP	211	.num_resources = ARRAY_SIZE(scif1_resources),
be091d20 MD	212	.dev = {
	213	.platform_data = &scif1_platform_data,
	214	},
	215	};
	216
	217	static struct plat_sci_port scif2_platform_data = {
c3fa400b	218	.scscr = SCSCR_REIE,
be091d20	219	.type = PORT_SCIF,
d850acf9 LP	220	};
	221
	222	static struct resource scif2_resources[] = {
	223	DEFINE_RES_MEM(0xfffe9000, 0x100),
	224	DEFINE_RES_IRQ(188),
be091d20 MD	225	};
	226
	227	static struct platform_device scif2_device = {
	228	.name = "sh-sci",
	229	.id = 2,
d850acf9 LP	230	.resource = scif2_resources,
d850acf9 LP	231	.num_resources = ARRAY_SIZE(scif2_resources),
be091d20 MD	232	.dev = {
	233	.platform_data = &scif2_platform_data,
	234	},
	235	};
	236
	237	static struct plat_sci_port scif3_platform_data = {
c3fa400b	238	.scscr = SCSCR_REIE,
be091d20	239	.type = PORT_SCIF,
d850acf9 LP	240	};
	241
	242	static struct resource scif3_resources[] = {
	243	DEFINE_RES_MEM(0xfffe9800, 0x100),
	244	DEFINE_RES_IRQ(192),
be091d20 MD	245	};
	246
	247	static struct platform_device scif3_device = {
	248	.name = "sh-sci",
	249	.id = 3,
d850acf9 LP	250	.resource = scif3_resources,
d850acf9 LP	251	.num_resources = ARRAY_SIZE(scif3_resources),
be091d20 MD	252	.dev = {
	253	.platform_data = &scif3_platform_data,
	254	},
	255	};
	256
	257	static struct plat_sci_port scif4_platform_data = {
c3fa400b	258	.scscr = SCSCR_REIE,
be091d20	259	.type = PORT_SCIF,
d850acf9 LP	260	};
	261
	262	static struct resource scif4_resources[] = {
	263	DEFINE_RES_MEM(0xfffea000, 0x100),
	264	DEFINE_RES_IRQ(196),
be091d20 MD	265	};
	266
	267	static struct platform_device scif4_device = {
	268	.name = "sh-sci",
	269	.id = 4,
d850acf9 LP	270	.resource = scif4_resources,
d850acf9 LP	271	.num_resources = ARRAY_SIZE(scif4_resources),
be091d20 MD	272	.dev = {
	273	.platform_data = &scif4_platform_data,
	274	},
	275	};
	276
	277	static struct plat_sci_port scif5_platform_data = {
c3fa400b	278	.scscr = SCSCR_REIE,
be091d20	279	.type = PORT_SCIF,
d850acf9 LP	280	};
	281
	282	static struct resource scif5_resources[] = {
	283	DEFINE_RES_MEM(0xfffea800, 0x100),
	284	DEFINE_RES_IRQ(200),
be091d20 MD	285	};
	286
	287	static struct platform_device scif5_device = {
	288	.name = "sh-sci",
	289	.id = 5,
d850acf9 LP	290	.resource = scif5_resources,
d850acf9 LP	291	.num_resources = ARRAY_SIZE(scif5_resources),
be091d20 MD	292	.dev = {
	293	.platform_data = &scif5_platform_data,
	294	},
	295	};
	296
	297	static struct plat_sci_port scif6_platform_data = {
c3fa400b	298	.scscr = SCSCR_REIE,
be091d20	299	.type = PORT_SCIF,
d850acf9 LP	300	};
	301
	302	static struct resource scif6_resources[] = {
	303	DEFINE_RES_MEM(0xfffeb000, 0x100),
	304	DEFINE_RES_IRQ(204),
be091d20 MD	305	};
	306
	307	static struct platform_device scif6_device = {
	308	.name = "sh-sci",
	309	.id = 6,
d850acf9 LP	310	.resource = scif6_resources,
d850acf9 LP	311	.num_resources = ARRAY_SIZE(scif6_resources),
be091d20 MD	312	.dev = {
	313	.platform_data = &scif6_platform_data,
	314	},
	315	};
	316
	317	static struct plat_sci_port scif7_platform_data = {
c3fa400b	318	.scscr = SCSCR_REIE,
be091d20	319	.type = PORT_SCIF,
d850acf9 LP	320	};
	321
	322	static struct resource scif7_resources[] = {
	323	DEFINE_RES_MEM(0xfffeb800, 0x100),
	324	DEFINE_RES_IRQ(208),
be091d20 MD	325	};
	326
	327	static struct platform_device scif7_device = {
	328	.name = "sh-sci",
	329	.id = 7,
d850acf9 LP	330	.resource = scif7_resources,
d850acf9 LP	331	.num_resources = ARRAY_SIZE(scif7_resources),
2825999e	332	.dev = {
be091d20	333	.platform_data = &scif7_platform_data,
2825999e PG	334	},
	335	};
	336
	337	static struct resource rtc_resources[] = {
	338	[0] = {
	339	.start = 0xffff0800,
	340	.end = 0xffff2000 + 0x58 - 1,
	341	.flags = IORESOURCE_IO,
	342	},
	343	[1] = {
d55eedd5	344	/* Shared Period/Carry/Alarm IRQ */
2825999e PG	345	.start = 152,
	346	.flags = IORESOURCE_IRQ,
	347	},
	348	};
	349
	350	static struct platform_device rtc_device = {
	351	.name = "sh-rtc",
	352	.id = -1,
	353	.num_resources = ARRAY_SIZE(rtc_resources),
	354	.resource = rtc_resources,
	355	};
	356
5204601c LP	357	static struct resource mtu2_resources[] = {
	358	DEFINE_RES_MEM(0xfffe4000, 0x400),
	359	DEFINE_RES_IRQ_NAMED(108, "tgi0a"),
	360	DEFINE_RES_IRQ_NAMED(116, "tgi1a"),
	361	DEFINE_RES_IRQ_NAMED(124, "tgi1b"),
da107c6e MD	362	};
da107c6e MD	363
5204601c LP	364	static struct platform_device mtu2_device = {
	365	.name = "sh-mtu2",
	366	.id = -1,
	367	.resource = mtu2_resources,
	368	.num_resources = ARRAY_SIZE(mtu2_resources),
da107c6e MD	369	};
da107c6e MD	370
2825999e	371	static struct platform_device *sh7201_devices[] __initdata = {
be091d20 MD	372	&scif0_device,
	373	&scif1_device,
	374	&scif2_device,
	375	&scif3_device,
	376	&scif4_device,
	377	&scif5_device,
	378	&scif6_device,
	379	&scif7_device,
2825999e	380	&rtc_device,
5204601c	381	&mtu2_device,
2825999e PG	382	};
	383
	384	static int __init sh7201_devices_setup(void)
	385	{
	386	return platform_add_devices(sh7201_devices,
	387	ARRAY_SIZE(sh7201_devices));
	388	}
ba9a6337	389	arch_initcall(sh7201_devices_setup);
2825999e PG	390
	391	void __init plat_irq_setup(void)
	392	{
	393	register_intc_controller(&intc_desc);
	394	}
da107c6e MD	395
da107c6e MD	396	static struct platform_device *sh7201_early_devices[] __initdata = {
be091d20 MD	397	&scif0_device,
	398	&scif1_device,
	399	&scif2_device,
	400	&scif3_device,
	401	&scif4_device,
	402	&scif5_device,
	403	&scif6_device,
	404	&scif7_device,
5204601c	405	&mtu2_device,
da107c6e MD	406	};
	407
	408	#define STBCR3 0xfffe0408
	409
	410	void __init plat_early_device_setup(void)
	411	{
	412	/* enable MTU2 clock */
	413	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
	414
	415	early_platform_add_devices(sh7201_early_devices,
	416	ARRAY_SIZE(sh7201_early_devices));
	417	}