[mirror_ubuntu-artful-kernel.git] / arch / sh / kernel / cpu / sh3 / setup-sh770x.c

/*
 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
 *
 *  Copyright (C) 2007  Magnus Damm
 *  Copyright (C) 2009  Paul Mundt
 *
 * Based on setup-sh7709.c
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <cpu/serial.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
	PINT07, PINT815,
	DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
	LCDC, PCC0, PCC1,
	TMU0, TMU1, TMU2,
	RTC, WDT, REF,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
	INTC_VECT(RTC, 0x4c0),
	INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
	INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(REF, 0x580),
	INTC_VECT(REF, 0x5a0),
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	/* IRQ0->5 are handled in setup-sh3.c */
	INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
	INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
	INTC_VECT(ADC_ADI, 0x980),
	INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
	INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
	INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
	INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
	INTC_VECT(LCDC, 0x9a0),
	INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
#endif
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
	{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
	{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
#endif
};

static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
			 NULL, prio_registers, NULL);

static struct resource rtc_resources[] = {
	[0] =	{
		.start	= 0xfffffec0,
		.end	= 0xfffffec0 + 0x1e,
		.flags  = IORESOURCE_IO,
	},
	[1] =	{
		.start	= 20,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xfffffe80,
	.port_reg	= 0xa4000136,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_TE | SCSCR_RE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCI,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x4E0)),
	.ops		= &sh770x_sci_port_ops,
	.regshift	= 1,
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xa4000150,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_TE | SCSCR_RE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_SCIF,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x900)),
	.ops		= &sh770x_sci_port_ops,
	.regtype	= SCIx_SH3_SCIF_REGTYPE,
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xa4000140,
	.port_reg	= SCIx_NOT_SUPPORTED,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_TE | SCSCR_RE,
	.scbrr_algo_id	= SCBRR_ALGO_2,
	.type		= PORT_IRDA,
	.irqs		= SCIx_IRQ_MUXED(evt2irq(0x880)),
	.ops		= &sh770x_sci_port_ops,
	.regshift	= 1,
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};
#endif

static struct sh_timer_config tmu0_platform_data = {
	.channel_offset = 0x02,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.start	= 0xfffffe94,
		.end	= 0xfffffe9f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 16,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.channel_offset = 0xe,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.start	= 0xfffffea0,
		.end	= 0xfffffeab,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 17,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.channel_offset = 0x1a,
	.timer_bit = 2,
};

static struct resource tmu2_resources[] = {
	[0] = {
		.start	= 0xfffffeac,
		.end	= 0xfffffebb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 18,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct platform_device *sh770x_devices[] __initdata = {
	&scif0_device,
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	&scif1_device,
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	&scif2_device,
#endif
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&rtc_device,
};

static int __init sh770x_devices_setup(void)
{
	return platform_add_devices(sh770x_devices,
		ARRAY_SIZE(sh770x_devices));
}
arch_initcall(sh770x_devices_setup);

static struct platform_device *sh770x_early_devices[] __initdata = {
	&scif0_device,
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	&scif1_device,
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	&scif2_device,
#endif
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh770x_early_devices,
				   ARRAY_SIZE(sh770x_early_devices));
}

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
    defined(CONFIG_CPU_SUBTYPE_SH7709)
	plat_irq_setup_sh3();
#endif
}
Commit	Line	Data
ec58f1f3 MD	1	/*
	2	* SH3 Setup code for SH7706, SH7707, SH7708, SH7709
	3	*
	4	* Copyright (C) 2007 Magnus Damm
592acbda	5	* Copyright (C) 2009 Paul Mundt
ec58f1f3 MD	6	*
	7	* Based on setup-sh7709.c
	8	*
	9	* Copyright (C) 2006 Paul Mundt
	10	*
	11	* This file is subject to the terms and conditions of the GNU General Public
	12	* License. See the file "COPYING" in the main directory of this archive
	13	* for more details.
	14	*/
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/irq.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/serial.h>
96de1a8f	20	#include <linux/serial_sci.h>
c8a9011b	21	#include <linux/sh_timer.h>
61a6976b	22	#include <cpu/serial.h>
ec58f1f3 MD	23
	24	enum {
	25	UNUSED = 0,
	26
	27	/* interrupt sources */
	28	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
	29	PINT07, PINT815,
592acbda	30	DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
1301e715	31	LCDC, PCC0, PCC1,
592acbda PM	32	TMU0, TMU1, TMU2,
592acbda PM	33	RTC, WDT, REF,
ec58f1f3 MD	34	};
ec58f1f3 MD	35
5c37e025	36	static struct intc_vect vectors[] __initdata = {
ec58f1f3	37	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
592acbda PM	38	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
	39	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
	40	INTC_VECT(RTC, 0x4c0),
	41	INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
	42	INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
ec58f1f3	43	INTC_VECT(WDT, 0x560),
592acbda PM	44	INTC_VECT(REF, 0x580),
592acbda PM	45	INTC_VECT(REF, 0x5a0),
ec58f1f3 MD	46	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	47	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	48	defined(CONFIG_CPU_SUBTYPE_SH7709)
a276e588	49	/* IRQ0->5 are handled in setup-sh3.c */
592acbda PM	50	INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
592acbda PM	51	INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
ec58f1f3	52	INTC_VECT(ADC_ADI, 0x980),
592acbda PM	53	INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
592acbda PM	54	INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
ec58f1f3 MD	55	#endif
	56	#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	57	defined(CONFIG_CPU_SUBTYPE_SH7709)
	58	INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
592acbda PM	59	INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
592acbda PM	60	INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
ec58f1f3	61	#endif
1301e715 MD	62	#if defined(CONFIG_CPU_SUBTYPE_SH7707)
	63	INTC_VECT(LCDC, 0x9a0),
	64	INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
	65	#endif
ec58f1f3 MD	66	};
ec58f1f3 MD	67
5c37e025	68	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	69	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
6ef5fb2c MD	70	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
ec58f1f3 MD	71	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	72	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	73	defined(CONFIG_CPU_SUBTYPE_SH7709)
6ef5fb2c MD	74	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
	75	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
	76	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
ec58f1f3 MD	77	#endif
	78	#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	79	defined(CONFIG_CPU_SUBTYPE_SH7709)
6ef5fb2c MD	80	{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
6ef5fb2c MD	81	{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
ec58f1f3	82	#endif
1301e715	83	#if defined(CONFIG_CPU_SUBTYPE_SH7707)
6ef5fb2c	84	{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
1301e715	85	#endif
ec58f1f3 MD	86	};
ec58f1f3 MD	87
592acbda	88	static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
7f3edee8	89	NULL, prio_registers, NULL);
ec58f1f3	90
ec58f1f3 MD	91	static struct resource rtc_resources[] = {
	92	[0] = {
	93	.start = 0xfffffec0,
	94	.end = 0xfffffec0 + 0x1e,
	95	.flags = IORESOURCE_IO,
	96	},
	97	[1] = {
b7fd0956	98	.start = 20,
ec58f1f3 MD	99	.flags = IORESOURCE_IRQ,
	100	},
	101	};
	102
	103	static struct platform_device rtc_device = {
	104	.name = "sh-rtc",
	105	.id = -1,
	106	.num_resources = ARRAY_SIZE(rtc_resources),
	107	.resource = rtc_resources,
	108	};
	109
44658dfb MD	110	static struct plat_sci_port scif0_platform_data = {
44658dfb MD	111	.mapbase = 0xfffffe80,
514820eb	112	.port_reg = 0xa4000136,
44658dfb	113	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	114	.scscr = SCSCR_TE \| SCSCR_RE,
f43dc23d PM	115	.scbrr_algo_id = SCBRR_ALGO_2,
44658dfb	116	.type = PORT_SCI,
545f3bcf	117	.irqs = SCIx_IRQ_MUXED(evt2irq(0x4E0)),
61a6976b PM	118	.ops = &sh770x_sci_port_ops,
61a6976b PM	119	.regshift = 1,
44658dfb MD	120	};
	121
	122	static struct platform_device scif0_device = {
	123	.name = "sh-sci",
	124	.id = 0,
	125	.dev = {
	126	.platform_data = &scif0_platform_data,
ec58f1f3	127	},
44658dfb	128	};
ec58f1f3 MD	129	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	130	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	131	defined(CONFIG_CPU_SUBTYPE_SH7709)
44658dfb MD	132	static struct plat_sci_port scif1_platform_data = {
	133	.mapbase = 0xa4000150,
	134	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	135	.scscr = SCSCR_TE \| SCSCR_RE,
f43dc23d PM	136	.scbrr_algo_id = SCBRR_ALGO_2,
44658dfb	137	.type = PORT_SCIF,
545f3bcf	138	.irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
61a6976b PM	139	.ops = &sh770x_sci_port_ops,
61a6976b PM	140	.regtype = SCIx_SH3_SCIF_REGTYPE,
44658dfb MD	141	};
	142
	143	static struct platform_device scif1_device = {
	144	.name = "sh-sci",
	145	.id = 1,
	146	.dev = {
	147	.platform_data = &scif1_platform_data,
ec58f1f3	148	},
44658dfb	149	};
ec58f1f3 MD	150	#endif
	151	#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	152	defined(CONFIG_CPU_SUBTYPE_SH7709)
44658dfb MD	153	static struct plat_sci_port scif2_platform_data = {
44658dfb MD	154	.mapbase = 0xa4000140,
61a6976b	155	.port_reg = SCIx_NOT_SUPPORTED,
44658dfb	156	.flags = UPF_BOOT_AUTOCONF,
f43dc23d PM	157	.scscr = SCSCR_TE \| SCSCR_RE,
f43dc23d PM	158	.scbrr_algo_id = SCBRR_ALGO_2,
44658dfb	159	.type = PORT_IRDA,
545f3bcf	160	.irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
61a6976b PM	161	.ops = &sh770x_sci_port_ops,
61a6976b PM	162	.regshift = 1,
ec58f1f3 MD	163	};
ec58f1f3 MD	164
44658dfb	165	static struct platform_device scif2_device = {
ec58f1f3	166	.name = "sh-sci",
44658dfb	167	.id = 2,
ec58f1f3	168	.dev = {
44658dfb	169	.platform_data = &scif2_platform_data,
ec58f1f3 MD	170	},
ec58f1f3 MD	171	};
44658dfb	172	#endif
ec58f1f3	173
c8a9011b	174	static struct sh_timer_config tmu0_platform_data = {
c8a9011b MD	175	.channel_offset = 0x02,
c8a9011b MD	176	.timer_bit = 0,
c8a9011b MD	177	.clockevent_rating = 200,
	178	};
	179
	180	static struct resource tmu0_resources[] = {
	181	[0] = {
c8a9011b MD	182	.start = 0xfffffe94,
	183	.end = 0xfffffe9f,
	184	.flags = IORESOURCE_MEM,
	185	},
	186	[1] = {
	187	.start = 16,
	188	.flags = IORESOURCE_IRQ,
	189	},
	190	};
	191
	192	static struct platform_device tmu0_device = {
	193	.name = "sh_tmu",
	194	.id = 0,
	195	.dev = {
	196	.platform_data = &tmu0_platform_data,
	197	},
	198	.resource = tmu0_resources,
	199	.num_resources = ARRAY_SIZE(tmu0_resources),
	200	};
	201
	202	static struct sh_timer_config tmu1_platform_data = {
c8a9011b MD	203	.channel_offset = 0xe,
c8a9011b MD	204	.timer_bit = 1,
c8a9011b MD	205	.clocksource_rating = 200,
	206	};
	207
	208	static struct resource tmu1_resources[] = {
	209	[0] = {
c8a9011b MD	210	.start = 0xfffffea0,
	211	.end = 0xfffffeab,
	212	.flags = IORESOURCE_MEM,
	213	},
	214	[1] = {
	215	.start = 17,
	216	.flags = IORESOURCE_IRQ,
	217	},
	218	};
	219
	220	static struct platform_device tmu1_device = {
	221	.name = "sh_tmu",
	222	.id = 1,
	223	.dev = {
	224	.platform_data = &tmu1_platform_data,
	225	},
	226	.resource = tmu1_resources,
	227	.num_resources = ARRAY_SIZE(tmu1_resources),
	228	};
	229
	230	static struct sh_timer_config tmu2_platform_data = {
c8a9011b MD	231	.channel_offset = 0x1a,
c8a9011b MD	232	.timer_bit = 2,
c8a9011b MD	233	};
	234
	235	static struct resource tmu2_resources[] = {
	236	[0] = {
c8a9011b MD	237	.start = 0xfffffeac,
	238	.end = 0xfffffebb,
	239	.flags = IORESOURCE_MEM,
	240	},
	241	[1] = {
	242	.start = 18,
	243	.flags = IORESOURCE_IRQ,
	244	},
	245	};
	246
	247	static struct platform_device tmu2_device = {
	248	.name = "sh_tmu",
	249	.id = 2,
	250	.dev = {
	251	.platform_data = &tmu2_platform_data,
	252	},
	253	.resource = tmu2_resources,
	254	.num_resources = ARRAY_SIZE(tmu2_resources),
	255	};
	256
ec58f1f3	257	static struct platform_device *sh770x_devices[] __initdata = {
44658dfb MD	258	&scif0_device,
	259	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	260	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	261	defined(CONFIG_CPU_SUBTYPE_SH7709)
	262	&scif1_device,
	263	#endif
	264	#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	265	defined(CONFIG_CPU_SUBTYPE_SH7709)
	266	&scif2_device,
	267	#endif
c8a9011b MD	268	&tmu0_device,
	269	&tmu1_device,
	270	&tmu2_device,
ec58f1f3 MD	271	&rtc_device,
	272	};
	273
	274	static int __init sh770x_devices_setup(void)
	275	{
	276	return platform_add_devices(sh770x_devices,
	277	ARRAY_SIZE(sh770x_devices));
	278	}
ba9a6337	279	arch_initcall(sh770x_devices_setup);
ec58f1f3	280
c8a9011b	281	static struct platform_device *sh770x_early_devices[] __initdata = {
44658dfb MD	282	&scif0_device,
	283	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	284	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	285	defined(CONFIG_CPU_SUBTYPE_SH7709)
	286	&scif1_device,
	287	#endif
	288	#if defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	289	defined(CONFIG_CPU_SUBTYPE_SH7709)
	290	&scif2_device,
	291	#endif
c8a9011b MD	292	&tmu0_device,
	293	&tmu1_device,
	294	&tmu2_device,
	295	};
	296
	297	void __init plat_early_device_setup(void)
	298	{
	299	early_platform_add_devices(sh770x_early_devices,
	300	ARRAY_SIZE(sh770x_early_devices));
	301	}
	302
a276e588	303	void __init plat_irq_setup(void)
ec58f1f3	304	{
a276e588	305	register_intc_controller(&intc_desc);
ec58f1f3 MD	306	#if defined(CONFIG_CPU_SUBTYPE_SH7706) \|\| \
	307	defined(CONFIG_CPU_SUBTYPE_SH7707) \|\| \
	308	defined(CONFIG_CPU_SUBTYPE_SH7709)
a276e588	309	plat_irq_setup_sh3();
ec58f1f3	310	#endif
ec58f1f3	311	}